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[/] [connect-6/] [trunk/] [XILINX/] [BUILD_SCC_SRCH/] [SP6/] [bram_based_stream_buffer.v] - Blame information for rev 17

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// Copyright (c) 2011 Synopsys, Inc.  All rights reserved.
//
//
// $Revision: 1.8 $
 
 
`timescale 1ns / 1ps
 
`ifdef PICO_CLOCK_EDGE
`else
   `define PICO_CLOCK_EDGE posedge
`endif
`ifdef PICO_CLOCK_SENSITIVITY
`else
   `define PICO_CLOCK_SENSITIVITY clk
`endif
`ifdef PICO_RESET_SENSITIVITY
`else
   `define PICO_RESET_SENSITIVITY
`endif
`ifdef PICO_RESET_SENSITIVITY2
`else
   `define PICO_RESET_SENSITIVITY2 reset
`endif
 
`timescale 1 ns / 10 ps
 
module bram_based_stream_buffer (clk, indata, outdata, store_ready, load_ready,  reset, flush, load_req, store_req );
 
     parameter width = 48;
     parameter depth = 800;
     parameter awidth = clogb2(depth);
 
input clk, load_ready, store_ready, reset, flush;
wire  clk, load_ready, store_ready, reset, flush;
 
input [width-1:0] indata;
wire [width-1:0] indata;
 
output  load_req, store_req;
wire    load_req, store_req;
 
output [width-1:0] outdata;
wire   [width-1:0] outdata;
 
 
function integer clogb2(input integer depth);
 begin
     for (clogb2=0; depth>0; clogb2=clogb2+1)
          depth= depth>>1;
     end
 endfunction
 
   // 0in assert -var (depth >= 1)
   // coverage off
   // pragma coverage off
   // VCS coverage off
   // synopsys translate_off
   initial begin
      if ( depth < 1 ) begin
        $display ("ERROR::::");
        $display ("mc_log:  ERROR:  bram_based_stream_buffer of depth %0d in %m. This is unsupported.Stopping simulation",depth);
        $display ("END ERROR");
        $finish;
      end
   end
   // synopsys translate_on
   // VCS coverage on
   // pragma coverage on
   // coverage on
 
reg [awidth-1:0] read_addr_ff, next_read_addr_ff, write_addr_ff;
reg [awidth-1:0]  count_ff ;
reg   full_ff, not_empty_ff, onefull_ff, init_ff;
 
reg    [width-1:0] bypass_reg_ff;
reg    bypass_reg_valid_ff;
 
wire   [width-1:0] bram_outdata;
wire   addq_only, shiftq_only, shiftq_addq, mem_is_empty;
 
wire addq = load_ready;
wire shiftq = store_ready;
 
wire  full_mem = full_ff;
assign mem_is_empty = ~not_empty_ff;
 
assign addq_only = (addq & !full_ff & (!shiftq |(shiftq & mem_is_empty)));
assign shiftq_only = (shiftq & !mem_is_empty & (!addq | (addq & full_mem)) );
assign shiftq_addq = (shiftq & addq & not_empty_ff & !full_mem);
 
wire rreq, wreq;
 
assign rreq = not_empty_ff;
assign wreq = addq & !full_mem;
assign load_req = !full_mem;
assign store_req = !mem_is_empty;
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY  `PICO_RESET_SENSITIVITY ) begin
   if (`PICO_RESET_SENSITIVITY2) begin
       not_empty_ff <= 1'b0;
       full_ff      <= 1'b0;
       init_ff      <= 1'b0;
   end
   else if (flush) begin
       not_empty_ff <= 1'b0;
       full_ff      <= 1'b0;
       init_ff      <= 1'b0;
   end
   else begin
        init_ff      <= 1'b1;
      if (addq & mem_is_empty) begin
              not_empty_ff <= 1'b1;
      end
      else if (shiftq & !addq & onefull_ff)  begin
              not_empty_ff <= 1'b0;
      end
 
      if (addq_only & (count_ff == depth-1))  full_ff <= 1'b1;
      else if (shiftq_only)   full_ff <= 1'b0;
 
   end
end
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY  `PICO_RESET_SENSITIVITY ) begin
   if (`PICO_RESET_SENSITIVITY2) begin
       onefull_ff   <= 1'b0;
   end
   else if (flush) begin
       onefull_ff   <= 1'b0;
   end
   else begin
      if (addq_only) begin
         if (mem_is_empty) begin
              onefull_ff <= 1'b1;
         end
         else begin
              onefull_ff <= 1'b0;
         end
      end
      else if (shiftq_only)  begin
         if (onefull_ff)  begin
              onefull_ff   <= 1'b0;
         end
         else if (count_ff == 2'b10) begin
              onefull_ff   <= 1'b1;
         end
      end
   end
end
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY  `PICO_RESET_SENSITIVITY ) begin
 if (`PICO_RESET_SENSITIVITY2) begin
     read_addr_ff <= {awidth{1'b0}};
     next_read_addr_ff <= {awidth{1'b0}};
 end
 else if (flush)  begin
     read_addr_ff <= {awidth{1'b0}};
     next_read_addr_ff <= {awidth{1'b0}};
 end
 else begin
 
   if ( (shiftq & not_empty_ff) | ~init_ff ) begin
         read_addr_ff <= next_read_addr_ff;
     if (next_read_addr_ff == depth-1) begin
         next_read_addr_ff <= {awidth{1'b0}};
     end
     else begin
         next_read_addr_ff <= next_read_addr_ff + 1'b1;
     end
   end
 end
end
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY  `PICO_RESET_SENSITIVITY ) begin
 if (`PICO_RESET_SENSITIVITY2) begin
     write_addr_ff <= {awidth{1'b0}};
 end
 else if (flush) begin
     write_addr_ff <= {awidth{1'b0}};
 end
 else begin
    if (wreq) begin
       if (write_addr_ff == depth-1)
         write_addr_ff <= {awidth{1'b0}};
       else
         write_addr_ff <= write_addr_ff + 1'b1;
   end
 end
end
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY  `PICO_RESET_SENSITIVITY ) begin
  if (`PICO_RESET_SENSITIVITY2) begin
       count_ff <= {awidth{1'b0}};
  end
  else if (flush) begin
       count_ff <= {awidth{1'b0}};
  end
  else begin
     if (addq_only) begin
       count_ff <= count_ff + 1'b1;
     end
     else if (shiftq_only) begin
       count_ff <= count_ff - 1'b1;
     end
  end
end
 
  always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY) begin
      if (`PICO_RESET_SENSITIVITY2)
      begin
         bypass_reg_valid_ff <= 1'b0;
         bypass_reg_ff <= {(width){1'b0}};
      end
      else if (flush)
      begin
         bypass_reg_valid_ff <= 1'b0;
      end
      else
      begin
        bypass_reg_valid_ff <= addq & ( mem_is_empty | (shiftq & onefull_ff) );
        bypass_reg_ff <= indata;
      end
   end
   assign outdata = bypass_reg_valid_ff ? bypass_reg_ff[width-1:0] : bram_outdata[width-1:0];
 
   wire [awidth-1:0] speculative_read_addr = (shiftq & not_empty_ff) ? next_read_addr_ff : read_addr_ff;
 
   RA2SH #(.dwidth(width), .depth(depth), .awidth(awidth) ) fifo_storage(
                         .QA(),
                         .CLKA(clk),
                         .CENA(~wreq),
                         .WENA(1'b0),
                         .AA(write_addr_ff[awidth-1:0]),
                         .DA(indata[width-1:0]),
                         .QB(bram_outdata[width-1:0]),
                         .CLKB(clk),
                         .CENB(~rreq),
                         .WENB(1'b1),
                         .AB(speculative_read_addr),
                         .DB({width{1'b0}}));
 
 
endmodule

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[/] [connect-6/] [trunk/] [XILINX/] [BUILD_SCC_SRCH/] [SP6/] [bram_based_stream_buffer.v] - Blame information for rev 17

Line No.	Rev	Author	Line
1	17	sumanta.ch	`// Copyright (c) 2011 Synopsys, Inc. All rights reserved.`
2			`//`
3			`//`
4			`// $Revision: 1.8 $`
5
6
7			`timescale 1ns / 1ps
8
9			`ifdef PICO_CLOCK_EDGE
10			`else
11			`define PICO_CLOCK_EDGE posedge
12			`endif
13			`ifdef PICO_CLOCK_SENSITIVITY
14			`else
15			`define PICO_CLOCK_SENSITIVITY clk
16			`endif
17			`ifdef PICO_RESET_SENSITIVITY
18			`else
19			`define PICO_RESET_SENSITIVITY
20			`endif
21			`ifdef PICO_RESET_SENSITIVITY2
22			`else
23			`define PICO_RESET_SENSITIVITY2 reset
24			`endif
25
26			`timescale 1 ns / 10 ps
27
28			`module bram_based_stream_buffer (clk, indata, outdata, store_ready, load_ready, reset, flush, load_req, store_req );`
29
30			`parameter width = 48;`
31			`parameter depth = 800;`
32			`parameter awidth = clogb2(depth);`
33
34			`input clk, load_ready, store_ready, reset, flush;`
35			`wire clk, load_ready, store_ready, reset, flush;`
36
37			`input [width-1:0] indata;`
38			`wire [width-1:0] indata;`
39
40			`output load_req, store_req;`
41			`wire load_req, store_req;`
42
43			`output [width-1:0] outdata;`
44			`wire [width-1:0] outdata;`
45
46
47			`function integer clogb2(input integer depth);`
48			`begin`
49			`for (clogb2=0; depth>0; clogb2=clogb2+1)`
50			`depth= depth>>1;`
51			`end`
52			`endfunction`
53
54			`// 0in assert -var (depth >= 1)`
55			`// coverage off`
56			`// pragma coverage off`
57			`// VCS coverage off`
58			`// synopsys translate_off`
59			`initial begin`
60			`if ( depth < 1 ) begin`
61			`$display ("ERROR::::");`
62			`$display ("mc_log: ERROR: bram_based_stream_buffer of depth %0d in %m. This is unsupported.Stopping simulation",depth);`
63			`$display ("END ERROR");`
64			`$finish;`
65			`end`
66			`end`
67			`// synopsys translate_on`
68			`// VCS coverage on`
69			`// pragma coverage on`
70			`// coverage on`
71
72			`reg [awidth-1:0] read_addr_ff, next_read_addr_ff, write_addr_ff;`
73			`reg [awidth-1:0] count_ff ;`
74			`reg full_ff, not_empty_ff, onefull_ff, init_ff;`
75
76			`reg [width-1:0] bypass_reg_ff;`
77			`reg bypass_reg_valid_ff;`
78
79			`wire [width-1:0] bram_outdata;`
80			`wire addq_only, shiftq_only, shiftq_addq, mem_is_empty;`
81
82			`wire addq = load_ready;`
83			`wire shiftq = store_ready;`
84
85			`wire full_mem = full_ff;`
86			`assign mem_is_empty = ~not_empty_ff;`
87
88			`assign addq_only = (addq & !full_ff & (!shiftq \|(shiftq & mem_is_empty)));`
89			`assign shiftq_only = (shiftq & !mem_is_empty & (!addq \| (addq & full_mem)) );`
90			`assign shiftq_addq = (shiftq & addq & not_empty_ff & !full_mem);`
91
92			`wire rreq, wreq;`
93
94			`assign rreq = not_empty_ff;`
95			`assign wreq = addq & !full_mem;`
96			`assign load_req = !full_mem;`
97			`assign store_req = !mem_is_empty;`
98
99			always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
100			if (`PICO_RESET_SENSITIVITY2) begin
101			`not_empty_ff <= 1'b0;`
102			`full_ff <= 1'b0;`
103			`init_ff <= 1'b0;`
104			`end`
105			`else if (flush) begin`
106			`not_empty_ff <= 1'b0;`
107			`full_ff <= 1'b0;`
108			`init_ff <= 1'b0;`
109			`end`
110			`else begin`
111			`init_ff <= 1'b1;`
112			`if (addq & mem_is_empty) begin`
113			`not_empty_ff <= 1'b1;`
114			`end`
115			`else if (shiftq & !addq & onefull_ff) begin`
116			`not_empty_ff <= 1'b0;`
117			`end`
118
119			`if (addq_only & (count_ff == depth-1)) full_ff <= 1'b1;`
120			`else if (shiftq_only) full_ff <= 1'b0;`
121
122			`end`
123			`end`
124
125			always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
126			if (`PICO_RESET_SENSITIVITY2) begin
127			`onefull_ff <= 1'b0;`
128			`end`
129			`else if (flush) begin`
130			`onefull_ff <= 1'b0;`
131			`end`
132			`else begin`
133			`if (addq_only) begin`
134			`if (mem_is_empty) begin`
135			`onefull_ff <= 1'b1;`
136			`end`
137			`else begin`
138			`onefull_ff <= 1'b0;`
139			`end`
140			`end`
141			`else if (shiftq_only) begin`
142			`if (onefull_ff) begin`
143			`onefull_ff <= 1'b0;`
144			`end`
145			`else if (count_ff == 2'b10) begin`
146			`onefull_ff <= 1'b1;`
147			`end`
148			`end`
149			`end`
150			`end`
151
152			always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
153			if (`PICO_RESET_SENSITIVITY2) begin
154			`read_addr_ff <= {awidth{1'b0}};`
155			`next_read_addr_ff <= {awidth{1'b0}};`
156			`end`
157			`else if (flush) begin`
158			`read_addr_ff <= {awidth{1'b0}};`
159			`next_read_addr_ff <= {awidth{1'b0}};`
160			`end`
161			`else begin`
162
163			`if ( (shiftq & not_empty_ff) \| ~init_ff ) begin`
164			`read_addr_ff <= next_read_addr_ff;`
165			`if (next_read_addr_ff == depth-1) begin`
166			`next_read_addr_ff <= {awidth{1'b0}};`
167			`end`
168			`else begin`
169			`next_read_addr_ff <= next_read_addr_ff + 1'b1;`
170			`end`
171			`end`
172			`end`
173			`end`
174
175			always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
176			if (`PICO_RESET_SENSITIVITY2) begin
177			`write_addr_ff <= {awidth{1'b0}};`
178			`end`
179			`else if (flush) begin`
180			`write_addr_ff <= {awidth{1'b0}};`
181			`end`
182			`else begin`
183			`if (wreq) begin`
184			`if (write_addr_ff == depth-1)`
185			`write_addr_ff <= {awidth{1'b0}};`
186			`else`
187			`write_addr_ff <= write_addr_ff + 1'b1;`
188			`end`
189			`end`
190			`end`
191
192			always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
193			if (`PICO_RESET_SENSITIVITY2) begin
194			`count_ff <= {awidth{1'b0}};`
195			`end`
196			`else if (flush) begin`
197			`count_ff <= {awidth{1'b0}};`
198			`end`
199			`else begin`
200			`if (addq_only) begin`
201			`count_ff <= count_ff + 1'b1;`
202			`end`
203			`else if (shiftq_only) begin`
204			`count_ff <= count_ff - 1'b1;`
205			`end`
206			`end`
207			`end`
208
209			always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY) begin
210			if (`PICO_RESET_SENSITIVITY2)
211			`begin`
212			`bypass_reg_valid_ff <= 1'b0;`
213			`bypass_reg_ff <= {(width){1'b0}};`
214			`end`
215			`else if (flush)`
216			`begin`
217			`bypass_reg_valid_ff <= 1'b0;`
218			`end`
219			`else`
220			`begin`
221			`bypass_reg_valid_ff <= addq & ( mem_is_empty \| (shiftq & onefull_ff) );`
222			`bypass_reg_ff <= indata;`
223			`end`
224			`end`
225			`assign outdata = bypass_reg_valid_ff ? bypass_reg_ff[width-1:0] : bram_outdata[width-1:0];`
226
227			`wire [awidth-1:0] speculative_read_addr = (shiftq & not_empty_ff) ? next_read_addr_ff : read_addr_ff;`
228
229			`RA2SH #(.dwidth(width), .depth(depth), .awidth(awidth) ) fifo_storage(`
230			`.QA(),`
231			`.CLKA(clk),`
232			`.CENA(~wreq),`
233			`.WENA(1'b0),`
234			`.AA(write_addr_ff[awidth-1:0]),`
235			`.DA(indata[width-1:0]),`
236			`.QB(bram_outdata[width-1:0]),`
237			`.CLKB(clk),`
238			`.CENB(~rreq),`
239			`.WENB(1'b1),`
240			`.AB(speculative_read_addr),`
241			`.DB({width{1'b0}}));`
242
243
244			`endmodule`