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[/] [connect-6/] [trunk/] [XILINX/] [BUILD_SCC_SRCH/] [SP6/] [constraints.sdc] - Blame information for rev 17

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Line No. Rev Author Line
1 17 sumanta.ch
# clocks
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create_clock -period 30.0 -name clk [get_ports OSC_27]
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# input/output delays
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