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[/] [connect-6/] [trunk/] [XILINX/] [BUILD_SCC_SRCH/] [SP6/] [safe_test.vhd] - Blame information for rev 17

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library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_bit.all;
use ieee.std_logic_arith.all;
 
 
 
entity safe_test is
generic(INPUT_LENGTH:integer:=6;OUTPUT_LENGTH:integer:=6);
        port(
                clk:in std_ulogic;
                rst:in std_ulogic;
                --Config Signals
                init_out:out std_ulogic;
                config_mode_out:out std_ulogic;
                config_out0:out std_ulogic;
                config_out1:out std_ulogic;
                config_ack_in:in std_ulogic;
                --DE2 Control SIgnals
                msg_out:out std_ulogic_vector(2 downto 0);
                Ack_count_out:out std_logic_vector(31 downto 0);
                cmd:in std_ulogic_vector(4 downto 0);
                --SRAM
                SRAM_DATA_OUT: OUT std_logic_vector(15 downto 0);
                SRAM_DATA: in std_logic_vector(15 downto 0);
                SRAM_ADDR: out std_logic_vector(23 downto 0);
                SRAM_WEN:  out std_logic;
                SRAM_OEN:  out std_logic;
                --SDRAM
                SDRAM_DATA: out std_logic_vector(15 downto 0);
                SDRAM_ADDR: out std_logic_vector(23 downto 0);
                SDRAM_WEN:  out std_logic;
                SDRAM_OEN:  out std_logic;
                --Result Vectors
                INPUT_ASYNC_0: in std_ulogic_vector(INPUT_LENGTH-1 downto 0);
                INPUT_ASYNC_1: in std_ulogic_vector(INPUT_LENGTH-1 downto 0);
                INPUT_ASYNC_ACKOUT: out std_ulogic_vector(INPUT_LENGTH-1 downto 0);
                --Test Vectors
                OUTPUT_ASYNC_0: out std_ulogic_vector(OUTPUT_LENGTH-1 downto 0);
                OUTPUT_ASYNC_1: out std_ulogic_vector(OUTPUT_LENGTH-1 downto 0);
                OUTPUT_ASYNC_ACKIN: in std_ulogic_vector(OUTPUT_LENGTH-1 downto 0);
 
                --Trigger for oscilloscope
                trigger: out std_ulogic
 
                );
end entity safe_test;
 
 
architecture machine_a_etat of safe_test is
component S_TO_AS_CONFIG is
generic (BEGIN_ADDR:integer:=0;END_ADDR:integer:=0;LENGTH:integer:=16);
        port(
                clk:in std_ulogic;
                rst:in std_ulogic;
 
                SRAM_DATA_OUT: out std_logic_vector(15 downto 0);
                SRAM_DATA: in std_logic_vector(15 downto 0);
                SRAM_ADDR: out std_logic_vector(23 downto 0);
                SRAM_WEN:  out std_logic;
                SRAM_OEN:  out std_logic;
 
                AS_OUT0: out std_ulogic;
                AS_OUT1: out std_ulogic;
                ACK_IN:  in std_ulogic;
 
                config_enable: in std_ulogic; -- Command from the state_machine up there
                ACK_COUNT_OUT: out std_logic_vector(31 downto 0)
                );
end component S_TO_AS_CONFIG;
 
component AS_TO_S_VECTOR is
generic (BEGIN_ADDR:integer:=0;END_ADDR:integer:=0;LENGTH:integer:=16);
        port(
                clk:in std_ulogic;
                rst:in std_ulogic;
 
                SRAM_DATA: out std_logic_vector(15 downto 0);
                SRAM_ADDR: out std_logic_vector(23 downto 0);
                SRAM_WEN:  out std_logic;
                SRAM_OEN:  out std_logic;
 
                I_ASYNC_0: in std_ulogic_vector(LENGTH-1 downto 0);
                I_ASYNC_1: in std_ulogic_vector(LENGTH-1 downto 0);
                I_ASYNC_ACK_OUT:  out std_ulogic_vector(LENGTH-1 downto 0);
 
                vector_enable: in std_ulogic; -- Command from the state_machine up there
                ACK_COUNT_OUT: out std_logic_vector(31 downto 0)
                );
end component AS_TO_S_VECTOR;
 
component S_TO_AS_VECTOR is
generic (BEGIN_ADDR:integer:=0;END_ADDR:integer:=0;LENGTH:integer:=16);
        port(
                clk:in std_ulogic;
                rst:in std_ulogic;
                trigger:out std_ulogic;
 
                SRAM_DATA: in std_logic_vector(15 downto 0);
                SRAM_ADDR: out std_logic_vector(23 downto 0);
                SRAM_WEN:  out std_logic;
                SRAM_OEN:  out std_logic;
 
                O_ASYNC_0: out std_ulogic_vector(LENGTH-1 downto 0);
                O_ASYNC_1: out std_ulogic_vector(LENGTH-1 downto 0);
                O_ASYNC_ACK_IN:  in std_ulogic_vector(LENGTH-1 downto 0);
 
                vector_enable: in std_ulogic; -- Command from the state_machine up there
                ACK_COUNT_OUT: out std_logic_vector(31 downto 0)
                );
end component S_TO_AS_VECTOR;
 
--type STATE_TYPE is(IDLE,INIT,CONFIG,RUNNING);
--signal state,next_state:STATE_TYPE;
signal msg_out_int:std_ulogic_vector(2 downto 0);
signal count:integer range 0 to integer'high;
signal count_in,count_out:std_logic_vector(31 downto 0);
signal config_enable,run_enable,safe_rst:std_ulogic;
signal SRAM_DATA_TEST,SRAM_DATA_CONFIG:std_logic_vector(15 downto 0);
signal SRAM_ADDR_TEST,SRAM_ADDR_CONFIG:std_logic_vector(23 downto 0);
signal SRAM_WEN_CONFIG,SRAM_WEN_TEST,SRAM_OEN_CONFIG,SRAM_OEN_TEST:std_logic;
signal trig_count:integer range 0 to integer'high;
begin
        msg_out<=msg_out_int;
        TRANSLATE: S_TO_AS_CONFIG
                                generic map(BEGIN_ADDR=>0,END_ADDR=>293,LENGTH=>1)
                                port map(
                                        clk=>clk,
                                        rst=>rst,
 
                                        SRAM_DATA_OUT=>SRAM_DATA_OUT,
                                        SRAM_DATA=>SRAM_DATA,
                                        SRAM_ADDR=>SRAM_ADDR_CONFIG,
                                        SRAM_WEN=>SRAM_WEN_CONFIG,
                                        SRAM_OEN=>SRAM_OEN_CONFIG,
 
                                        AS_OUT0=>config_out0,
                                        AS_OUT1=>config_out1,
                                        ACK_IN=>config_ack_in,
 
                                        config_enable=>config_enable,
                                        ACK_COUNT_OUT=>Ack_count_out);
 
 
        TRANSLATE_S_TO_AS:S_TO_AS_VECTOR
        generic map(BEGIN_ADDR=>4096,END_ADDR=>4159,LENGTH=>OUTPUT_LENGTH)
                port map(
                        clk=>clk,
                        rst=>safe_rst,
                        trigger=>trigger,
 
                        SRAM_DATA=>SRAM_DATA,
                        SRAM_ADDR=>SRAM_ADDR_TEST,
                        SRAM_WEN=>SRAM_WEN_TEST,
                        SRAM_OEN=>SRAM_OEN_TEST,
 
                        O_ASYNC_0=>OUTPUT_ASYNC_0,
                        O_ASYNC_1=>OUTPUT_ASYNC_1,
                        O_ASYNC_ACK_IN=>OUTPUT_ASYNC_ACKIN,
 
                        vector_enable=>run_enable,
                        ACK_COUNT_OUT=>count_out
                        );
        TRANSLATE_AS_TO_S:AS_TO_S_VECTOR
        generic map(BEGIN_ADDR=>0,END_ADDR=>63,LENGTH=>INPUT_LENGTH)
                port map(
                        clk=>clk,
                        rst=>safe_rst,
 
                        SRAM_DATA=>SDRAM_DATA,
                        SRAM_ADDR=>SDRAM_ADDR,
                        SRAM_WEN=>SDRAM_WEN,
                        SRAM_OEN=>SDRAM_OEN,
 
                        I_ASYNC_0=>INPUT_ASYNC_0,
                        I_ASYNC_1=>INPUT_ASYNC_1,
                        I_ASYNC_ACK_OUT=>INPUT_ASYNC_ACKOUT,
 
                        vector_enable=>run_enable,
                        ACK_COUNT_OUT=>count_in
                        );
        p1:process(cmd,SRAM_ADDR_CONFIG,SRAM_WEN_CONFIG,SRAM_OEN_CONFIG,SRAM_ADDR_TEST,SRAM_WEN_TEST,SRAM_OEN_TEST)
        begin
--              if(rst='0') then
--                      --state<=IDLE;
--                      msg_out_int<="111";
--                      init_out<='0';
--                      config_mode_out<='0';
--                      config_enable<='0';
--                      I_OL7_JP2_53<='0';              
--              elsif rising_edge(clk) then
                --      state<=next_state;
                        case cmd is
                                when "00000"=>--IDLE
                                        msg_out_int<="111";
                                        init_out<='0';
                                        config_mode_out<='0';
                                        config_enable<='0';
                                        run_enable<='0';
                                        SRAM_ADDR<=SRAM_ADDR_CONFIG;
                                        SRAM_WEN<=SRAM_WEN_CONFIG;
                                        SRAM_OEN<=SRAM_OEN_CONFIG;
                                        safe_rst<='0';
 
                                when "00001"=>--CONNECTED
                                        msg_out_int<="000";
                                        init_out<='0';
                                        config_mode_out<='0';
                                        config_enable<='0';
                                        run_enable<='0';
                                        SRAM_ADDR<=SRAM_ADDR_CONFIG;
                                        SRAM_WEN<=SRAM_WEN_CONFIG;
                                        SRAM_OEN<=SRAM_OEN_CONFIG;
                                        safe_rst<='0';
 
                                when "00011"=>--INIT
                                        msg_out_int<="001";
                                        init_out<='0';
                                        config_mode_out<='0';
                                        config_enable<='0';
                                        run_enable<='0';
                                        SRAM_ADDR<=SRAM_ADDR_CONFIG;
                                        SRAM_WEN<=SRAM_WEN_CONFIG;
                                        SRAM_OEN<=SRAM_OEN_CONFIG;
                                        safe_rst<='0';
 
                                when "00101"=>--CONFIG
                                        msg_out_int<="010";
                                        init_out<='1';
                                        config_mode_out<='0';
                                        config_enable<='1';
                                        run_enable<='0';
                                        SRAM_ADDR<=SRAM_ADDR_CONFIG;
                                        SRAM_WEN<=SRAM_WEN_CONFIG;
                                        SRAM_OEN<=SRAM_OEN_CONFIG;
                                        safe_rst<='0';
 
                                when "10001"=>--SAFE_RESET,Only I/Os there is no reset for safe!! 
                                        msg_out_int<="011";
                                        init_out<='1';
                                        config_mode_out<='1';
                                        config_enable<='1';
                                        run_enable<='0';
                                        SRAM_ADDR<=SRAM_ADDR_TEST;
                                        SRAM_WEN<=SRAM_WEN_TEST;
                                        SRAM_OEN<=SRAM_OEN_TEST;
                                        safe_rst<='0';
                                when "01001"=>--RUNNING
                                        msg_out_int<="011";
                                        init_out<='1';
                                        config_mode_out<='1';
                                        config_enable<='1';
                                        run_enable<='1';
                                        SRAM_ADDR<=SRAM_ADDR_TEST;
                                        SRAM_WEN<=SRAM_WEN_TEST;
                                        SRAM_OEN<=SRAM_OEN_TEST;
                                        safe_rst<='1';
 
                                when others=>
                                        msg_out_int<= "111";
                                        init_out<='1';
                                        config_mode_out<='0';
                                        config_enable<='0';
                                        run_enable<='0';
                                        SRAM_ADDR<=SRAM_ADDR_CONFIG;
                                        SRAM_WEN<=SRAM_WEN_CONFIG;
                                        SRAM_OEN<=SRAM_OEN_CONFIG;
                                        safe_rst<='0';
                        end case;
--              end if;
        end process;
 
--      p2:process(state,init_config,config_mode)
--      begin
--              case state is
--                      
--                      when IDLE=>
--                                      if(init_config='0') then 
--                                              next_state<=INIT;
--                                      else
--                                              next_state<=IDLE;
--                                      end if;
----                    when CONNECT=>
----                                    
----                                    if(init_config='0') then 
----                                            next_state<= INIT;
----                                    else
----                                            next_state<= CONNECT;
----                                    end if;
--
--                      when INIT=>
--                                      if(config_mode='1') then
--                                              next_state<=CONFIG;
--                                      else 
--                                              next_state<=INIT;
--                                      end if;
--
--                      when CONFIG=>
--              --                      if(init_config='0') then
--              --                              next_state<=INIT;
--                                      if(config_mode='0') then
--                                              next_state<=RUNNING;
--                                      elsif(config_mode='1') then
--                                              next_state<=CONFIG;
--                                      end if;
--
--                      when RUNNING=>
--                                      --if(init_config='0') then
--                                      --      next_state<=INIT;
--                                      if(config_mode='1') then
--                                              next_state<=CONFIG;
--                                      elsif(config_mode='0') then
--                                              next_state<=RUNNING;
--                                      end if;
--
--                      when others=>
--                                      next_state<=state;
--              end case;
--      end process;
 
--      p3:process(state)
--      begin
--              case state is
--                      when IDLE=>
--                              msg_out_int<="111";
--                              init_out<='0';
--                              config_mode_out<='0';
--                              config_enable<='0';
--                              I_OL7_JP2_53<='0';              
--                      
--                      when CONNECT=>
--                              msg_out_int<="000";
--                              init_out<='0';
--                              config_mode_out<='0';
--                              config_enable<='0';
--                              I_OL7_JP2_53<='0';              
--
--                      when INIT=>
--                              msg_out_int<="001";
--                              init_out<='0';
--                              config_mode_out<='0';
--                              config_enable<='0';
--                              I_OL7_JP2_53<='0';              
--
--                      when CONFIG=>
--                              msg_out_int<="010";
--                              init_out<='1';
--                              config_mode_out<='0';
--                              config_enable<='1';
--                              I_OL7_JP2_53<='0';              
--
--                      when RUNNING=>
--                              msg_out_int<="011";
--                              init_out<='1';
--                              config_mode_out<='1';
--                              config_enable<='0';
--                              I_OL7_JP2_53<='1';              
--                      
--                      when others=>
--                              msg_out_int<= "111";
--                              init_out<='1';
--                              config_mode_out<='0';
--                              config_enable<='0';
--                              I_OL7_JP2_53<='0';              
--              end case;
--      end process;
--      --Main State Machine------------------------------------
--p_trigger:process(clk,rst)
--      begin
--      if(rst='0') then
--              trig_count<=0;
--              trigger<='0';
--      elsif rising_edge(clk) then
--              trig_count<=trig_count+1;
--              if(trig_count=1024) then
--                      trigger<='1';
--              elsif(trig_count=2048) then
--                      trig_count<=0;
--                      trigger<='0';
--              end if;
--      end if;
--      end process;
--trigger<=clk;
end architecture machine_a_etat;

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[/] [connect-6/] [trunk/] [XILINX/] [BUILD_SCC_SRCH/] [SP6/] [safe_test.vhd] - Blame information for rev 17

Line No.	Rev	Author	Line
1	17	sumanta.ch	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`--use ieee.numeric_bit.all;`
4			`use ieee.std_logic_arith.all;`
5
6
7
8			`entity safe_test is`
9			`generic(INPUT_LENGTH:integer:=6;OUTPUT_LENGTH:integer:=6);`
10			`port(`
11			`clk:in std_ulogic;`
12			`rst:in std_ulogic;`
13			`--Config Signals`
14			`init_out:out std_ulogic;`
15			`config_mode_out:out std_ulogic;`
16			`config_out0:out std_ulogic;`
17			`config_out1:out std_ulogic;`
18			`config_ack_in:in std_ulogic;`
19			`--DE2 Control SIgnals`
20			`msg_out:out std_ulogic_vector(2 downto 0);`
21			`Ack_count_out:out std_logic_vector(31 downto 0);`
22			`cmd:in std_ulogic_vector(4 downto 0);`
23			`--SRAM`
24			`SRAM_DATA_OUT: OUT std_logic_vector(15 downto 0);`
25			`SRAM_DATA: in std_logic_vector(15 downto 0);`
26			`SRAM_ADDR: out std_logic_vector(23 downto 0);`
27			`SRAM_WEN: out std_logic;`
28			`SRAM_OEN: out std_logic;`
29			`--SDRAM`
30			`SDRAM_DATA: out std_logic_vector(15 downto 0);`
31			`SDRAM_ADDR: out std_logic_vector(23 downto 0);`
32			`SDRAM_WEN: out std_logic;`
33			`SDRAM_OEN: out std_logic;`
34			`--Result Vectors`
35			`INPUT_ASYNC_0: in std_ulogic_vector(INPUT_LENGTH-1 downto 0);`
36			`INPUT_ASYNC_1: in std_ulogic_vector(INPUT_LENGTH-1 downto 0);`
37			`INPUT_ASYNC_ACKOUT: out std_ulogic_vector(INPUT_LENGTH-1 downto 0);`
38			`--Test Vectors`
39			`OUTPUT_ASYNC_0: out std_ulogic_vector(OUTPUT_LENGTH-1 downto 0);`
40			`OUTPUT_ASYNC_1: out std_ulogic_vector(OUTPUT_LENGTH-1 downto 0);`
41			`OUTPUT_ASYNC_ACKIN: in std_ulogic_vector(OUTPUT_LENGTH-1 downto 0);`
42
43			`--Trigger for oscilloscope`
44			`trigger: out std_ulogic`
45
46			`);`
47			`end entity safe_test;`
48
49
50			`architecture machine_a_etat of safe_test is`
51			`component S_TO_AS_CONFIG is`
52			`generic (BEGIN_ADDR:integer:=0;END_ADDR:integer:=0;LENGTH:integer:=16);`
53			`port(`
54			`clk:in std_ulogic;`
55			`rst:in std_ulogic;`
56
57			`SRAM_DATA_OUT: out std_logic_vector(15 downto 0);`
58			`SRAM_DATA: in std_logic_vector(15 downto 0);`
59			`SRAM_ADDR: out std_logic_vector(23 downto 0);`
60			`SRAM_WEN: out std_logic;`
61			`SRAM_OEN: out std_logic;`
62
63			`AS_OUT0: out std_ulogic;`
64			`AS_OUT1: out std_ulogic;`
65			`ACK_IN: in std_ulogic;`
66
67			`config_enable: in std_ulogic; -- Command from the state_machine up there`
68			`ACK_COUNT_OUT: out std_logic_vector(31 downto 0)`
69			`);`
70			`end component S_TO_AS_CONFIG;`
71
72			`component AS_TO_S_VECTOR is`
73			`generic (BEGIN_ADDR:integer:=0;END_ADDR:integer:=0;LENGTH:integer:=16);`
74			`port(`
75			`clk:in std_ulogic;`
76			`rst:in std_ulogic;`
77
78			`SRAM_DATA: out std_logic_vector(15 downto 0);`
79			`SRAM_ADDR: out std_logic_vector(23 downto 0);`
80			`SRAM_WEN: out std_logic;`
81			`SRAM_OEN: out std_logic;`
82
83			`I_ASYNC_0: in std_ulogic_vector(LENGTH-1 downto 0);`
84			`I_ASYNC_1: in std_ulogic_vector(LENGTH-1 downto 0);`
85			`I_ASYNC_ACK_OUT: out std_ulogic_vector(LENGTH-1 downto 0);`
86
87			`vector_enable: in std_ulogic; -- Command from the state_machine up there`
88			`ACK_COUNT_OUT: out std_logic_vector(31 downto 0)`
89			`);`
90			`end component AS_TO_S_VECTOR;`
91
92			`component S_TO_AS_VECTOR is`
93			`generic (BEGIN_ADDR:integer:=0;END_ADDR:integer:=0;LENGTH:integer:=16);`
94			`port(`
95			`clk:in std_ulogic;`
96			`rst:in std_ulogic;`
97			`trigger:out std_ulogic;`
98
99			`SRAM_DATA: in std_logic_vector(15 downto 0);`
100			`SRAM_ADDR: out std_logic_vector(23 downto 0);`
101			`SRAM_WEN: out std_logic;`
102			`SRAM_OEN: out std_logic;`
103
104			`O_ASYNC_0: out std_ulogic_vector(LENGTH-1 downto 0);`
105			`O_ASYNC_1: out std_ulogic_vector(LENGTH-1 downto 0);`
106			`O_ASYNC_ACK_IN: in std_ulogic_vector(LENGTH-1 downto 0);`
107
108			`vector_enable: in std_ulogic; -- Command from the state_machine up there`
109			`ACK_COUNT_OUT: out std_logic_vector(31 downto 0)`
110			`);`
111			`end component S_TO_AS_VECTOR;`
112
113			`--type STATE_TYPE is(IDLE,INIT,CONFIG,RUNNING);`
114			`--signal state,next_state:STATE_TYPE;`
115			`signal msg_out_int:std_ulogic_vector(2 downto 0);`
116			`signal count:integer range 0 to integer'high;`
117			`signal count_in,count_out:std_logic_vector(31 downto 0);`
118			`signal config_enable,run_enable,safe_rst:std_ulogic;`
119			`signal SRAM_DATA_TEST,SRAM_DATA_CONFIG:std_logic_vector(15 downto 0);`
120			`signal SRAM_ADDR_TEST,SRAM_ADDR_CONFIG:std_logic_vector(23 downto 0);`
121			`signal SRAM_WEN_CONFIG,SRAM_WEN_TEST,SRAM_OEN_CONFIG,SRAM_OEN_TEST:std_logic;`
122			`signal trig_count:integer range 0 to integer'high;`
123			`begin`
124			`msg_out<=msg_out_int;`
125			`TRANSLATE: S_TO_AS_CONFIG`
126			`generic map(BEGIN_ADDR=>0,END_ADDR=>293,LENGTH=>1)`
127			`port map(`
128			`clk=>clk,`
129			`rst=>rst,`
130
131			`SRAM_DATA_OUT=>SRAM_DATA_OUT,`
132			`SRAM_DATA=>SRAM_DATA,`
133			`SRAM_ADDR=>SRAM_ADDR_CONFIG,`
134			`SRAM_WEN=>SRAM_WEN_CONFIG,`
135			`SRAM_OEN=>SRAM_OEN_CONFIG,`
136
137			`AS_OUT0=>config_out0,`
138			`AS_OUT1=>config_out1,`
139			`ACK_IN=>config_ack_in,`
140
141			`config_enable=>config_enable,`
142			`ACK_COUNT_OUT=>Ack_count_out);`
143
144
145			`TRANSLATE_S_TO_AS:S_TO_AS_VECTOR`
146			`generic map(BEGIN_ADDR=>4096,END_ADDR=>4159,LENGTH=>OUTPUT_LENGTH)`
147			`port map(`
148			`clk=>clk,`
149			`rst=>safe_rst,`
150			`trigger=>trigger,`
151
152			`SRAM_DATA=>SRAM_DATA,`
153			`SRAM_ADDR=>SRAM_ADDR_TEST,`
154			`SRAM_WEN=>SRAM_WEN_TEST,`
155			`SRAM_OEN=>SRAM_OEN_TEST,`
156
157			`O_ASYNC_0=>OUTPUT_ASYNC_0,`
158			`O_ASYNC_1=>OUTPUT_ASYNC_1,`
159			`O_ASYNC_ACK_IN=>OUTPUT_ASYNC_ACKIN,`
160
161			`vector_enable=>run_enable,`
162			`ACK_COUNT_OUT=>count_out`
163			`);`
164			`TRANSLATE_AS_TO_S:AS_TO_S_VECTOR`
165			`generic map(BEGIN_ADDR=>0,END_ADDR=>63,LENGTH=>INPUT_LENGTH)`
166			`port map(`
167			`clk=>clk,`
168			`rst=>safe_rst,`
169
170			`SRAM_DATA=>SDRAM_DATA,`
171			`SRAM_ADDR=>SDRAM_ADDR,`
172			`SRAM_WEN=>SDRAM_WEN,`
173			`SRAM_OEN=>SDRAM_OEN,`
174
175			`I_ASYNC_0=>INPUT_ASYNC_0,`
176			`I_ASYNC_1=>INPUT_ASYNC_1,`
177			`I_ASYNC_ACK_OUT=>INPUT_ASYNC_ACKOUT,`
178
179			`vector_enable=>run_enable,`
180			`ACK_COUNT_OUT=>count_in`
181			`);`
182			`p1:process(cmd,SRAM_ADDR_CONFIG,SRAM_WEN_CONFIG,SRAM_OEN_CONFIG,SRAM_ADDR_TEST,SRAM_WEN_TEST,SRAM_OEN_TEST)`
183			`begin`
184			`-- if(rst='0') then`
185			`-- --state<=IDLE;`
186			`-- msg_out_int<="111";`
187			`-- init_out<='0';`
188			`-- config_mode_out<='0';`
189			`-- config_enable<='0';`
190			`-- I_OL7_JP2_53<='0';`
191			`-- elsif rising_edge(clk) then`
192			`-- state<=next_state;`
193			`case cmd is`
194			`when "00000"=>--IDLE`
195			`msg_out_int<="111";`
196			`init_out<='0';`
197			`config_mode_out<='0';`
198			`config_enable<='0';`
199			`run_enable<='0';`
200			`SRAM_ADDR<=SRAM_ADDR_CONFIG;`
201			`SRAM_WEN<=SRAM_WEN_CONFIG;`
202			`SRAM_OEN<=SRAM_OEN_CONFIG;`
203			`safe_rst<='0';`
204
205			`when "00001"=>--CONNECTED`
206			`msg_out_int<="000";`
207			`init_out<='0';`
208			`config_mode_out<='0';`
209			`config_enable<='0';`
210			`run_enable<='0';`
211			`SRAM_ADDR<=SRAM_ADDR_CONFIG;`
212			`SRAM_WEN<=SRAM_WEN_CONFIG;`
213			`SRAM_OEN<=SRAM_OEN_CONFIG;`
214			`safe_rst<='0';`
215
216			`when "00011"=>--INIT`
217			`msg_out_int<="001";`
218			`init_out<='0';`
219			`config_mode_out<='0';`
220			`config_enable<='0';`
221			`run_enable<='0';`
222			`SRAM_ADDR<=SRAM_ADDR_CONFIG;`
223			`SRAM_WEN<=SRAM_WEN_CONFIG;`
224			`SRAM_OEN<=SRAM_OEN_CONFIG;`
225			`safe_rst<='0';`
226
227			`when "00101"=>--CONFIG`
228			`msg_out_int<="010";`
229			`init_out<='1';`
230			`config_mode_out<='0';`
231			`config_enable<='1';`
232			`run_enable<='0';`
233			`SRAM_ADDR<=SRAM_ADDR_CONFIG;`
234			`SRAM_WEN<=SRAM_WEN_CONFIG;`
235			`SRAM_OEN<=SRAM_OEN_CONFIG;`
236			`safe_rst<='0';`
237
238			`when "10001"=>--SAFE_RESET,Only I/Os there is no reset for safe!!`
239			`msg_out_int<="011";`
240			`init_out<='1';`
241			`config_mode_out<='1';`
242			`config_enable<='1';`
243			`run_enable<='0';`
244			`SRAM_ADDR<=SRAM_ADDR_TEST;`
245			`SRAM_WEN<=SRAM_WEN_TEST;`
246			`SRAM_OEN<=SRAM_OEN_TEST;`
247			`safe_rst<='0';`
248			`when "01001"=>--RUNNING`
249			`msg_out_int<="011";`
250			`init_out<='1';`
251			`config_mode_out<='1';`
252			`config_enable<='1';`
253			`run_enable<='1';`
254			`SRAM_ADDR<=SRAM_ADDR_TEST;`
255			`SRAM_WEN<=SRAM_WEN_TEST;`
256			`SRAM_OEN<=SRAM_OEN_TEST;`
257			`safe_rst<='1';`
258
259			`when others=>`
260			`msg_out_int<= "111";`
261			`init_out<='1';`
262			`config_mode_out<='0';`
263			`config_enable<='0';`
264			`run_enable<='0';`
265			`SRAM_ADDR<=SRAM_ADDR_CONFIG;`
266			`SRAM_WEN<=SRAM_WEN_CONFIG;`
267			`SRAM_OEN<=SRAM_OEN_CONFIG;`
268			`safe_rst<='0';`
269			`end case;`
270			`-- end if;`
271			`end process;`
272
273			`-- p2:process(state,init_config,config_mode)`
274			`-- begin`
275			`-- case state is`
276			`--`
277			`-- when IDLE=>`
278			`-- if(init_config='0') then`
279			`-- next_state<=INIT;`
280			`-- else`
281			`-- next_state<=IDLE;`
282			`-- end if;`
283			`---- when CONNECT=>`
284			`----`
285			`---- if(init_config='0') then`
286			`---- next_state<= INIT;`
287			`---- else`
288			`---- next_state<= CONNECT;`
289			`---- end if;`
290			`--`
291			`-- when INIT=>`
292			`-- if(config_mode='1') then`
293			`-- next_state<=CONFIG;`
294			`-- else`
295			`-- next_state<=INIT;`
296			`-- end if;`
297			`--`
298			`-- when CONFIG=>`
299			`-- -- if(init_config='0') then`
300			`-- -- next_state<=INIT;`
301			`-- if(config_mode='0') then`
302			`-- next_state<=RUNNING;`
303			`-- elsif(config_mode='1') then`
304			`-- next_state<=CONFIG;`
305			`-- end if;`
306			`--`
307			`-- when RUNNING=>`
308			`-- --if(init_config='0') then`
309			`-- -- next_state<=INIT;`
310			`-- if(config_mode='1') then`
311			`-- next_state<=CONFIG;`
312			`-- elsif(config_mode='0') then`
313			`-- next_state<=RUNNING;`
314			`-- end if;`
315			`--`
316			`-- when others=>`
317			`-- next_state<=state;`
318			`-- end case;`
319			`-- end process;`
320
321			`-- p3:process(state)`
322			`-- begin`
323			`-- case state is`
324			`-- when IDLE=>`
325			`-- msg_out_int<="111";`
326			`-- init_out<='0';`
327			`-- config_mode_out<='0';`
328			`-- config_enable<='0';`
329			`-- I_OL7_JP2_53<='0';`
330			`--`
331			`-- when CONNECT=>`
332			`-- msg_out_int<="000";`
333			`-- init_out<='0';`
334			`-- config_mode_out<='0';`
335			`-- config_enable<='0';`
336			`-- I_OL7_JP2_53<='0';`
337			`--`
338			`-- when INIT=>`
339			`-- msg_out_int<="001";`
340			`-- init_out<='0';`
341			`-- config_mode_out<='0';`
342			`-- config_enable<='0';`
343			`-- I_OL7_JP2_53<='0';`
344			`--`
345			`-- when CONFIG=>`
346			`-- msg_out_int<="010";`
347			`-- init_out<='1';`
348			`-- config_mode_out<='0';`
349			`-- config_enable<='1';`
350			`-- I_OL7_JP2_53<='0';`
351			`--`
352			`-- when RUNNING=>`
353			`-- msg_out_int<="011";`
354			`-- init_out<='1';`
355			`-- config_mode_out<='1';`
356			`-- config_enable<='0';`
357			`-- I_OL7_JP2_53<='1';`
358			`--`
359			`-- when others=>`
360			`-- msg_out_int<= "111";`
361			`-- init_out<='1';`
362			`-- config_mode_out<='0';`
363			`-- config_enable<='0';`
364			`-- I_OL7_JP2_53<='0';`
365			`-- end case;`
366			`-- end process;`
367			`-- --Main State Machine------------------------------------`
368			`--p_trigger:process(clk,rst)`
369			`-- begin`
370			`-- if(rst='0') then`
371			`-- trig_count<=0;`
372			`-- trigger<='0';`
373			`-- elsif rising_edge(clk) then`
374			`-- trig_count<=trig_count+1;`
375			`-- if(trig_count=1024) then`
376			`-- trigger<='1';`
377			`-- elsif(trig_count=2048) then`
378			`-- trig_count<=0;`
379			`-- trigger<='0';`
380			`-- end if;`
381			`-- end if;`
382			`-- end process;`
383			`--trigger<=clk;`
384			`end architecture machine_a_etat;`