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[/] [cop/] [trunk/] [rtl/] [verilog/] [cop_count.v] - Blame information for rev 3

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////////////////////////////////////////////////////////////////////////////////
//
//  Computer Operating Properly - Watchdog Counter
//
//  Author: Bob Hayes
//          rehayes@opencores.org
//
//  Downloaded from: http://www.opencores.org/projects/cop.....
//
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009, Robert Hayes
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//     * Redistributions of source code must retain the above copyright
//       notice, this list of conditions and the following disclaimer.
//     * Redistributions in binary form must reproduce the above copyright
//       notice, this list of conditions and the following disclaimer in the
//       documentation and/or other materials provided with the distribution.
//     * Neither the name of the <organization> nor the
//       names of its contributors may be used to endorse or promote products
//       derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
////////////////////////////////////////////////////////////////////////////////
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
 
module cop_count #(parameter COUNT_SIZE = 16)
  (
  output reg [COUNT_SIZE-1:0] cop_counter,   // Modulo Counter value
  output reg [COUNT_SIZE-1:0] cop_capture,   // Counter value syncronized to bus_clk domain
  output reg                  cop_rst_o,     // COP Reset
  output reg                  cop_irq_o,     // COP Interrupt Request
  output reg                  cop_event,     // COP status bit
  input                       async_rst_b,   // Asyncronous reset signal
  input                       sync_reset,    // Syncronous reset signal
  input                       por_reset_i,   // System Power On Reset, active low
  input                       startup_osc_i, // System Startup Oscillator
  input                       bus_clk,       // Control register bus clock
  input                       reload_count,  // Correct control words written
  input                       clear_event,   // Reset the COP event register
  input                       debug_mode_i,  // System DEBUG Mode
  input                       debug_ena,     // Enable COP in system debug mode
  input                       wait_ena,      // Enable COP in system wait mode
  input                       wait_mode_i,   // System WAIT Mode
  input                       stop_ena,      // Enable COP in system stop mode
  input                       stop_mode_i,   // System STOP Mode
  input                       cop_ena,       // Enable COP Timout Counter
  input                [ 1:0] cop_irq_en,    // COP IRQ Enable/Value
  input      [COUNT_SIZE-1:0] timeout_value, // COP Counter initial value
  input                       scantestmode   // Chip in in scan test mode
  );
 
 
  wire stop_counter;    // Enable COP because of external inputs
  wire cop_clk;         // Clock for COP Timeout counter
  wire event_reset;     // Clear COP event status bit
  wire cop_clk_posedge; // Syncronizing signal to move data to bus_clk domain
 
  reg  cop_irq_dec;     // COP Interrupt Request Decode
  reg  cop_irq;         // COP Interrupt Request
  reg  reload_1;        // Resync register for commands crossing from bus_clk domain to cop_clk domain
  reg  reload_2;        //
  reg  cop_clk_resync1; //
  reg  cop_clk_resync2; //
 
 
  assign event_reset = reload_count || clear_event;
 
  assign stop_counter = (debug_mode_i && debug_ena) ||
                        (wait_mode_i && wait_ena) || (stop_mode_i && stop_ena);
 
  assign cop_clk = scantestmode ? bus_clk : startup_osc_i;
 
 
  assign cop_clk_posedge = cop_clk_resync1 && !cop_clk_resync2;
 
  //  Watchdog Timout Counter
  always @(posedge cop_clk or negedge async_rst_b)
    if ( !async_rst_b )
      cop_counter  <= {COUNT_SIZE{1'b1}};
    else if ( reload_2 )
      cop_counter  <= timeout_value;
    else if ( !stop_counter )
      cop_counter  <= cop_counter - 1;
 
  //  COP Output Register
  always @(posedge cop_clk or negedge por_reset_i)
    if ( !por_reset_i )
      cop_rst_o <= 1'b0;
    else if ( reload_2 )
      cop_rst_o <= 1'b0;
    else
      cop_rst_o <= (cop_counter == 0);
 
  // Clock domain crossing registers. Take data from cop_clk domain and move it
  //  to the bus_clk domain.
  always @(posedge bus_clk or negedge async_rst_b)
    if ( !async_rst_b )
      begin
        cop_clk_resync1 <= 1'b0;
        cop_clk_resync2 <= 1'b0;
        cop_capture     <= {COUNT_SIZE{1'b1}};
      end
    else if (sync_reset)
      begin
        cop_clk_resync1 <= 1'b0;
        cop_clk_resync2 <= 1'b0;
        cop_capture     <= {COUNT_SIZE{1'b1}};
      end
    else
      begin
        cop_clk_resync1 <= cop_clk;
        cop_clk_resync2 <= cop_clk_resync1;
        cop_capture     <= cop_clk_posedge ? cop_counter : cop_capture;
      end
 
  // Stage one of pulse strecher and resync
  always @(posedge bus_clk or negedge async_rst_b)
    if ( !async_rst_b )
      reload_1 <= 1'b0;
    else if (sync_reset)
      reload_1 <= 1'b0;
    else
      reload_1 <= (sync_reset || reload_count || !cop_ena) || (reload_1 && !reload_2);
 
  // Stage two pulse strecher and resync
  always @(posedge cop_clk or negedge por_reset_i)
    if ( !por_reset_i )
      reload_2 <= 1'b1;
    else
      reload_2 <= reload_1;
 
  // Decode COP Interrupt Request
  always @*
    case (cop_irq_en) // synopsys parallel_case
       2'b01 : cop_irq_dec = (cop_counter <= 16);
       2'b10 : cop_irq_dec = (cop_counter <= 32);
       2'b11 : cop_irq_dec = (cop_counter <= 64);
       default: cop_irq_dec = 1'b0;
    endcase
 
  //  Watchdog Interrupt and resync
  always @(posedge bus_clk or negedge async_rst_b)
    if ( !async_rst_b )
      begin
        cop_irq   <= 0;
        cop_irq_o <= 0;
      end
    else if (sync_reset)
      begin
        cop_irq   <= 0;
        cop_irq_o <= 0;
      end
    else
      begin
        cop_irq   <= cop_irq_dec;
        cop_irq_o <= cop_irq;
      end
 
  //  Watchdog Status Bit
  always @(posedge bus_clk or negedge por_reset_i)
    if ( !por_reset_i )
      cop_event <= 0;
    else
      cop_event <= cop_rst_o || (cop_event && !event_reset);
 
endmodule  // cop_count
 

Line No.	Rev	Author	Line
1	2	rehayes	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Computer Operating Properly - Watchdog Counter`
4			`//`
5			`// Author: Bob Hayes`
6			`// rehayes@opencores.org`
7			`//`
8			`// Downloaded from: http://www.opencores.org/projects/cop.....`
9			`//`
10			`////////////////////////////////////////////////////////////////////////////////`
11			`// Copyright (c) 2009, Robert Hayes`
12			`//`
13			`// All rights reserved.`
14			`//`
15			`// Redistribution and use in source and binary forms, with or without`
16			`// modification, are permitted provided that the following conditions are met:`
17			`// * Redistributions of source code must retain the above copyright`
18			`// notice, this list of conditions and the following disclaimer.`
19			`// * Redistributions in binary form must reproduce the above copyright`
20			`// notice, this list of conditions and the following disclaimer in the`
21			`// documentation and/or other materials provided with the distribution.`
22			`// * Neither the name of the <organization> nor the`
23			`// names of its contributors may be used to endorse or promote products`
24			`// derived from this software without specific prior written permission.`
25			`//`
26			`// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY`
27			`// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED`
28			`// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE`
29			`// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY`
30			`// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES`
31			`// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;`
32			`// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND`
33			`// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
34			`// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS`
35			`// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
36			`////////////////////////////////////////////////////////////////////////////////`
37			`// 45678901234567890123456789012345678901234567890123456789012345678901234567890`
38
39			`module cop_count #(parameter COUNT_SIZE = 16)`
40			`(`
41			`output reg [COUNT_SIZE-1:0] cop_counter, // Modulo Counter value`
42			`output reg [COUNT_SIZE-1:0] cop_capture, // Counter value syncronized to bus_clk domain`
43			`output reg cop_rst_o, // COP Reset`
44			`output reg cop_irq_o, // COP Interrupt Request`
45			`output reg cop_event, // COP status bit`
46			`input async_rst_b, // Asyncronous reset signal`
47			`input sync_reset, // Syncronous reset signal`
48			`input por_reset_i, // System Power On Reset, active low`
49			`input startup_osc_i, // System Startup Oscillator`
50			`input bus_clk, // Control register bus clock`
51			`input reload_count, // Correct control words written`
52			`input clear_event, // Reset the COP event register`
53			`input debug_mode_i, // System DEBUG Mode`
54			`input debug_ena, // Enable COP in system debug mode`
55			`input wait_ena, // Enable COP in system wait mode`
56			`input wait_mode_i, // System WAIT Mode`
57			`input stop_ena, // Enable COP in system stop mode`
58			`input stop_mode_i, // System STOP Mode`
59			`input cop_ena, // Enable COP Timout Counter`
60			`input [ 1:0] cop_irq_en, // COP IRQ Enable/Value`
61			`input [COUNT_SIZE-1:0] timeout_value, // COP Counter initial value`
62			`input scantestmode // Chip in in scan test mode`
63			`);`
64
65
66			`wire stop_counter; // Enable COP because of external inputs`
67			`wire cop_clk; // Clock for COP Timeout counter`
68			`wire event_reset; // Clear COP event status bit`
69			`wire cop_clk_posedge; // Syncronizing signal to move data to bus_clk domain`
70
71			`reg cop_irq_dec; // COP Interrupt Request Decode`
72			`reg cop_irq; // COP Interrupt Request`
73			`reg reload_1; // Resync register for commands crossing from bus_clk domain to cop_clk domain`
74			`reg reload_2; //`
75			`reg cop_clk_resync1; //`
76			`reg cop_clk_resync2; //`
77
78
79			`assign event_reset = reload_count \|\| clear_event;`
80
81			`assign stop_counter = (debug_mode_i && debug_ena) \|\|`
82			`(wait_mode_i && wait_ena) \|\| (stop_mode_i && stop_ena);`
83
84			`assign cop_clk = scantestmode ? bus_clk : startup_osc_i;`
85
86
87			`assign cop_clk_posedge = cop_clk_resync1 && !cop_clk_resync2;`
88
89			`// Watchdog Timout Counter`
90			`always @(posedge cop_clk or negedge async_rst_b)`
91			`if ( !async_rst_b )`
92			`cop_counter <= {COUNT_SIZE{1'b1}};`
93			`else if ( reload_2 )`
94			`cop_counter <= timeout_value;`
95			`else if ( !stop_counter )`
96			`cop_counter <= cop_counter - 1;`
97
98			`// COP Output Register`
99			`always @(posedge cop_clk or negedge por_reset_i)`
100			`if ( !por_reset_i )`
101			`cop_rst_o <= 1'b0;`
102			`else if ( reload_2 )`
103			`cop_rst_o <= 1'b0;`
104			`else`
105			`cop_rst_o <= (cop_counter == 0);`
106
107			`// Clock domain crossing registers. Take data from cop_clk domain and move it`
108			`// to the bus_clk domain.`
109			`always @(posedge bus_clk or negedge async_rst_b)`
110			`if ( !async_rst_b )`
111			`begin`
112			`cop_clk_resync1 <= 1'b0;`
113			`cop_clk_resync2 <= 1'b0;`
114			`cop_capture <= {COUNT_SIZE{1'b1}};`
115			`end`
116			`else if (sync_reset)`
117			`begin`
118			`cop_clk_resync1 <= 1'b0;`
119			`cop_clk_resync2 <= 1'b0;`
120			`cop_capture <= {COUNT_SIZE{1'b1}};`
121			`end`
122			`else`
123			`begin`
124			`cop_clk_resync1 <= cop_clk;`
125			`cop_clk_resync2 <= cop_clk_resync1;`
126			`cop_capture <= cop_clk_posedge ? cop_counter : cop_capture;`
127			`end`
128
129			`// Stage one of pulse strecher and resync`
130			`always @(posedge bus_clk or negedge async_rst_b)`
131			`if ( !async_rst_b )`
132			`reload_1 <= 1'b0;`
133			`else if (sync_reset)`
134			`reload_1 <= 1'b0;`
135			`else`
136			`reload_1 <= (sync_reset \|\| reload_count \|\| !cop_ena) \|\| (reload_1 && !reload_2);`
137
138			`// Stage two pulse strecher and resync`
139			`always @(posedge cop_clk or negedge por_reset_i)`
140			`if ( !por_reset_i )`
141			`reload_2 <= 1'b1;`
142			`else`
143			`reload_2 <= reload_1;`
144
145			`// Decode COP Interrupt Request`
146			`always @*`
147			`case (cop_irq_en) // synopsys parallel_case`
148			`2'b01 : cop_irq_dec = (cop_counter <= 16);`
149			`2'b10 : cop_irq_dec = (cop_counter <= 32);`
150			`2'b11 : cop_irq_dec = (cop_counter <= 64);`
151			`default: cop_irq_dec = 1'b0;`
152			`endcase`
153
154			`// Watchdog Interrupt and resync`
155			`always @(posedge bus_clk or negedge async_rst_b)`
156			`if ( !async_rst_b )`
157			`begin`
158			`cop_irq <= 0;`
159			`cop_irq_o <= 0;`
160			`end`
161			`else if (sync_reset)`
162			`begin`
163			`cop_irq <= 0;`
164			`cop_irq_o <= 0;`
165			`end`
166			`else`
167			`begin`
168			`cop_irq <= cop_irq_dec;`
169			`cop_irq_o <= cop_irq;`
170			`end`
171
172			`// Watchdog Status Bit`
173			`always @(posedge bus_clk or negedge por_reset_i)`
174			`if ( !por_reset_i )`
175			`cop_event <= 0;`
176			`else`
177			`cop_event <= cop_rst_o \|\| (cop_event && !event_reset);`
178
179			`endmodule // cop_count`
180

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[/] [cop/] [trunk/] [rtl/] [verilog/] [cop_count.v] - Blame information for rev 3