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-- Company:
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--
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-- File: cp_BancRegister.vhd
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--
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-- Description:
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-- projet copyblaze
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-- Banc Registers
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--
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-- File history:
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-- v1.0: 10/10/11: Creation
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--
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-- Targeted device: ProAsic A3P250 VQFP100
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-- Author: AbdAllah Meziti
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.Usefull_Pkg.all; -- Usefull Package
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-- Entity: cp_BancRegister
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--
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-- Description:
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--
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-- REMARQUE:
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--
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--
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-- History:
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-- 10/10/11 AM: Creation
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-- ---------------------
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-- xx/xx/xx AM:
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--
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entity cp_BancRegister is
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generic
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(
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GEN_WIDTH_DATA : positive := 8;
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GEN_DEPTH_BANC : positive := 16
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);
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port (
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--------------------------------------------------------------------------------
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-- Signaux Systeme
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Clk_i : in std_ulogic; -- signal d'horloge générale
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Rst_i_n : in std_ulogic; -- signal de reset générale
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--------------------------------------------------------------------------------
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-- Signaux Fonctionels
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--------------------------------------------------------------------------------
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SxPtr_i : in std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0);
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SyPtr_i : in std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0);
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Write_i : in std_ulogic;
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SxData_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
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SxData_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
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SyData_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0)
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);
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end cp_BancRegister;
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--------------------------------------------------------------------------------
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-- Architecture: RTL
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-- of entity : cp_BancRegister
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architecture rtl of cp_BancRegister is
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--------------------------------------------------------------------------------
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-- Définition des fonctions
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--------------------------------------------------------------------------------
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-- Définition des constantes
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Machine d'état principale de pilotage du driver de l'igbt
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Définition des signaux interne
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type RAM_TYPE is array (0 to GEN_DEPTH_BANC-1) of std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
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signal iBancRegMem : RAM_TYPE;
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-- Déclaration des composants
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begin
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--------------------------------------------------------------------------------
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-- Process : BancReg_Proc
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-- Description: BancRegister Memory
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BancReg_Proc : process(Rst_i_n, Clk_i)
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begin
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if ( Rst_i_n = '0' ) then
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for i in 0 to GEN_DEPTH_BANC-1 loop
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iBancRegMem(i) <= (others=>'0');
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end loop;
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elsif ( rising_edge(Clk_i) ) then
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if ( Write_i = '1' ) then
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iBancRegMem( to_integer(unsigned(SxPtr_i)) ) <= SxData_i;
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end if;
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end if;
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end process BancReg_Proc;
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SxData_o <= iBancRegMem( to_integer(unsigned(SxPtr_i)) );
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SyData_o <= iBancRegMem( to_integer(unsigned(SyPtr_i)) );
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end rtl;
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