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ameziti |
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-- Company:
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--
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-- File: cp_DecodeControl.vhd
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--
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-- Description:
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-- projet copyblaze
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-- instruction decoding & Operational control
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--
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-- File history:
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-- v1.0: 21/10/11: Creation
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-- v2.0: 26/10/11: Add Wishbone instructions
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--
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-- Targeted device: ProAsic A3P250 VQFP100
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-- Author: AbdAllah Meziti
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.Usefull_Pkg.all; -- Usefull Package
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--------------------------------------------------------------------------------
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-- Entity: cp_DecodeControl
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--
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-- Description:
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--
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-- REMARQUE:
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--
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--
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-- History:
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-- 21/10/11 AM: Creation
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-- ---------------------
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-- xx/xx/xx AM:
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--
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--------------------------------------------------------------------------------
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entity cp_DecodeControl is
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generic
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(
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GEN_WIDTH_INST : positive := 18;
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GEN_WIDTH_PC : positive := 10;
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GEN_DEPTH_BANC : positive := 16; -- Taille (en octet) du Banc Register
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GEN_DEPTH_SCRATCH : positive := 64 -- Taille (en octet) du Scratch Pad
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);
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port (
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--------------------------------------------------------------------------------
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-- Signaux Fonctionels
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--------------------------------------------------------------------------------
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--Phase1_i : in std_ulogic;
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Phase2_i : in std_ulogic;
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IEvent_i : in std_ulogic;
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Instruction_i : in std_ulogic_vector(GEN_WIDTH_INST-1 downto 0);
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Fetch_o : out std_ulogic;
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Input_o : out std_ulogic;
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Ouput_o : out std_ulogic;
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Jump_o : out std_ulogic;
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Call_o : out std_ulogic;
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Return_o : out std_ulogic;
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ReturnI_o : out std_ulogic;
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IEWrite_o : out std_ulogic;
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BancWrite_o : out std_ulogic;
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ScratchWrite_o : out std_ulogic;
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OperationSelect_o : out std_ulogic_vector(2 downto 0);
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FlagsWrite_o : out std_ulogic;
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FlagsPush_o : out std_ulogic;
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FlagsPop_o : out std_ulogic;
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aaa_o : out std_ulogic_vector(GEN_WIDTH_PC-1 downto 0);
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kk_o : out std_ulogic_vector(7 downto 0);
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ss_o : out std_ulogic_vector(log2(GEN_DEPTH_SCRATCH)-1 downto 0);
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pp_o : out std_ulogic_vector(7 downto 0);
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SxPtr_o : out std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0);
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SyPtr_o : out std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0);
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OperandSelect_o : out std_ulogic;
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ArithOper_o : out std_ulogic_vector(1 downto 0);
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LogicOper_o : out std_ulogic_vector(1 downto 0);
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ShiftBit_o : out std_ulogic_vector(2 downto 0);
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ShiftSens_o : out std_ulogic;
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ConditionCtrl_o : out std_ulogic_vector(2 downto 0);
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IEValue_o : out std_ulogic;
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wbRdSing_o : out std_ulogic;
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wbWrSing_o : out std_ulogic
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);
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end cp_DecodeControl;
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--------------------------------------------------------------------------------
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-- Architecture: RTL
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-- of entity : cp_DecodeControl
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--------------------------------------------------------------------------------
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architecture rtl of cp_DecodeControl is
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--------------------------------------------------------------------------------
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-- Définition des fonctions
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Définition des constantes
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Définition des signaux interne
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--------------------------------------------------------------------------------
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signal iInstruction : std_ulogic_vector(GEN_WIDTH_INST-1 downto 0);
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alias iInstructionCode : std_ulogic_vector(4 downto 0) is iInstruction(17 downto 13);
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-- **** --
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-- PATH --
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-- **** --
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alias iaaa : std_ulogic_vector(GEN_WIDTH_PC-1 downto 0) is iInstruction(GEN_WIDTH_PC-1 downto 0);
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alias ikk : std_ulogic_vector(7 downto 0) is iInstruction(7 downto 0);
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alias iss : std_ulogic_vector(log2(GEN_DEPTH_SCRATCH)-1 downto 0) is iInstruction(log2(GEN_DEPTH_SCRATCH)-1 downto 0);
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alias ipp : std_ulogic_vector(7 downto 0) is iInstruction(7 downto 0);
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alias iSxPtr : std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0) is iInstruction(8+log2(GEN_DEPTH_BANC)-1 downto 8);
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alias iSyPtr : std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0) is iInstruction(4+log2(GEN_DEPTH_BANC)-1 downto 4);
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-- ******* --
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-- CONTROL --
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-- ******* --
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-- Alu
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signal iOperationSelect : std_ulogic_vector(2 downto 0);
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alias iOperandSelect : std_ulogic is iInstruction(12);
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alias iArithOper : std_ulogic_vector(1 downto 0) is iInstruction(14 downto 13);
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alias iLogicOper : std_ulogic_vector(1 downto 0) is iInstruction(14 downto 13);
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alias iShiftBit : std_ulogic_vector(2 downto 0) is iInstruction(2 downto 0);
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alias iShiftSens : std_ulogic is iInstruction(3);
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-- Banc
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signal iBancWrite : std_ulogic;
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-- Scratch
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signal iScratchWrite : std_ulogic;
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-- Flags
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signal iFlagsWrite ,
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iFlagsPush ,
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iFlagsPop : std_ulogic;
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signal iIEWrite : std_ulogic;
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signal iAddSub ,
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iCompare ,
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iLoad ,
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iLogic ,
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iTest ,
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iShift ,
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iStore ,
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iFetch ,
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iInput ,
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iOuput ,
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iJump ,
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iCall ,
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iReturn ,
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iReturnI ,
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iSetInterrupt ,
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-- Wishbone instructions
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iWBWrSing ,
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iWBRdSing
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: std_ulogic;
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-- Flow
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alias iConditionCtrl : std_ulogic_vector(2 downto 0) is iInstruction(12 downto 10);
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-- Int
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alias iIEValue : std_ulogic is iInstruction(0);
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signal iIEvent : std_ulogic;
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--------------------------------------------------------------------------------
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-- Déclaration des composants
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--------------------------------------------------------------------------------
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begin
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--------------------------------------------------------------------------------
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-- DECODER
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--------------------------------------------------------------------------------
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iIEvent <= IEvent_i;
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-- Preempte the instruction in case of interrupt event
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iInstruction <= (others => '1') when (iIEvent='1') else Instruction_i;
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--------------------------------------------------------------------------------
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-- INSTRUCTION DECODER
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--------------------------------------------------------------------------------
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-- Arithmetic Group
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iAddSub <= '1' when ((iInstructionCode = '0' & x"C") or
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(iInstructionCode = '0' & x"D") or
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(iInstructionCode = '0' & x"E") or
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(iInstructionCode = '0' & x"F")) else '0';
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iCompare <= '1' when ( iInstructionCode = '0' & x"A" ) else '0';
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-- Logic Group
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iLoad <= '1' when ( iInstructionCode = '0' & x"0" ) else '0';
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iLogic <= '1' when ((iInstructionCode = '0' & x"5") or
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(iInstructionCode = '0' & x"6") or
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(iInstructionCode = '0' & x"7")) else '0';
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iTest <= '1' when ( iInstructionCode = '0' & x"9" ) else '0';
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-- Shift and Rotate Group
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iShift <= '1' when ( iInstructionCode = '1' & x"0" ) else '0';
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-- Storage Group
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iStore <= '1' when ( iInstructionCode = '1' & x"7" ) else '0';
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iFetch <= '1' when ( iInstructionCode = '0' & x"3" ) else '0';
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-- Input/Ouput Group
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iInput <= '1' when ( iInstructionCode = '0' & x"2" ) else '0';
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iOuput <= '1' when ( iInstructionCode = '1' & x"6" ) else '0';
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-- Program Control Group
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iJump <= '1' when ( iInstructionCode = '1' & x"A" ) else '0';
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iCall <= '1' when ( iInstructionCode = '1' & x"8" ) else '0';
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iReturn <= '1' when ( iInstructionCode = '1' & x"5" ) else '0';
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-- Interrupt Group
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iReturnI <= '1' when ( iInstructionCode = '1' & x"C" ) else '0';
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-- TODO : The ENABLE INTERRUPT instruction must clear the "iIEvent" bit if is set while the interrupts are disabled.
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iSetInterrupt <= '1' when ( iInstructionCode = '1' & x"E" ) else '0';
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-- Reserved for extension 6
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-- STAR = '0' & "B"
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-- TESTCY = '0' & "7"
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-- COMPARECY = '0' & "F"
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-- REGBANK = '1' & "B"
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-- OUTPUTK = '1' & "5"
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-- CALL@ = '1' & "2"
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-- LOAD&RETURN = '1' & "0"
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-- HWBUILD = '0' & "A"
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-- Wishbone instructions
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iWBRdSing <= '1' when ( iInstructionCode = '0' & x"1" ) else '0';
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iWBWrSing <= '1' when ( iInstructionCode = '0' & x"4" ) else '0';
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--------------------------------------------------------------------------------
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-- CONTROL SIGNAL
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--------------------------------------------------------------------------------
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-- Flow
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iIEWrite <= (Phase2_i and (iSetInterrupt or iReturnI));
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-- Banc
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iBancWrite <= (Phase2_i and (iAddSub or iLoad or iLogic or iShift or iFetch or iInput));
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-- Scratch
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iScratchWrite <= (Phase2_i and (iStore));
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-- Alu
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iOperationSelect <= "000" when (iShift='1') else
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"001" when (iLogic='1' or iTest='1') else
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"010" when (iAddSub='1' or iCompare='1') else
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"011" when (iLoad='1') else
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"111";
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-- Flags
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iFlagsWrite <= (Phase2_i and (iAddSub or iCompare or iLogic or iTest or iShift));
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iFlagsPush <= (Phase2_i and (IEvent_i));
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iFlagsPop <= (Phase2_i and (iReturnI));
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--------------------------------------------------------------------------------
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-- Outputs
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--------------------------------------------------------------------------------
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Fetch_o <= iFetch ;
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Input_o <= iInput ;
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Ouput_o <= iOuput ;
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Jump_o <= iJump ;
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Call_o <= iCall ;
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Return_o <= iReturn ;
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ReturnI_o <= iReturnI ;
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IEWrite_o <= iIEWrite ;
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BancWrite_o <= iBancWrite ;
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ScratchWrite_o <= iScratchWrite ;
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OperationSelect_o <= iOperationSelect ;
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FlagsWrite_o <= iFlagsWrite ;
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FlagsPush_o <= iFlagsPush ;
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FlagsPop_o <= iFlagsPop ;
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aaa_o <= iaaa ;
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kk_o <= ikk ;
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ss_o <= iss ;
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pp_o <= ipp ;
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SxPtr_o <= iSxPtr ;
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SyPtr_o <= iSyPtr ;
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OperandSelect_o <= iOperandSelect ;
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ArithOper_o <= iArithOper ;
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LogicOper_o <= iLogicOper ;
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ShiftBit_o <= iShiftBit ;
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ShiftSens_o <= iShiftSens ;
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ConditionCtrl_o <= iConditionCtrl ;
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IEValue_o <= iIEValue ;
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wbRdSing_o <= iWBRdSing ;
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wbWrSing_o <= iWBWrSing ;
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end rtl;
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