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[/] [copyblaze/] [trunk/] [copyblaze/] [rtl/] [vhdl/] [ip/] [wb_timer/] [wb_timer.vhd] - Blame information for rev 59

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-----------------------------------------------------------------------------
-- Wishbone TIMER -----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity wb_timer is
   port (
      clk      : in  std_logic;
      reset    : in  std_logic;
      -- Wishbone bus
      wb_adr_i : in  std_logic_vector(31 downto 0);
      wb_dat_i : in  std_logic_vector(31 downto 0);
      wb_dat_o : out std_logic_vector(31 downto 0);
      wb_sel_i : in  std_logic_vector( 3 downto 0);
      wb_cyc_i : in  std_logic;
      wb_stb_i : in  std_logic;
      wb_ack_o : out std_logic;
      wb_we_i  : in  std_logic;
      wb_irq0_o: out std_logic;
      wb_irq1_o: out std_logic );
end wb_timer;
 
-----------------------------------------------------------------------------
-- 0x00: TCR0          Timer Control and Status Register
-- 0x04: COMPARE0
-- 0x08: COUNTER0
-- 0x0C: TCR1
-- 0x10: COMPARE1
-- 0x14: COUNTER1
--
-- TCRx:
-- 
--   +-----------------------------------+-----+-----+--------+-------+
--   |     ZEROs (31 downto 4)           | en0 | ar0 | irq0en | trig0 |
--   +-----------------------------------+-----+-----+--------+-------+
--
 
-----------------------------------------------------------------------------
-- Implementation -----------------------------------------------------------
architecture rtl of wb_timer is
 
signal wbactive      : std_logic;
 
signal counter0      : unsigned(31 downto 0);
signal counter1      : unsigned(31 downto 0);
 
signal compare0      : unsigned(31 downto 0);
signal compare1      : unsigned(31 downto 0);
 
signal en0, en1      : std_logic;     -- Enable counter
signal ar0, ar1      : std_logic;     -- Auto Reload
signal trig0, trig1  : std_logic;     -- Triggered
 
signal irq0en, irq1en: std_logic;     -- Enable Interrupt
 
signal tcr0, tcr1    : std_logic_vector(31 downto 0);
 
 
begin
 
-----------------------------------------------------------------------------
-- Wishbone handling --------------------------------------------------------
wbactive <= wb_stb_i and wb_cyc_i;
 
wb_ack_o <= wbactive;
 
wb_dat_o <= tcr0                        when wbactive='1' and wb_adr_i(7 downto 0)=x"00" else
            std_logic_vector(compare0)  when wbactive='1' and wb_adr_i(7 downto 0)=x"04" else
            std_logic_vector(counter0)  when wbactive='1' and wb_adr_i(7 downto 0)=x"08" else
            tcr1                        when wbactive='1' and wb_adr_i(7 downto 0)=x"0C" else
            std_logic_vector(compare1)  when wbactive='1' and wb_adr_i(7 downto 0)=x"10" else
            std_logic_vector(counter1)  when wbactive='1' and wb_adr_i(7 downto 0)=x"14" else
            (others => '-');
 
wb_irq0_o <= trig0 and irq0en;
wb_irq1_o <= trig1 and irq1en;
 
tcr0 <= "0000000000000000000000000000" & en0 & ar0 & irq0en & trig0;
tcr1 <= "0000000000000000000000000000" & en1 & ar1 & irq1en & trig1;
 
timerproc: process (reset, clk) is
variable val : std_logic_vector(31 downto 0);
begin
        if reset='1' then
                en0       <= '0';      -- enable
                en1       <= '0';
                ar0       <= '0';      -- auto reload
                ar1       <= '0';
                trig0     <= '0';      -- triggered
                trig1     <= '0';
                irq0en    <= '0';      -- IRQ enable
                irq1en    <= '0';
                compare0  <= TO_UNSIGNED(0, 32);        -- compare
                compare1  <= TO_UNSIGNED(0, 32);
                counter0  <= TO_UNSIGNED(0, 32);        -- actual counter
                counter1  <= TO_UNSIGNED(0, 32);
        elsif clk'event and clk='1' then
 
                -- Reset trigX on TCR access --------------------------------
                if wbactive='1' and wb_adr_i(7 downto 0)=x"00" then
                        trig0 <= '0';
                end if;
                if wbactive='1' and wb_adr_i(7 downto 0)=x"0C" then
                        trig1 <= '0';
                end if;
 
                -- WB write register ----------------------------------------
                if wbactive='1' and wb_we_i='1' then
 
                        -- decode WB_SEL_I --
                        if wb_sel_i(3)='1' then
                                val(31 downto 24) := wb_dat_i(31 downto 24);
                        end if;
                        if wb_sel_i(2)='1' then
                                val(23 downto 16) := wb_dat_i(23 downto 16);
                        end if;
                        if wb_sel_i(1)='1' then
                                val(15 downto  8) := wb_dat_i(15 downto  8);
                        end if;
                        if wb_sel_i(0)='1' then
                                val( 7 downto  0) := wb_dat_i( 7 downto  0);
                        end if;
 
                        -- decode WB_ADR_I --
                        if wb_adr_i(7 downto 0)=x"00" then
                                en0    <= val(3);
                                ar0    <= val(2);
                                irq0en <= val(1);
                        elsif wb_adr_i(7 downto 0)=x"04" then
                                compare0 <= unsigned(val);
                        elsif wb_adr_i(7 downto 0)=x"08" then
                                counter0 <= unsigned(val);
                        elsif wb_adr_i(7 downto 0)=x"0C" then
                                en1    <= val(3);
                                ar1    <= val(2);
                                irq1en <= val(1);
                        elsif wb_adr_i(7 downto 0)=x"10" then
                                compare1 <= unsigned(val);
                        elsif wb_adr_i(7 downto 0)=x"14" then
                                counter1 <= unsigned(val);
                        end if;
                end if;
 
 
                -- timer0 ---------------------------------------------------
                if en0='1' then
                        if counter0 = compare0 then
                                trig0 <= '1';
                                if ar0='1' then
                                        counter0 <= to_unsigned(1, 32);
                                else
                                        en0 <= '0';
                                end if;
                        else
                                counter0 <= counter0 + 1;
                        end if;
                end if;
 
                -- timer1 ---------------------------------------------------
                if en1='1' then
                        if counter1 = compare1 then
                                trig1 <= '1';
                                if ar1='1' then
                                        counter1 <= to_unsigned(1, 32);
                                else
                                        en1 <= '0';
                                end if;
                        else
                                counter1 <= counter1 + 1;
                        end if;
                end if;
 
        end if;
end process;
 
end rtl;

Line No.	Rev	Author	Line
1	16	ameziti	`-----------------------------------------------------------------------------`
2			`-- Wishbone TIMER -----------------------------------------------------------`
3			`library ieee;`
4			`use ieee.std_logic_1164.all;`
5			`use ieee.numeric_std.all;`
6
7			`entity wb_timer is`
8			`port (`
9			`clk : in std_logic;`
10			`reset : in std_logic;`
11			`-- Wishbone bus`
12			`wb_adr_i : in std_logic_vector(31 downto 0);`
13			`wb_dat_i : in std_logic_vector(31 downto 0);`
14			`wb_dat_o : out std_logic_vector(31 downto 0);`
15			`wb_sel_i : in std_logic_vector( 3 downto 0);`
16			`wb_cyc_i : in std_logic;`
17			`wb_stb_i : in std_logic;`
18			`wb_ack_o : out std_logic;`
19			`wb_we_i : in std_logic;`
20			`wb_irq0_o: out std_logic;`
21			`wb_irq1_o: out std_logic );`
22			`end wb_timer;`
23
24			`-----------------------------------------------------------------------------`
25			`-- 0x00: TCR0 Timer Control and Status Register`
26			`-- 0x04: COMPARE0`
27			`-- 0x08: COUNTER0`
28			`-- 0x0C: TCR1`
29			`-- 0x10: COMPARE1`
30			`-- 0x14: COUNTER1`
31			`--`
32			`-- TCRx:`
33			`--`
34			`-- +-----------------------------------+-----+-----+--------+-------+`
35			`-- \| ZEROs (31 downto 4) \| en0 \| ar0 \| irq0en \| trig0 \|`
36			`-- +-----------------------------------+-----+-----+--------+-------+`
37			`--`
38
39			`-----------------------------------------------------------------------------`
40			`-- Implementation -----------------------------------------------------------`
41			`architecture rtl of wb_timer is`
42
43			`signal wbactive : std_logic;`
44
45			`signal counter0 : unsigned(31 downto 0);`
46			`signal counter1 : unsigned(31 downto 0);`
47
48			`signal compare0 : unsigned(31 downto 0);`
49			`signal compare1 : unsigned(31 downto 0);`
50
51			`signal en0, en1 : std_logic; -- Enable counter`
52			`signal ar0, ar1 : std_logic; -- Auto Reload`
53			`signal trig0, trig1 : std_logic; -- Triggered`
54
55			`signal irq0en, irq1en: std_logic; -- Enable Interrupt`
56
57			`signal tcr0, tcr1 : std_logic_vector(31 downto 0);`
58
59
60			`begin`
61
62			`-----------------------------------------------------------------------------`
63			`-- Wishbone handling --------------------------------------------------------`
64			`wbactive <= wb_stb_i and wb_cyc_i;`
65
66			`wb_ack_o <= wbactive;`
67
68			`wb_dat_o <= tcr0 when wbactive='1' and wb_adr_i(7 downto 0)=x"00" else`
69			`std_logic_vector(compare0) when wbactive='1' and wb_adr_i(7 downto 0)=x"04" else`
70			`std_logic_vector(counter0) when wbactive='1' and wb_adr_i(7 downto 0)=x"08" else`
71			`tcr1 when wbactive='1' and wb_adr_i(7 downto 0)=x"0C" else`
72			`std_logic_vector(compare1) when wbactive='1' and wb_adr_i(7 downto 0)=x"10" else`
73			`std_logic_vector(counter1) when wbactive='1' and wb_adr_i(7 downto 0)=x"14" else`
74			`(others => '-');`
75
76			`wb_irq0_o <= trig0 and irq0en;`
77			`wb_irq1_o <= trig1 and irq1en;`
78
79			`tcr0 <= "0000000000000000000000000000" & en0 & ar0 & irq0en & trig0;`
80			`tcr1 <= "0000000000000000000000000000" & en1 & ar1 & irq1en & trig1;`
81
82			`timerproc: process (reset, clk) is`
83			`variable val : std_logic_vector(31 downto 0);`
84			`begin`
85			`if reset='1' then`
86			`en0 <= '0'; -- enable`
87			`en1 <= '0';`
88			`ar0 <= '0'; -- auto reload`
89			`ar1 <= '0';`
90			`trig0 <= '0'; -- triggered`
91			`trig1 <= '0';`
92			`irq0en <= '0'; -- IRQ enable`
93			`irq1en <= '0';`
94			`compare0 <= TO_UNSIGNED(0, 32); -- compare`
95			`compare1 <= TO_UNSIGNED(0, 32);`
96			`counter0 <= TO_UNSIGNED(0, 32); -- actual counter`
97			`counter1 <= TO_UNSIGNED(0, 32);`
98			`elsif clk'event and clk='1' then`
99
100			`-- Reset trigX on TCR access --------------------------------`
101			`if wbactive='1' and wb_adr_i(7 downto 0)=x"00" then`
102			`trig0 <= '0';`
103			`end if;`
104			`if wbactive='1' and wb_adr_i(7 downto 0)=x"0C" then`
105			`trig1 <= '0';`
106			`end if;`
107
108			`-- WB write register ----------------------------------------`
109			`if wbactive='1' and wb_we_i='1' then`
110
111			`-- decode WB_SEL_I --`
112			`if wb_sel_i(3)='1' then`
113			`val(31 downto 24) := wb_dat_i(31 downto 24);`
114			`end if;`
115			`if wb_sel_i(2)='1' then`
116			`val(23 downto 16) := wb_dat_i(23 downto 16);`
117			`end if;`
118			`if wb_sel_i(1)='1' then`
119			`val(15 downto 8) := wb_dat_i(15 downto 8);`
120			`end if;`
121			`if wb_sel_i(0)='1' then`
122			`val( 7 downto 0) := wb_dat_i( 7 downto 0);`
123			`end if;`
124
125			`-- decode WB_ADR_I --`
126			`if wb_adr_i(7 downto 0)=x"00" then`
127			`en0 <= val(3);`
128			`ar0 <= val(2);`
129			`irq0en <= val(1);`
130			`elsif wb_adr_i(7 downto 0)=x"04" then`
131			`compare0 <= unsigned(val);`
132			`elsif wb_adr_i(7 downto 0)=x"08" then`
133			`counter0 <= unsigned(val);`
134			`elsif wb_adr_i(7 downto 0)=x"0C" then`
135			`en1 <= val(3);`
136			`ar1 <= val(2);`
137			`irq1en <= val(1);`
138			`elsif wb_adr_i(7 downto 0)=x"10" then`
139			`compare1 <= unsigned(val);`
140			`elsif wb_adr_i(7 downto 0)=x"14" then`
141			`counter1 <= unsigned(val);`
142			`end if;`
143			`end if;`
144
145
146			`-- timer0 ---------------------------------------------------`
147			`if en0='1' then`
148			`if counter0 = compare0 then`
149			`trig0 <= '1';`
150			`if ar0='1' then`
151			`counter0 <= to_unsigned(1, 32);`
152			`else`
153			`en0 <= '0';`
154			`end if;`
155			`else`
156			`counter0 <= counter0 + 1;`
157			`end if;`
158			`end if;`
159
160			`-- timer1 ---------------------------------------------------`
161			`if en1='1' then`
162			`if counter1 = compare1 then`
163			`trig1 <= '1';`
164			`if ar1='1' then`
165			`counter1 <= to_unsigned(1, 32);`
166			`else`
167			`en1 <= '0';`
168			`end if;`
169			`else`
170			`counter1 <= counter1 + 1;`
171			`end if;`
172			`end if;`
173
174			`end if;`
175			`end process;`
176
177			`end rtl;`

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[/] [copyblaze/] [trunk/] [copyblaze/] [rtl/] [vhdl/] [ip/] [wb_timer/] [wb_timer.vhd] - Blame information for rev 59