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[/] [copyblaze/] [trunk/] [copyblaze/] [rtl/] [vhdl/] [ip/] [wb_uart/] [uart.vhd] - Blame information for rev 59

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
-----------------------------------------------------------------------------
-- UART ---------------------------------------------------------------------
entity myuart is
        port (
                clk       : in  std_ulogic;
                reset     : in  std_ulogic;
                --
                divisor   : in  std_ulogic_vector(15 downto 0);
                txdata    : in  std_ulogic_vector( 7 downto 0);
                rxdata    : out std_ulogic_vector( 7 downto 0);
                wr        : in  std_ulogic;
                rd        : in  std_ulogic;
                tx_avail  : out std_ulogic;
                tx_busy   : out std_ulogic;
                rx_avail  : out std_ulogic;
                rx_full   : out std_ulogic;
                rx_error  : out std_ulogic;
                -- 
                uart_rxd  : in  std_ulogic;
                uart_txd  : out std_ulogic );
end myuart;
 
-----------------------------------------------------------------------------
-- implementation -----------------------------------------------------------
architecture rtl of myuart is
 
-----------------------------------------------------------------------------
-- component declarations ---------------------------------------------------
component uart_rx is
        port (
                clk      : in  std_ulogic;
                reset    : in  std_ulogic;
                --
                divisor  : in  std_ulogic_vector(15 downto 0);
                dout     : out std_ulogic_vector(7 downto 0);
                avail    : out std_ulogic;
                error    : out std_ulogic;
                clear    : in  std_ulogic;
                --
                rxd      : in  std_ulogic );
end component;
 
component uart_tx is
        port (
                clk      : in  std_ulogic;
                reset    : in  std_ulogic;
                --  
                divisor  : in  std_ulogic_vector(15 downto 0);
                din      : in  std_ulogic_vector(7 downto 0);
                wr       : in  std_ulogic;
                busy     : out std_ulogic;
                --
                txd      : out std_ulogic );
end component;
 
-----------------------------------------------------------------------------
-- local signals ------------------------------------------------------------
signal utx_busy   : std_ulogic;
signal utx_wr     : std_ulogic;
 
signal urx_dout   : std_ulogic_vector(7 downto 0);
signal urx_avail  : std_ulogic;
signal urx_clear  : std_ulogic;
signal urx_error  : std_ulogic;
 
signal txbuf      : std_ulogic_vector(7 downto 0);
signal txbuf_full : std_ulogic;
signal rxbuf      : std_ulogic_vector(7 downto 0);
signal rxbuf_full : std_ulogic;
 
begin
 
iotxproc: process(clk) is
begin
        if clk'event and clk='1' then
                if reset='1' then
                        utx_wr     <= '0';
                        txbuf_full <= '0';
 
                        urx_clear  <= '0';
                        rxbuf_full <= '0';
                else
                        -- TX Buffer Logic
                        if  wr='1' and not txbuf_full='1' then
                                txbuf      <= txdata;
                                txbuf_full <= '1';
                        end if;
 
                        if txbuf_full='1' and utx_busy='0' then
                                utx_wr     <= '1';
                                txbuf_full <= '0';
                        else
                                utx_wr     <= '0';
                        end if;
 
                        -- RX Buffer Logic
                        if rd='1' then
                                rxbuf_full <= '0';
                        end if;
 
                        if urx_avail='1' and rxbuf_full='0' then
                                rxbuf      <= urx_dout;
                                rxbuf_full <= '1';
                                urx_clear  <= '1';
                        else
                                urx_clear  <= '0';
                        end if;
                end if;
        end if;
end process;
 
rxdata   <= rxbuf;
rx_avail <= rxbuf_full and not rd;
rx_full  <= rxbuf_full and urx_avail and not rd;
rx_error <= urx_error;
 
tx_busy  <= utx_busy or txbuf_full; -- or wr;
tx_avail <= not txbuf_full;
 
-- Instantiate RX and TX engine
uart_rx0: uart_rx
        port map (
                clk     => clk,
                reset   => reset,
                --
                divisor => divisor,
                dout    => urx_dout,
                avail   => urx_avail,
                error   => urx_error,
                clear   => urx_clear,
                --
                rxd     => uart_rxd );
 
uart_tx0: uart_tx
        port map (
                clk     => clk,
                reset   => reset,
                --
                divisor => divisor,
                din     => txbuf,
                wr      => utx_wr,
                busy    => utx_busy,
                --
                txd     => uart_txd );
end rtl;

Line No.	Rev	Author	Line
1	16	ameziti	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3	41	ameziti	`use ieee.numeric_std.all;`
4	16	ameziti
5			`-----------------------------------------------------------------------------`
6			`-- UART ---------------------------------------------------------------------`
7			`entity myuart is`
8			`port (`
9	41	ameziti	`clk : in std_ulogic;`
10			`reset : in std_ulogic;`
11	16	ameziti	`--`
12	41	ameziti	`divisor : in std_ulogic_vector(15 downto 0);`
13			`txdata : in std_ulogic_vector( 7 downto 0);`
14			`rxdata : out std_ulogic_vector( 7 downto 0);`
15			`wr : in std_ulogic;`
16			`rd : in std_ulogic;`
17			`tx_avail : out std_ulogic;`
18			`tx_busy : out std_ulogic;`
19			`rx_avail : out std_ulogic;`
20			`rx_full : out std_ulogic;`
21			`rx_error : out std_ulogic;`
22	16	ameziti	`--`
23	41	ameziti	`uart_rxd : in std_ulogic;`
24			`uart_txd : out std_ulogic );`
25	16	ameziti	`end myuart;`
26
27			`-----------------------------------------------------------------------------`
28			`-- implementation -----------------------------------------------------------`
29			`architecture rtl of myuart is`
30
31			`-----------------------------------------------------------------------------`
32			`-- component declarations ---------------------------------------------------`
33			`component uart_rx is`
34			`port (`
35	41	ameziti	`clk : in std_ulogic;`
36			`reset : in std_ulogic;`
37	16	ameziti	`--`
38	41	ameziti	`divisor : in std_ulogic_vector(15 downto 0);`
39			`dout : out std_ulogic_vector(7 downto 0);`
40			`avail : out std_ulogic;`
41			`error : out std_ulogic;`
42			`clear : in std_ulogic;`
43	16	ameziti	`--`
44	41	ameziti	`rxd : in std_ulogic );`
45	16	ameziti	`end component;`
46
47			`component uart_tx is`
48			`port (`
49	41	ameziti	`clk : in std_ulogic;`
50			`reset : in std_ulogic;`
51	16	ameziti	`--`
52	41	ameziti	`divisor : in std_ulogic_vector(15 downto 0);`
53			`din : in std_ulogic_vector(7 downto 0);`
54			`wr : in std_ulogic;`
55			`busy : out std_ulogic;`
56	16	ameziti	`--`
57	41	ameziti	`txd : out std_ulogic );`
58	16	ameziti	`end component;`
59
60			`-----------------------------------------------------------------------------`
61			`-- local signals ------------------------------------------------------------`
62	41	ameziti	`signal utx_busy : std_ulogic;`
63			`signal utx_wr : std_ulogic;`
64	16	ameziti
65	41	ameziti	`signal urx_dout : std_ulogic_vector(7 downto 0);`
66			`signal urx_avail : std_ulogic;`
67			`signal urx_clear : std_ulogic;`
68			`signal urx_error : std_ulogic;`
69	16	ameziti
70	41	ameziti	`signal txbuf : std_ulogic_vector(7 downto 0);`
71			`signal txbuf_full : std_ulogic;`
72			`signal rxbuf : std_ulogic_vector(7 downto 0);`
73			`signal rxbuf_full : std_ulogic;`
74	16	ameziti
75			`begin`
76
77			`iotxproc: process(clk) is`
78			`begin`
79			`if clk'event and clk='1' then`
80			`if reset='1' then`
81			`utx_wr <= '0';`
82			`txbuf_full <= '0';`
83
84			`urx_clear <= '0';`
85			`rxbuf_full <= '0';`
86			`else`
87			`-- TX Buffer Logic`
88			`if wr='1' and not txbuf_full='1' then`
89			`txbuf <= txdata;`
90			`txbuf_full <= '1';`
91			`end if;`
92
93			`if txbuf_full='1' and utx_busy='0' then`
94			`utx_wr <= '1';`
95			`txbuf_full <= '0';`
96			`else`
97			`utx_wr <= '0';`
98			`end if;`
99
100			`-- RX Buffer Logic`
101			`if rd='1' then`
102			`rxbuf_full <= '0';`
103			`end if;`
104
105			`if urx_avail='1' and rxbuf_full='0' then`
106			`rxbuf <= urx_dout;`
107			`rxbuf_full <= '1';`
108			`urx_clear <= '1';`
109			`else`
110			`urx_clear <= '0';`
111			`end if;`
112			`end if;`
113			`end if;`
114			`end process;`
115
116			`rxdata <= rxbuf;`
117			`rx_avail <= rxbuf_full and not rd;`
118			`rx_full <= rxbuf_full and urx_avail and not rd;`
119			`rx_error <= urx_error;`
120
121			`tx_busy <= utx_busy or txbuf_full; -- or wr;`
122			`tx_avail <= not txbuf_full;`
123
124			`-- Instantiate RX and TX engine`
125			`uart_rx0: uart_rx`
126			`port map (`
127			`clk => clk,`
128			`reset => reset,`
129			`--`
130			`divisor => divisor,`
131			`dout => urx_dout,`
132			`avail => urx_avail,`
133			`error => urx_error,`
134			`clear => urx_clear,`
135			`--`
136			`rxd => uart_rxd );`
137
138			`uart_tx0: uart_tx`
139			`port map (`
140			`clk => clk,`
141			`reset => reset,`
142			`--`
143			`divisor => divisor,`
144			`din => txbuf,`
145			`wr => utx_wr,`
146			`busy => utx_busy,`
147			`--`
148			`txd => uart_txd );`
149			`end rtl;`

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[/] [copyblaze/] [trunk/] [copyblaze/] [rtl/] [vhdl/] [ip/] [wb_uart/] [uart.vhd] - Blame information for rev 59