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[/] [copyblaze/] [trunk/] [copyblaze/] [rtl/] [vhdl/] [ip/] [wb_uart/] [uart_rx.vhd] - Blame information for rev 63

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
-----------------------------------------------------------------------------
-- UART Receiver ------------------------------------------------------------
entity uart_rx is
        port (
                clk      : in  std_ulogic;
                reset    : in  std_ulogic;
                --
                divisor  : in  std_ulogic_vector(15 downto 0);
                dout     : out std_ulogic_vector( 7 downto 0);
                avail    : out std_ulogic;
                error    : out std_ulogic;
                clear    : in  std_ulogic;
                --
                rxd      : in  std_ulogic );
end uart_rx;
 
-----------------------------------------------------------------------------
-- Implemenattion -----------------------------------------------------------
architecture rtl of uart_rx is
 
-- Signals
signal bitcount  : integer range 0 to 10;
signal count     : unsigned(15 downto 0);
signal shiftreg  : std_ulogic_vector(7 downto 0);
signal rxh       : std_ulogic_vector(2 downto 0);
signal rxd2      : std_ulogic;
 
begin
 
proc: process(clk, reset) is
begin
        if clk'event and clk='1' then
        if reset='1' then
                count    <= (others => '0');
                bitcount <= 0;
                error    <= '0';
                avail    <= '0';
        else
                if clear='1' then
                        error <= '0';
                        avail <= '0';
                end if;
 
                if count/=0 then
                        count <= count - 1;
                else
                        if bitcount=0 then     -- wait for startbit
                                if rxd2='0' then     -- FOUND
                                        count    <= unsigned("0" & divisor(15 downto 1) );
                                        bitcount <= bitcount + 1;
                                end if;
                        elsif bitcount=1 then  -- sample mid of startbit
                                if rxd2='0' then     -- OK
                                        count    <= unsigned(divisor);
                                        bitcount <= bitcount + 1;
                                        shiftreg <= "00000000";
                                else                -- ERROR
                                        error    <= '1';
                                        bitcount <= 0;
                                end if;
                        elsif bitcount=10 then -- stopbit
--                              if rxd2='1' then     -- OK
                                        bitcount <= 0;
                                        dout     <= shiftreg;
                                        avail    <= '1';
--                              else                -- ERROR
--                                      error    <= '1';
--                              end if;
                        else
                                shiftreg(6 downto 0) <= shiftreg(7 downto 1);
                                shiftreg(7) <= rxd2;
                                count    <= unsigned(divisor);
                                bitcount <= bitcount + 1;
                        end if;
                end if;
        end if;
        end if;
end process;
 
-----------------------------------------------------------------------------
-- Sync incoming RXD (anti metastable) --------------------------------------
syncproc: process(reset, clk) is
begin
        if reset='1' then
                rxh  <= (others => '1');
                rxd2 <= '1';
        elsif clk'event and clk='1' then
                rxh <= rxh(1 downto 0) & rxd;
                if rxh="111" then
                        rxd2 <= '1';
                elsif rxh="000" then
                        rxd2 <= '0';
                end if;
        end if;
end process;
 
end rtl;
 

Line No.	Rev	Author	Line
1	16	ameziti	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.numeric_std.all;`
4
5			`-----------------------------------------------------------------------------`
6			`-- UART Receiver ------------------------------------------------------------`
7			`entity uart_rx is`
8			`port (`
9	41	ameziti	`clk : in std_ulogic;`
10			`reset : in std_ulogic;`
11	16	ameziti	`--`
12	41	ameziti	`divisor : in std_ulogic_vector(15 downto 0);`
13			`dout : out std_ulogic_vector( 7 downto 0);`
14			`avail : out std_ulogic;`
15			`error : out std_ulogic;`
16			`clear : in std_ulogic;`
17	16	ameziti	`--`
18	41	ameziti	`rxd : in std_ulogic );`
19	16	ameziti	`end uart_rx;`
20
21			`-----------------------------------------------------------------------------`
22			`-- Implemenattion -----------------------------------------------------------`
23			`architecture rtl of uart_rx is`
24
25			`-- Signals`
26			`signal bitcount : integer range 0 to 10;`
27			`signal count : unsigned(15 downto 0);`
28	41	ameziti	`signal shiftreg : std_ulogic_vector(7 downto 0);`
29			`signal rxh : std_ulogic_vector(2 downto 0);`
30			`signal rxd2 : std_ulogic;`
31	16	ameziti
32			`begin`
33
34			`proc: process(clk, reset) is`
35			`begin`
36			`if clk'event and clk='1' then`
37			`if reset='1' then`
38			`count <= (others => '0');`
39			`bitcount <= 0;`
40			`error <= '0';`
41			`avail <= '0';`
42			`else`
43			`if clear='1' then`
44			`error <= '0';`
45			`avail <= '0';`
46			`end if;`
47
48			`if count/=0 then`
49			`count <= count - 1;`
50			`else`
51			`if bitcount=0 then -- wait for startbit`
52			`if rxd2='0' then -- FOUND`
53			`count <= unsigned("0" & divisor(15 downto 1) );`
54			`bitcount <= bitcount + 1;`
55			`end if;`
56			`elsif bitcount=1 then -- sample mid of startbit`
57			`if rxd2='0' then -- OK`
58			`count <= unsigned(divisor);`
59			`bitcount <= bitcount + 1;`
60			`shiftreg <= "00000000";`
61			`else -- ERROR`
62			`error <= '1';`
63			`bitcount <= 0;`
64			`end if;`
65			`elsif bitcount=10 then -- stopbit`
66			`-- if rxd2='1' then -- OK`
67			`bitcount <= 0;`
68			`dout <= shiftreg;`
69			`avail <= '1';`
70			`-- else -- ERROR`
71			`-- error <= '1';`
72			`-- end if;`
73			`else`
74			`shiftreg(6 downto 0) <= shiftreg(7 downto 1);`
75			`shiftreg(7) <= rxd2;`
76			`count <= unsigned(divisor);`
77			`bitcount <= bitcount + 1;`
78			`end if;`
79			`end if;`
80			`end if;`
81			`end if;`
82			`end process;`
83
84			`-----------------------------------------------------------------------------`
85			`-- Sync incoming RXD (anti metastable) --------------------------------------`
86			`syncproc: process(reset, clk) is`
87			`begin`
88			`if reset='1' then`
89			`rxh <= (others => '1');`
90			`rxd2 <= '1';`
91			`elsif clk'event and clk='1' then`
92			`rxh <= rxh(1 downto 0) & rxd;`
93			`if rxh="111" then`
94			`rxd2 <= '1';`
95			`elsif rxh="000" then`
96			`rxd2 <= '0';`
97			`end if;`
98			`end if;`
99			`end process;`
100
101			`end rtl;`
102

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[/] [copyblaze/] [trunk/] [copyblaze/] [rtl/] [vhdl/] [ip/] [wb_uart/] [uart_rx.vhd] - Blame information for rev 63