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component_name={name};

width_a=18;

depth_a=1024;

configuration_port_a=read_only;

port_a_enable_pin=false;

port_a_handshaking_pins=false;

port_a_register_inputs=false;

port_a_init_pin=false;

port_a_init_value=00000;

port_a_additional_output_pipe_stages = 0;

port_a_register_inputs = false;

port_a_active_clock_edge = Rising_Edge_Triggered;

width_b=18;

depth_b=1024;

configuration_port_b=read_and_write;

write_mode_port_b=read_after_write;

port_b_enable_pin=false;

port_b_handshaking_pins=false;

port_b_register_inputs=false;

port_b_init_pin=false;

port_b_init_value=00000;

port_b_additional_output_pipe_stages = 0;

port_b_register_inputs = false;

port_b_active_clock_edge = Rising_Edge_Triggered;

port_b_write_enable_polarity = Active_High;

memory_initialization_radix=16;

global_init_value=00000;

memory_initialization_vector=