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1 2 ameziti
////////////////////////////////////////////////////////////////////////////////
2
// Copyright (c) 2004 Xilinx, Inc.
3
// All Rights Reserved
4
////////////////////////////////////////////////////////////////////////////////
5
//   ____  ____
6
//  /   /\/   /
7
// /___/  \  /    Vendor: Xilinx
8
// \   \   \/     Version: 1.02
9
//  \   \         Filename: ROM_form.v
10
//  /   /         Date Last Modified:  September 7 2004
11
// /___/   /\     Date Created: July 2003
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// \   \  /  \
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//  \___\/\___\
14
//
15
//Device:       Xilinx
16
//Purpose:      
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//      This is the Verilog template file for the KCPSM3 assembler.
18
//      It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block 
19
//      RAM to act as a single port program ROM.
20
//
21
//      This Verilog file is not valid as input directly into a synthesis or 
22
//      simulation tool.        The assembler will read this template and insert the 
23
//      data required to complete the definition of program ROM and write it out 
24
//      to a new '.v' file associated with the name of the original '.psm' file 
25
//      being assembled.
26
//
27
//      This template can be modified to define alternative memory definitions 
28
//      such as dual port.  However, you are responsible for ensuring the template
29
//      is correct as the assembler does not perform any checking of the Verilog.
30
//
31
//      The assembler identifies all text enclosed by {} characters, and replaces 
32
//      these character strings. All templates should include these {} character 
33
//      strings for the assembler to work correctly. 
34
//
35
//      This template defines a block RAM configured in 1024 x 18-bit single port 
36
//      mode and conneceted to act as a single port ROM.
37
//
38
//Reference:
39
//      None
40
//Revision History:
41
//    Rev 1.00 - jc - Converted to verilog,  July 2003.
42
//    Rev 1.01 - sus - Added text to confirm to Xilinx HDL std,  August 4 2004.
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//    Rev 1.02 - njs - Added attributes for Synplicity  August 5 2004.
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//      Rev 1.03 - sus - Added text to conform to Xilinx generated 
45
//                              HDL spec, September 7 2004
46
//
47
////////////////////////////////////////////////////////////////////////////////
48
// Contact: e-mail  picoblaze@xilinx.com
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//////////////////////////////////////////////////////////////////////////////////
50
//
51
// Disclaimer: 
52
// LIMITED WARRANTY AND DISCLAIMER. These designs are
53
// provided to you "as is". Xilinx and its licensors make and you
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// receive no warranties or conditions, express, implied,
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// statutory or otherwise, and Xilinx specifically disclaims any
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// implied warranties of merchantability, non-infringement, or
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// fitness for a particular purpose. Xilinx does not warrant that
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// the functions contained in these designs will meet your
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// requirements, or that the operation of these designs will be
60
// uninterrupted or error free, or that defects in the Designs
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// will be corrected. Furthermore, Xilinx does not warrant or
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// make any representations regarding use or the results of the
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// use of the designs in terms of correctness, accuracy,
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// reliability, or otherwise.
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//
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// LIMITATION OF LIABILITY. In no event will Xilinx or its
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// licensors be liable for any loss of data, lost profits, cost
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// or procurement of substitute goods or services, or for any
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// special, incidental, consequential, or indirect damages
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// arising from the use or operation of the designs or
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// accompanying documentation, however caused and on any theory
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// of liability. This limitation will apply even if Xilinx
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// has been advised of the possibility of such damage. This
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// limitation shall apply not-withstanding the failure of the 
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// essential purpose of any limited remedies herein. 
76
//////////////////////////////////////////////////////////////////////////////////
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78
The next line is used to determine where the template actually starts and must exist.
79
{begin template}
80
////////////////////////////////////////////////////////////////////////////////
81
// Copyright (c) 2004 Xilinx, Inc.
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// All Rights Reserved
83
////////////////////////////////////////////////////////////////////////////////
84
//   ____  ____
85
//  /   /\/   /
86
// /___/  \  /    Vendor: Xilinx
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// \   \   \/     Version: v1.30
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//  \   \         Application : KCPSM3
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//  /   /         Filename: {name}.v
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// /___/   /\     
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// \   \  /  \
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//  \___\/\___\
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//
94
//Command: kcpsm3 {name}.psm
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//Device: Spartan-3, Spartan-3E, Virtex-II, and Virtex-II Pro FPGAs
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//Design Name: {name}
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//Generated {timestamp}.
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//Purpose:
99
//      {name} verilog program definition.
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//
101
//Reference:
102
//      PicoBlaze 8-bit Embedded Microcontroller User Guide
103
////////////////////////////////////////////////////////////////////////////////
104
 
105
`timescale 1 ps / 1ps
106
 
107
module {name} (address, instruction, clk);
108
 
109
input [9:0] address;
110
input clk;
111
 
112
output [17:0] instruction;
113
 
114
RAMB16_S18 ram_1024_x_18(
115
        .DI     (16'h0000),
116
        .DIP    (2'b00),
117
        .EN     (1'b1),
118
        .WE     (1'b0),
119
        .SSR    (1'b0),
120
        .CLK    (clk),
121
        .ADDR   (address),
122
        .DO     (instruction[15:0]),
123
        .DOP    (instruction[17:16]))
124
/*synthesis
125
init_00 = "{INIT_00}"
126
init_01 = "{INIT_01}"
127
init_02 = "{INIT_02}"
128
init_03 = "{INIT_03}"
129
init_04 = "{INIT_04}"
130
init_05 = "{INIT_05}"
131
init_06 = "{INIT_06}"
132
init_07 = "{INIT_07}"
133
init_08 = "{INIT_08}"
134
init_09 = "{INIT_09}"
135
init_0A = "{INIT_0A}"
136
init_0B = "{INIT_0B}"
137
init_0C = "{INIT_0C}"
138
init_0D = "{INIT_0D}"
139
init_0E = "{INIT_0E}"
140
init_0F = "{INIT_0F}"
141
init_10 = "{INIT_10}"
142
init_11 = "{INIT_11}"
143
init_12 = "{INIT_12}"
144
init_13 = "{INIT_13}"
145
init_14 = "{INIT_14}"
146
init_15 = "{INIT_15}"
147
init_16 = "{INIT_16}"
148
init_17 = "{INIT_17}"
149
init_18 = "{INIT_18}"
150
init_19 = "{INIT_19}"
151
init_1A = "{INIT_1A}"
152
init_1B = "{INIT_1B}"
153
init_1C = "{INIT_1C}"
154
init_1D = "{INIT_1D}"
155
init_1E = "{INIT_1E}"
156
init_1F = "{INIT_1F}"
157
init_20 = "{INIT_20}"
158
init_21 = "{INIT_21}"
159
init_22 = "{INIT_22}"
160
init_23 = "{INIT_23}"
161
init_24 = "{INIT_24}"
162
init_25 = "{INIT_25}"
163
init_26 = "{INIT_26}"
164
init_27 = "{INIT_27}"
165
init_28 = "{INIT_28}"
166
init_29 = "{INIT_29}"
167
init_2A = "{INIT_2A}"
168
init_2B = "{INIT_2B}"
169
init_2C = "{INIT_2C}"
170
init_2D = "{INIT_2D}"
171
init_2E = "{INIT_2E}"
172
init_2F = "{INIT_2F}"
173
init_30 = "{INIT_30}"
174
init_31 = "{INIT_31}"
175
init_32 = "{INIT_32}"
176
init_33 = "{INIT_33}"
177
init_34 = "{INIT_34}"
178
init_35 = "{INIT_35}"
179
init_36 = "{INIT_36}"
180
init_37 = "{INIT_37}"
181
init_38 = "{INIT_38}"
182
init_39 = "{INIT_39}"
183
init_3A = "{INIT_3A}"
184
init_3B = "{INIT_3B}"
185
init_3C = "{INIT_3C}"
186
init_3D = "{INIT_3D}"
187
init_3E = "{INIT_3E}"
188
init_3F = "{INIT_3F}"
189
initp_00 = "{INITP_00}"
190
initp_01 = "{INITP_01}"
191
initp_02 = "{INITP_02}"
192
initp_03 = "{INITP_03}"
193
initp_04 = "{INITP_04}"
194
initp_05 = "{INITP_05}"
195
initp_06 = "{INITP_06}"
196
initp_07 = "{INITP_07}" */;
197
 
198
// synthesis translate_off
199
// Attributes for Simulation
200
defparam ram_1024_x_18.INIT_00  = 256'h{INIT_00};
201
defparam ram_1024_x_18.INIT_01  = 256'h{INIT_01};
202
defparam ram_1024_x_18.INIT_02  = 256'h{INIT_02};
203
defparam ram_1024_x_18.INIT_03  = 256'h{INIT_03};
204
defparam ram_1024_x_18.INIT_04  = 256'h{INIT_04};
205
defparam ram_1024_x_18.INIT_05  = 256'h{INIT_05};
206
defparam ram_1024_x_18.INIT_06  = 256'h{INIT_06};
207
defparam ram_1024_x_18.INIT_07  = 256'h{INIT_07};
208
defparam ram_1024_x_18.INIT_08  = 256'h{INIT_08};
209
defparam ram_1024_x_18.INIT_09  = 256'h{INIT_09};
210
defparam ram_1024_x_18.INIT_0A  = 256'h{INIT_0A};
211
defparam ram_1024_x_18.INIT_0B  = 256'h{INIT_0B};
212
defparam ram_1024_x_18.INIT_0C  = 256'h{INIT_0C};
213
defparam ram_1024_x_18.INIT_0D  = 256'h{INIT_0D};
214
defparam ram_1024_x_18.INIT_0E  = 256'h{INIT_0E};
215
defparam ram_1024_x_18.INIT_0F  = 256'h{INIT_0F};
216
defparam ram_1024_x_18.INIT_10  = 256'h{INIT_10};
217
defparam ram_1024_x_18.INIT_11  = 256'h{INIT_11};
218
defparam ram_1024_x_18.INIT_12  = 256'h{INIT_12};
219
defparam ram_1024_x_18.INIT_13  = 256'h{INIT_13};
220
defparam ram_1024_x_18.INIT_14  = 256'h{INIT_14};
221
defparam ram_1024_x_18.INIT_15  = 256'h{INIT_15};
222
defparam ram_1024_x_18.INIT_16  = 256'h{INIT_16};
223
defparam ram_1024_x_18.INIT_17  = 256'h{INIT_17};
224
defparam ram_1024_x_18.INIT_18  = 256'h{INIT_18};
225
defparam ram_1024_x_18.INIT_19  = 256'h{INIT_19};
226
defparam ram_1024_x_18.INIT_1A  = 256'h{INIT_1A};
227
defparam ram_1024_x_18.INIT_1B  = 256'h{INIT_1B};
228
defparam ram_1024_x_18.INIT_1C  = 256'h{INIT_1C};
229
defparam ram_1024_x_18.INIT_1D  = 256'h{INIT_1D};
230
defparam ram_1024_x_18.INIT_1E  = 256'h{INIT_1E};
231
defparam ram_1024_x_18.INIT_1F  = 256'h{INIT_1F};
232
defparam ram_1024_x_18.INIT_20  = 256'h{INIT_20};
233
defparam ram_1024_x_18.INIT_21  = 256'h{INIT_21};
234
defparam ram_1024_x_18.INIT_22  = 256'h{INIT_22};
235
defparam ram_1024_x_18.INIT_23  = 256'h{INIT_23};
236
defparam ram_1024_x_18.INIT_24  = 256'h{INIT_24};
237
defparam ram_1024_x_18.INIT_25  = 256'h{INIT_25};
238
defparam ram_1024_x_18.INIT_26  = 256'h{INIT_26};
239
defparam ram_1024_x_18.INIT_27  = 256'h{INIT_27};
240
defparam ram_1024_x_18.INIT_28  = 256'h{INIT_28};
241
defparam ram_1024_x_18.INIT_29  = 256'h{INIT_29};
242
defparam ram_1024_x_18.INIT_2A  = 256'h{INIT_2A};
243
defparam ram_1024_x_18.INIT_2B  = 256'h{INIT_2B};
244
defparam ram_1024_x_18.INIT_2C  = 256'h{INIT_2C};
245
defparam ram_1024_x_18.INIT_2D  = 256'h{INIT_2D};
246
defparam ram_1024_x_18.INIT_2E  = 256'h{INIT_2E};
247
defparam ram_1024_x_18.INIT_2F  = 256'h{INIT_2F};
248
defparam ram_1024_x_18.INIT_30  = 256'h{INIT_30};
249
defparam ram_1024_x_18.INIT_31  = 256'h{INIT_31};
250
defparam ram_1024_x_18.INIT_32  = 256'h{INIT_32};
251
defparam ram_1024_x_18.INIT_33  = 256'h{INIT_33};
252
defparam ram_1024_x_18.INIT_34  = 256'h{INIT_34};
253
defparam ram_1024_x_18.INIT_35  = 256'h{INIT_35};
254
defparam ram_1024_x_18.INIT_36  = 256'h{INIT_36};
255
defparam ram_1024_x_18.INIT_37  = 256'h{INIT_37};
256
defparam ram_1024_x_18.INIT_38  = 256'h{INIT_38};
257
defparam ram_1024_x_18.INIT_39  = 256'h{INIT_39};
258
defparam ram_1024_x_18.INIT_3A  = 256'h{INIT_3A};
259
defparam ram_1024_x_18.INIT_3B  = 256'h{INIT_3B};
260
defparam ram_1024_x_18.INIT_3C  = 256'h{INIT_3C};
261
defparam ram_1024_x_18.INIT_3D  = 256'h{INIT_3D};
262
defparam ram_1024_x_18.INIT_3E  = 256'h{INIT_3E};
263
defparam ram_1024_x_18.INIT_3F  = 256'h{INIT_3F};
264
defparam ram_1024_x_18.INITP_00 = 256'h{INITP_00};
265
defparam ram_1024_x_18.INITP_01 = 256'h{INITP_01};
266
defparam ram_1024_x_18.INITP_02 = 256'h{INITP_02};
267
defparam ram_1024_x_18.INITP_03 = 256'h{INITP_03};
268
defparam ram_1024_x_18.INITP_04 = 256'h{INITP_04};
269
defparam ram_1024_x_18.INITP_05 = 256'h{INITP_05};
270
defparam ram_1024_x_18.INITP_06 = 256'h{INITP_06};
271
defparam ram_1024_x_18.INITP_07 = 256'h{INITP_07};
272
 
273
// synthesis translate_on
274
// Attributes for XST (Synplicity attributes are in-line)
275
// synthesis attribute INIT_00  of ram_1024_x_18 is "{INIT_00}"
276
// synthesis attribute INIT_01  of ram_1024_x_18 is "{INIT_01}"
277
// synthesis attribute INIT_02  of ram_1024_x_18 is "{INIT_02}"
278
// synthesis attribute INIT_03  of ram_1024_x_18 is "{INIT_03}"
279
// synthesis attribute INIT_04  of ram_1024_x_18 is "{INIT_04}"
280
// synthesis attribute INIT_05  of ram_1024_x_18 is "{INIT_05}"
281
// synthesis attribute INIT_06  of ram_1024_x_18 is "{INIT_06}"
282
// synthesis attribute INIT_07  of ram_1024_x_18 is "{INIT_07}"
283
// synthesis attribute INIT_08  of ram_1024_x_18 is "{INIT_08}"
284
// synthesis attribute INIT_09  of ram_1024_x_18 is "{INIT_09}"
285
// synthesis attribute INIT_0A  of ram_1024_x_18 is "{INIT_0A}"
286
// synthesis attribute INIT_0B  of ram_1024_x_18 is "{INIT_0B}"
287
// synthesis attribute INIT_0C  of ram_1024_x_18 is "{INIT_0C}"
288
// synthesis attribute INIT_0D  of ram_1024_x_18 is "{INIT_0D}"
289
// synthesis attribute INIT_0E  of ram_1024_x_18 is "{INIT_0E}"
290
// synthesis attribute INIT_0F  of ram_1024_x_18 is "{INIT_0F}"
291
// synthesis attribute INIT_10  of ram_1024_x_18 is "{INIT_10}"
292
// synthesis attribute INIT_11  of ram_1024_x_18 is "{INIT_11}"
293
// synthesis attribute INIT_12  of ram_1024_x_18 is "{INIT_12}"
294
// synthesis attribute INIT_13  of ram_1024_x_18 is "{INIT_13}"
295
// synthesis attribute INIT_14  of ram_1024_x_18 is "{INIT_14}"
296
// synthesis attribute INIT_15  of ram_1024_x_18 is "{INIT_15}"
297
// synthesis attribute INIT_16  of ram_1024_x_18 is "{INIT_16}"
298
// synthesis attribute INIT_17  of ram_1024_x_18 is "{INIT_17}"
299
// synthesis attribute INIT_18  of ram_1024_x_18 is "{INIT_18}"
300
// synthesis attribute INIT_19  of ram_1024_x_18 is "{INIT_19}"
301
// synthesis attribute INIT_1A  of ram_1024_x_18 is "{INIT_1A}"
302
// synthesis attribute INIT_1B  of ram_1024_x_18 is "{INIT_1B}"
303
// synthesis attribute INIT_1C  of ram_1024_x_18 is "{INIT_1C}"
304
// synthesis attribute INIT_1D  of ram_1024_x_18 is "{INIT_1D}"
305
// synthesis attribute INIT_1E  of ram_1024_x_18 is "{INIT_1E}"
306
// synthesis attribute INIT_1F  of ram_1024_x_18 is "{INIT_1F}"
307
// synthesis attribute INIT_20  of ram_1024_x_18 is "{INIT_20}"
308
// synthesis attribute INIT_21  of ram_1024_x_18 is "{INIT_21}"
309
// synthesis attribute INIT_22  of ram_1024_x_18 is "{INIT_22}"
310
// synthesis attribute INIT_23  of ram_1024_x_18 is "{INIT_23}"
311
// synthesis attribute INIT_24  of ram_1024_x_18 is "{INIT_24}"
312
// synthesis attribute INIT_25  of ram_1024_x_18 is "{INIT_25}"
313
// synthesis attribute INIT_26  of ram_1024_x_18 is "{INIT_26}"
314
// synthesis attribute INIT_27  of ram_1024_x_18 is "{INIT_27}"
315
// synthesis attribute INIT_28  of ram_1024_x_18 is "{INIT_28}"
316
// synthesis attribute INIT_29  of ram_1024_x_18 is "{INIT_29}"
317
// synthesis attribute INIT_2A  of ram_1024_x_18 is "{INIT_2A}"
318
// synthesis attribute INIT_2B  of ram_1024_x_18 is "{INIT_2B}"
319
// synthesis attribute INIT_2C  of ram_1024_x_18 is "{INIT_2C}"
320
// synthesis attribute INIT_2D  of ram_1024_x_18 is "{INIT_2D}"
321
// synthesis attribute INIT_2E  of ram_1024_x_18 is "{INIT_2E}"
322
// synthesis attribute INIT_2F  of ram_1024_x_18 is "{INIT_2F}"
323
// synthesis attribute INIT_30  of ram_1024_x_18 is "{INIT_30}"
324
// synthesis attribute INIT_31  of ram_1024_x_18 is "{INIT_31}"
325
// synthesis attribute INIT_32  of ram_1024_x_18 is "{INIT_32}"
326
// synthesis attribute INIT_33  of ram_1024_x_18 is "{INIT_33}"
327
// synthesis attribute INIT_34  of ram_1024_x_18 is "{INIT_34}"
328
// synthesis attribute INIT_35  of ram_1024_x_18 is "{INIT_35}"
329
// synthesis attribute INIT_36  of ram_1024_x_18 is "{INIT_36}"
330
// synthesis attribute INIT_37  of ram_1024_x_18 is "{INIT_37}"
331
// synthesis attribute INIT_38  of ram_1024_x_18 is "{INIT_38}"
332
// synthesis attribute INIT_39  of ram_1024_x_18 is "{INIT_39}"
333
// synthesis attribute INIT_3A  of ram_1024_x_18 is "{INIT_3A}"
334
// synthesis attribute INIT_3B  of ram_1024_x_18 is "{INIT_3B}"
335
// synthesis attribute INIT_3C  of ram_1024_x_18 is "{INIT_3C}"
336
// synthesis attribute INIT_3D  of ram_1024_x_18 is "{INIT_3D}"
337
// synthesis attribute INIT_3E  of ram_1024_x_18 is "{INIT_3E}"
338
// synthesis attribute INIT_3F  of ram_1024_x_18 is "{INIT_3F}"
339
// synthesis attribute INITP_00 of ram_1024_x_18 is "{INITP_00}"
340
// synthesis attribute INITP_01 of ram_1024_x_18 is "{INITP_01}"
341
// synthesis attribute INITP_02 of ram_1024_x_18 is "{INITP_02}"
342
// synthesis attribute INITP_03 of ram_1024_x_18 is "{INITP_03}"
343
// synthesis attribute INITP_04 of ram_1024_x_18 is "{INITP_04}"
344
// synthesis attribute INITP_05 of ram_1024_x_18 is "{INITP_05}"
345
// synthesis attribute INITP_06 of ram_1024_x_18 is "{INITP_06}"
346
// synthesis attribute INITP_07 of ram_1024_x_18 is "{INITP_07}"
347
 
348
endmodule
349
 
350
// END OF FILE {name}.v

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