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Line No.	Rev	Author	Line
1	2	ameziti	`;--------------------------------------------------------------------------------`
2			`;-- Company:`
3			`;--`
4			`;-- File: Test_Mnemonics.asm`
5			`;--`
6			`;-- Description:`
7			`;-- projet bicoblaze`
8			`;-- Test of the mnemonics of the BicoBlaze3 processor`
9			`;--`
10			`;-- File history:`
11			`;-- v1.0: 11/10/11: Creation`
12			`;--`
13			`;-- Targeted device: ProAsic A3P250 VQFP100`
14			`;-- Author: AbdAllah Meziti`
15			`;--------------------------------------------------------------------------------`
16
17			`LOAD s0, 0x85 ; s0=85`
18			`LOAD s3, 0x42 ; s3=42`
19			`LOAD s7, s3 ; s7=42`
20			`AND s3, 0x23 ; s3=02`
21			`AND s7, s0 ; s7=00`
22			`OR s3, 0x69 ; s3=6B`
23			`OR s7, s0 ; s7=85`
24			`XOR s0, 0x42 ; s0=C7`
25			`XOR s0, s7 ; s0=42`
26
27			`ADD s0, 0x43 ; s0=85`
28			`ADD s0, s7 ; s0=0A (Carry=1)`
29			`ADDC s0, 0x42 ; s0=4D`
30			`ADDC s0, s7 ; s0=D2`
31			`SUB s0, 0xE5 ; s0=ED (Borrow=1)`
32			`SUB s0, s7 ; s0=68`
33			`SUBC s0, 0xA7 ; s0=C1 (Borrow=1)`
34			`SUBC s0, s7 ; s0=3B`
35
36			`LOAD s0, 0x43 ; s0=43`
37			`SL0 s0 ; s0=86`
38			`SLX s0 ; s0=0C (Carry=1)`
39			`SLA s0 ; s0=19`
40			`SL1 s0 ; s0=33`
41			`LOAD s0, 0xB0 ; s0=B0`
42			`RL s0 ; s0=61 (Carry=1)`
43
44			`SRA s0 ; s0=B0 (Carry=1)`
45			`SR0 s0 ; s0=58`
46			`SR1 s0 ; s0=AC`
47			`SRX s0 ; s0=D6`
48			`LOAD s0, 0xCD ; s0=CD`
49			`RR s0 ; s0=E6`
50
51			`OUT s0, 0x30 ; OUT_PORT=s0=E6, PORT_ID=30`
52			`OUT s0, s7 ; OUT_PORT=s0=E6, PORT_ID=s7=85`
53			`IN s0, 0x20 ; s0=OUT_PORT=(see external value), PORT_ID=20`
54			`IN s0, s7 ; s0=OUT_PORT=(see external value), PORT_ID=s7=85`
55
56			`; one line macro for extra instructions`
57			`INST 0x1234`
58
59			`LOAD s0, 0xB8 ; s0=B8`
60			`COMP s0, 0x42 ; C=0, Z=0`
61			`COMP s0, 0xB8 ; C=0, Z=1`
62			`COMP s0, 0xC9 ; C=1, Z=0`
63
64			`LOAD s1, 0x44 ; s1=44`
65			`LOAD s2, 0xB8 ; s2=B8`
66			`LOAD s3, 0xD9 ; s3=D9`
67			`COMP s0, s1 ; C=0, Z=0`
68			`COMP s0, s2 ; C=0, Z=1`
69			`COMP s0, s3 ; C=1, Z=0`
70
71			`LOAD s5, 0x3D ; s5=3D`
72			`TEST s5, 0xFF ; C=1`
73			`TEST s0, s1 ; (s0 and s1)`
74
75			`LOAD s1, 0x03 ; s1=03`
76			`STORE s0, 0x0A ; Scratch(@0A)=s0=E6`
77			`STORE s0, s1 ; Scratch(@s1=03)=s0=E6`
78			`FETCH s4, 0x0A ; s4=Scratch(@0A)=E6`
79			`FETCH s5, s1 ; s5=Scratch(@s1=03)=E6`
80
81
82			`JUMP JmpL1 ; Validation`
83			`INST 0xFFFF`
84			`INST 0xFFFF`
85			`INST 0xFFFF`
86			`INST 0xFFFF`
87
88			`JmpL1:`
89			`LOAD s0, 0x03 ; s0=03`
90			`LoopL1:`
91			`SUB s0, 0x01 ; s0=s0-1`
92			`JUMP NZ, LoopL1 ; -- Validation`
93
94			`JUMP Z, JmpL2 ; -- Validation`
95			`INST 0xFFFF`
96			`INST 0xFFFF`
97			`INST 0xFFFF`
98			`INST 0xFFFF`
99
100			`JmpL2:`
101			`LOAD s0, 0x03 ; s0=03`
102			`LoopL2:`
103			`SUB s0, 0x01 ; s0=s0-1`
104			`JUMP NC, LoopL2 ; -- Validation`
105
106			`JUMP C, CalL1 ; -- Validation`
107			`INST 0xFFFF`
108			`INST 0xFFFF`
109			`INST 0xFFFF`
110			`INST 0xFFFF`
111
112			`CalL1:`
113			`LOAD s0, 0x03 ; s0=03`
114			`CALL Function ; -- Validation`
115			`LOAD s1, 0x03 ; s1=03`
116			`LOAD s2, 0x03 ; s2=03`
117			`LOAD s3, 0x03 ; s3=03`
118			`LOAD s4, 0x03 ; s4=03`
119
120			`; CALL NZ, Function ; -- Validation`
121			`; CALL Z, Function`
122			`; CALL NC, Function`
123			`CALL C, Function`
124
125			`load s0, 0xBB`
126			`call FuncLoadAllRegister`
127
128			`EINT ; ENABLE INTERRUPT`
129			`; DINT ; DISABLE INTERRUPT`
130
131			`; clear all register`
132			`load s0, 0x00`
133			`call FuncLoadAllRegister`
134
135			`; End LOOP`
136			`EndLoop:`
137			`; JUMP EndLoop ; -- Validation`
138
139			`ADD s0, 0x01 ; s0++`
140			`ADD s1, 0x01 ; s1++`
141			`ADD s2, 0x01 ; s2++`
142			`ADD s3, 0x01 ; s3++`
143			`ADD s4, 0x01 ; s4++`
144			`ADD s5, 0x01 ; s5++`
145			`ADD s6, 0x01 ; s6++`
146			`ADD s7, 0x01 ; s7++`
147			`ADD s8, 0x01 ; s8++`
148			`ADD s9, 0x01 ; s9++`
149			`ADD sA, 0x01 ; sA++`
150			`ADD sB, 0x01 ; sB++`
151			`ADD sC, 0x01 ; sC++`
152			`ADD sD, 0x01 ; sD++`
153			`ADD sE, 0x01 ; sE++`
154			`ADD sF, 0x01 ; sF++`
155
156			`JUMP EndLoop ; -- Validation`
157
158			`; =====================================================================`
159			`; END OF PROGRAM`
160			`; =====================================================================`
161
162			`; ****************************************`
163			`; Function`
164			`; ****************************************`
165			`Function:`
166			`LOAD s1, 0x55 ; s1=55`
167			`LOAD s2, 0x55 ; s2=55`
168			`LOAD s3, 0x55 ; s3=55`
169			`LOAD s4, 0x55 ; s4=55`
170
171			`RET ; -- Validation`
172
173			`; RET NZ ; -- Validation`
174			`; RET Z ; -- Validation`
175
176			`; RET NC ; -- Validation`
177			`; RET C ; -- Validation`
178
179
180			`; ****************************************`
181			`; Load All the register with the s0 value.`
182			`; ****************************************`
183			`FuncLoadAllRegister:`
184			`; LOAD s0, s0 ; s0=s0`
185			`LOAD s1, s0 ; s1=s0`
186			`LOAD s2, s0 ; s2=s0`
187			`LOAD s3, s0 ; s3=s0`
188			`LOAD s4, s0 ; s4=s0`
189			`LOAD s5, s0 ; s5=s0`
190			`LOAD s6, s0 ; s6=s0`
191			`LOAD s7, s0 ; s7=s0`
192			`LOAD s8, s0 ; s8=s0`
193			`LOAD s9, s0 ; s9=s0`
194			`LOAD sA, s0 ; sA=s0`
195			`LOAD sB, s0 ; sB=s0`
196			`LOAD sC, s0 ; sC=s0`
197			`LOAD sD, s0 ; sD=s0`
198			`LOAD sE, s0 ; sE=s0`
199			`LOAD sF, s0 ; sF=s0`
200			`ret`
201			`; ****************************************`
202			`; Decrement All the register by 1.`
203			`; ****************************************`
204			`FuncDecreAllRegister:`
205			`SUB s0, 0x02 ; s0--`
206			`SUB s1, 0x02 ; s1--`
207			`SUB s2, 0x02 ; s2--`
208			`SUB s3, 0x02 ; s3--`
209			`SUB s4, 0x02 ; s4--`
210			`SUB s5, 0x02 ; s5--`
211			`SUB s6, 0x02 ; s6--`
212			`SUB s7, 0x02 ; s7--`
213			`SUB s8, 0x02 ; s8--`
214			`SUB s9, 0x02 ; s9--`
215			`SUB sA, 0x02 ; sA--`
216			`SUB sB, 0x02 ; sB--`
217			`SUB sC, 0x02 ; sC--`
218			`SUB sD, 0x02 ; sD--`
219			`SUB sE, 0x02 ; sE--`
220			`SUB sF, 0x02 ; sF--`
221			`ret`
222
223			`; *************************`
224			`; Interrupt Service Routine`
225			`; *************************`
226			`ISR:`
227			`; load s0, 0xAA`
228			`call FuncDecreAllRegister ; ISR`
229
230			`; RETI ENABLE ; RETURNI`
231			`RETI DISABLE`
232			`; *************************`
233			`; End ISR Interrupt Handler`
234			`; *************************`
235
236			`.ORG 0x3FF`
237			`VECTOR:`
238			`JUMP ISR`

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[/] [copyblaze/] [trunk/] [copyblaze/] [sw/] [code/] [pBlaze/] [Mnemonics/] [Test_Mnemonics.asm] - Blame information for rev 58