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[/] [core1990_interlaken/] [trunk/] [gateware/] [simulation/] [decoder_tb.vhd] - Blame information for rev 9

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Line No. Rev Author Line
1 6 N.Boukadid 
library ieee;
2 
use ieee.std_logic_1164.all;
3 
 
4 
entity testbench_decoder is
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end entity testbench_decoder;
6 
 
7 
architecture tb_decoder of testbench_decoder is
8 
 
9 9 N.Boukadid 
    signal Clk             : std_logic;                      -- Clock input
10 
    signal Reset                   : std_logic;                                      -- Reset decoder
11 6 N.Boukadid 
    signal Data_In         :  std_logic_vector(66 downto 0); -- Data input
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    signal Decoder_En      :  std_logic;                     -- Enables the decoder
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    signal Data_Valid_In   :  std_logic;
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    signal Data_Valid_Out  :  std_logic;
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    signal Data_Out        :  std_logic_vector(63 downto 0);-- Decoded 64-bit output
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    signal Data_Control    :  std_logic;                    --  Indicates whether the word is data or control
17 
 
18 
    signal Sync_Locked  :  std_logic;
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    signal Sync_Error   :  std_logic;
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    signal Bitslip      :  std_logic;
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22 
    constant CLK_PERIOD : time := 10 ns;
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24 
begin
25 9 N.Boukadid 
    uut : entity work.decoder
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    port map (
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        clk => clk,
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        reset => reset,
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        Decoder_En => Decoder_En,
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        Data_in => Data_in,
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        Data_out => Data_out,
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        Data_Valid_In => Data_Valid_In,
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        Data_Valid_Out => Data_Valid_Out,
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        Data_control => Data_control,
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        Sync_Locked => Sync_locked,
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        Sync_error => Sync_error,
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        Bitslip => Bitslip
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    );
41 6 N.Boukadid 
 
42 9 N.Boukadid 
    Clk_process :process
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    begin
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        clk <= '1';
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        wait for CLK_PERIOD/2;  --for half of clock period clk stays at '0'.
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        clk <= '0';
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        wait for CLK_PERIOD/2;  --for next half of clock period clk stays at '1'.
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    end process;
49 6 N.Boukadid 
 
50 
    simulation : process
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    begin
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        wait for 1 ps;
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        decoder_en <= '1';
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        reset <= '1';
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        data_in <= (others=>'0');
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        wait for CLK_PERIOD;
58 
 
59 
        wait for CLK_PERIOD;
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61 
        reset <= '0';
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        Data_in <= "101" & X"1f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
64 
 
65 
 
66 
        Data_in <= "101" & X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
68 
 
69 
 
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        data_in <= "101" & X"3f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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73 
 
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        Data_in <= "101" & X"4f21a2a3a4a5a6a7";
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        wait for CLK_PERIOD;
76 
 
77 
 
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        data_in <= "101" & X"5f5e5a5c5b60f2a0";
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        wait for CLK_PERIOD;
80 
 
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        data_in  <= "001" & X"635e22a3a4a5a7a7";
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        wait for CLK_PERIOD;
83 
 
84 
        data_in  <= "101" & X"70000FFF000000F0";
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        wait for CLK_PERIOD*2;
86 
 
87 
 
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        Data_in <= "101" & X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
90 
 
91 
        wait for CLK_PERIOD;
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93 
 
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        data_in  <= "110" & X"8050505050050505";
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        wait for CLK_PERIOD*3;
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        data_in  <= "101" & X"9486576758050505";
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        wait for CLK_PERIOD;
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100 
 
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        data_in <= "101" & X"60b35d5dc4a582a7";
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        wait for CLK_PERIOD;
103 
 
104 
 
105 
        data_in <= "101" & X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD*12;
107 
 
108 
        data_in <= "111" & X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
110 
 
111 
        Data_in <= "101" & X"1f5e5d5c5b5a5958";
112 
        wait for CLK_PERIOD;
113 
 
114 
 
115 
        Data_in <= "101" & X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
117 
 
118 
 
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        data_in <= "101" & X"3f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
121 
 
122 
 
123 
        Data_in <= "101" & X"4f21a2a3a4a5a6a7";
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        wait for CLK_PERIOD;
125 
 
126 
 
127 
        data_in <= "101" & X"5f5e5a5c5b60f2a0";
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        wait for CLK_PERIOD;
129 
 
130 
        data_in  <= "001" & X"635e22a3a4a5a7a7";
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        wait for CLK_PERIOD;
132 
 
133 
        data_in <= "101" & X"5f5e5a5c5b60f2a0";
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        wait for CLK_PERIOD;
135 
 
136 
        data_in  <= "001" & X"635e22a3a4a5a7a7";
137 
        wait for CLK_PERIOD;
138 
 
139 
        data_in  <= "101" & X"70000FFF000000F0";
140 
        wait for CLK_PERIOD*2;
141 
 
142 
 
143 
        Data_in <= "101" & X"2f5e5d5c5b5a5958";
144 
        wait for CLK_PERIOD;
145 
 
146 
        data_in  <= "110" & X"8050505050050505";
147 
        wait for CLK_PERIOD*3;
148 
 
149 
        data_in  <= "101" & X"9486576758050505";
150 
        wait for CLK_PERIOD;
151 
 
152 
        data_in <= "101" & X"60b35d5dc4a582a7";
153 
        wait for CLK_PERIOD*60;
154 
 
155 
        data_in  <= "110" & X"8050505050050505";
156 
        wait for CLK_PERIOD*3;
157 
 
158 
        data_in  <= "101" & X"9486576758050505";
159 
        wait for CLK_PERIOD;
160 
 
161 
 
162 
        data_in <= "101" & X"60b35d5dc4a582a7";
163 
        wait for CLK_PERIOD;
164 
 
165 
 
166 
        data_in <= "101" & X"2f5e5d5c5b5a5958";
167 
        wait for CLK_PERIOD*12;
168 
 
169 
        data_in <= "111" & X"2c8e5d5c5b5a5958";
170 
        wait for CLK_PERIOD;
171 
 
172 
        Data_in <= "101" & X"1f5e5d5c5b5a5958";
173 
        wait for CLK_PERIOD*26;
174 
 
175 
        data_in <= "111" & X"2c8e5d5c5b5a5958";
176 
        wait for CLK_PERIOD*18;
177 
 
178 
        data_in <= "101" & X"1f5e5d5c5b5a5958";
179 
        wait for CLK_PERIOD;
180 
        wait;
181 
    end process;
182 
 
183 
end architecture tb_decoder;
184 
 

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