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[/] [core1990_interlaken/] [trunk/] [gateware/] [simulation/] [decoder_tb.vhd] - Blame information for rev 8

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Line No. Rev Author Line
1 6 N.Boukadid 
library ieee;
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use ieee.std_logic_1164.all;
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4 
entity testbench_decoder is
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end entity testbench_decoder;
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architecture tb_decoder of testbench_decoder is
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    signal Clk             : std_logic;                     -- Clock input
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    signal Reset                    : std_logic;                                         -- Reset decoder
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    signal Data_In         :  std_logic_vector(66 downto 0); -- Data input
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    signal Decoder_En      :  std_logic;                     -- Enables the decoder
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    signal Data_Valid_In   :  std_logic;
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    signal Data_Valid_Out  :  std_logic;
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    signal Data_Out        :  std_logic_vector(63 downto 0);-- Decoded 64-bit output
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    signal Data_Control    :  std_logic;                    --  Indicates whether the word is data or control
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    signal Sync_Locked  :  std_logic;
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    signal Sync_Error   :  std_logic;
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    signal Bitslip      :  std_logic;
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    constant CLK_PERIOD : time := 10 ns;
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begin
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  uut : entity work.decoder
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  port map (
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    clk => clk,
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    reset => reset,
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    Decoder_En => Decoder_En,
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    Data_in => Data_in,
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    Data_out => Data_out,
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    Data_Valid_In => Data_Valid_In,
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    Data_Valid_Out => Data_Valid_Out,
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    Data_control => Data_control,
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    Sync_Locked => Sync_locked,
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    Sync_error => Sync_error,
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    Bitslip => Bitslip
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  );
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   Clk_process :process
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     begin
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          clk <= '1';
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          wait for CLK_PERIOD/2;  --for half of clock period clk stays at '0'.
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          clk <= '0';
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          wait for CLK_PERIOD/2;  --for next half of clock period clk stays at '1'.
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     end process;
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    simulation : process
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    begin
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        wait for 1 ps;
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        decoder_en <= '1';
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        reset <= '1';
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        data_in <= (others=>'0');
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        wait for CLK_PERIOD;
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        wait for CLK_PERIOD;
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        reset <= '0';
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        Data_in <= "101" & X"1f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        Data_in <= "101" & X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        data_in <= "101" & X"3f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        Data_in <= "101" & X"4f21a2a3a4a5a6a7";
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        wait for CLK_PERIOD;
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        data_in <= "101" & X"5f5e5a5c5b60f2a0";
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        wait for CLK_PERIOD;
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        data_in  <= "001" & X"635e22a3a4a5a7a7";
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        wait for CLK_PERIOD;
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        data_in  <= "101" & X"70000FFF000000F0";
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        wait for CLK_PERIOD*2;
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        Data_in <= "101" & X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        wait for CLK_PERIOD;
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        data_in  <= "110" & X"8050505050050505";
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        wait for CLK_PERIOD*3;
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        data_in  <= "101" & X"9486576758050505";
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        wait for CLK_PERIOD;
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        data_in <= "101" & X"60b35d5dc4a582a7";
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        wait for CLK_PERIOD;
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        data_in <= "101" & X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD*12;
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        data_in <= "111" & X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        Data_in <= "101" & X"1f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        Data_in <= "101" & X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        data_in <= "101" & X"3f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        Data_in <= "101" & X"4f21a2a3a4a5a6a7";
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        wait for CLK_PERIOD;
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        data_in <= "101" & X"5f5e5a5c5b60f2a0";
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        wait for CLK_PERIOD;
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        data_in  <= "001" & X"635e22a3a4a5a7a7";
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        wait for CLK_PERIOD;
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        data_in <= "101" & X"5f5e5a5c5b60f2a0";
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        wait for CLK_PERIOD;
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        data_in  <= "001" & X"635e22a3a4a5a7a7";
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        wait for CLK_PERIOD;
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        data_in  <= "101" & X"70000FFF000000F0";
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        wait for CLK_PERIOD*2;
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        Data_in <= "101" & X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        data_in  <= "110" & X"8050505050050505";
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        wait for CLK_PERIOD*3;
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        data_in  <= "101" & X"9486576758050505";
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        wait for CLK_PERIOD;
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        data_in <= "101" & X"60b35d5dc4a582a7";
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        wait for CLK_PERIOD*60;
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        data_in  <= "110" & X"8050505050050505";
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        wait for CLK_PERIOD*3;
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        data_in  <= "101" & X"9486576758050505";
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        wait for CLK_PERIOD;
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        data_in <= "101" & X"60b35d5dc4a582a7";
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        wait for CLK_PERIOD;
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        data_in <= "101" & X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD*12;
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        data_in <= "111" & X"2c8e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        Data_in <= "101" & X"1f5e5d5c5b5a5958";
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        wait for CLK_PERIOD*26;
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        data_in <= "111" & X"2c8e5d5c5b5a5958";
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        wait for CLK_PERIOD*18;
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        data_in <= "101" & X"1f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        wait;
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    end process;
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end architecture tb_decoder;
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