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[/] [core1990_interlaken/] [trunk/] [gateware/] [simulation/] [framing_burst_tb.vhd] - Blame information for rev 7

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1 6 N.Boukadid 
library ieee;
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use ieee.std_logic_1164.all;
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entity testbench_burst is
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end entity testbench_burst;
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architecture tb_burst of testbench_burst is
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  --for uut : CRC use entity work.CRC(error_check);
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    constant BurstMax   : positive := 64; --256
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    constant BurstShort : positive := 32;  --512 - 256 - 128 - 64 - 32
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        signal clk                              : std_logic;                                -- System clock
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        signal reset                    : std_logic;                                -- Reset, use for initialization.
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        signal TX_Enable : std_logic := '0';                           -- Enable the TX
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        signal TX_SOP : std_logic := '0';                              -- Start of Packet
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        signal TX_ValidBytes : std_logic_vector(2 downto 0) := "000";    -- Valid bytes packet contains
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        signal TX_EOP : std_logic := '0';                              -- End of Packet
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        signal TX_FlowControl : std_logic_vector(15 downto 0) := (others => '0');  -- Flow control data (yet unutilized)
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        signal TX_Channel    : std_logic_vector(7 downto 0);
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        signal Data_in : std_logic_vector(63 downto 0);         -- Input data
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        signal Data_out : std_logic_vector(63 downto 0);       -- To scrambling/framing
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        signal Data_valid_out : std_logic;                                              -- Indicate data transmitted is valid
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        signal Data_control_out : std_logic;                   -- Control word indication
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        --signal CRC24_TX : std_logic_vector(63 downto 0);        -- Data to CRC-24
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        --signal CRC24_Cal : std_logic_vector(63 downto 0);             -- Calculated CRC-24
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        --signal CRC24_En : std_logic;                                                  -- Indicate the CRC-24 the data is valid
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    signal FIFO_meta : std_logic;
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        signal FIFO_read : std_logic;                                           -- Request data from the FIFO
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        signal FIFO_data : std_logic_vector(9 downto 0);         -- Determines how many bytes have to be transmitted
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 constant CLK_PERIOD : time := 10 ns;
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begin
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  uut : entity work.burst
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  generic map(
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    BurstShort => BurstShort,
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    BurstMax => BurstMax
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  )
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  port map (
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    clk => clk,
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    reset => reset,
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    TX_Enable => TX_Enable,
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    TX_SOP => TX_SOP,
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    TX_ValidBytes => TX_ValidBytes,
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    TX_EOP => TX_EOP,
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    TX_FlowControl => TX_FlowControl,
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    TX_Channel => TX_Channel,
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    Data_in => Data_in,
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    Data_out => Data_out,
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    Data_valid_out => Data_valid_out,
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    Data_control_out => Data_control_out,
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    --CRC24_TX => CRC24_TX,
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    --CRC24_Cal => CRC24_Cal,
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    --CRC24_En => CRC24_En,
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    FIFO_read => FIFO_read,
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    FIFO_meta => FIFO_meta,
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    FIFO_data => FIFO_data
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  );
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   Clk_process :process
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     begin
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          clk <= '1';
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          wait for CLK_PERIOD/2;  --for half of clock period clk stays at '0'.
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          clk <= '0';
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          wait for CLK_PERIOD/2;  --for next half of clock period clk stays at '1'.
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     end process;
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    simulation : process
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    begin
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       wait for 1 ps;
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       TX_SOP <= '0';
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       reset <= '1';
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       data_in <= (others=>'0');
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       wait for CLK_PERIOD;
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       wait for CLK_PERIOD;
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       FIFO_meta <= '1';
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       reset <= '0';
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       TX_Enable <= '1';
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       TX_ValidBytes <= "111";
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       Data_in <= X"1f5e5d5c5b5a5958";
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       wait for CLK_PERIOD;
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       TX_SOP <= '1';
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       TX_EOP <= '1';
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       Data_in <= X"2f5e5d5c5b5a5958";
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       wait for CLK_PERIOD;
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       TX_SOP <= '1';
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       TX_EOP <= '0';
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       data_in <= X"3f5e5d5c5b5a5958";
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       wait for CLK_PERIOD;
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       TX_EOP <= '0';
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       --reset <= '1';
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       Data_in <= X"4f21a2a3a4a5a6a7";
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       wait for CLK_PERIOD;
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       --reset <= '0';
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       data_in <= X"5f5e5a5c5b60f2a0";
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       wait for CLK_PERIOD;
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       --TX_EOP <= '1';
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       data_in  <= X"635e22a3a4a5a7a7";
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       wait for CLK_PERIOD;
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       --TX_EOP <= '0';
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       --TX_SOP <= '1';
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       data_in  <= X"70000FFF000000F0";
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       wait for CLK_PERIOD*2;
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       TX_SOP <= '1';
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       Data_in <= X"2f5e5d5c5b5a5958";
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       wait for CLK_PERIOD;
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       TX_SOP <= '0';
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       TX_EOP <= '1';
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       wait for CLK_PERIOD;
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       TX_EOP <= '0';
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       --TX_SOP <= '0';
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       data_in  <= X"8050505050050505";
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       wait for CLK_PERIOD*3;
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       data_in  <= X"9486576758050505";
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       wait for CLK_PERIOD;
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       TX_EOP <= '1';
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       data_in <= X"60b35d5dc4a582a7";
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       wait for CLK_PERIOD;
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       TX_EOP <= '0';
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       TX_SOP <= '1';
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       data_in <= X"2f5e5d5c5b5a5958";
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       wait for CLK_PERIOD*6;
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       FIFO_meta<= '0';
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       wait for CLK_PERIOD;
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       FIFO_meta<= '1';
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       wait for CLK_PERIOD*6;
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       TX_SOP <= '0';
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       TX_EOP <= '1';
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       wait for CLK_PERIOD;
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       FIFO_meta <= '0';
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       wait for CLK_PERIOD*4;
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       FIFO_meta <= '1';
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       wait;
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    end process;
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end architecture tb_burst;
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