| 1 |
6 |
N.Boukadid |
library ieee;
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| 2 |
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use ieee.std_logic_1164.all;
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| 3 |
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| 4 |
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entity testbench_interlaken_receiver is
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| 5 |
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end entity testbench_interlaken_receiver;
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| 6 |
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| 7 |
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architecture tb_interlaken_receiver of testbench_interlaken_receiver is
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| 8 |
9 |
N.Boukadid |
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| 9 |
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signal fifo_read_clk : std_logic;
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| 10 |
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signal clk : std_logic;
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| 11 |
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signal reset : std_logic;
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| 12 |
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| 13 |
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signal RX_Data_In : std_logic_vector(66 downto 0);
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signal RX_Data_Out : std_logic_vector (63 downto 0); -- Data ready to transmit
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| 15 |
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| 16 |
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signal RX_Valid_Out : std_logic;
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| 17 |
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| 18 |
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signal RX_SOP : std_logic; -- Start of Packet
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| 19 |
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signal RX_EOP_Valid : std_logic_vector(2 downto 0); -- Valid bytes packet contains
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signal RX_EOP : std_logic; -- End of Packet
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signal RX_FlowControl : std_logic_vector(15 downto 0); -- Flow control data (yet unutilized)
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| 22 |
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signal RX_prog_full : std_logic_vector(15 downto 0); -- Indication FIFO of this channel is full
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| 23 |
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signal RX_Channel : std_logic_vector(7 downto 0); -- Select transmit channel (yet unutilized)
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signal RX_Datavalid : std_logic;
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signal CRC24_Error : std_logic;
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signal CRC32_Error : std_logic;
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signal Decoder_lock : std_logic;
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| 29 |
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signal Descrambler_lock : std_logic;
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| 30 |
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| 31 |
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signal Data_Descrambler : std_logic_vector(63 downto 0);
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signal Data_Decoder : std_logic_vector(63 downto 0);
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| 33 |
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signal RX_FIFO_Full : std_logic;
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signal RX_FIFO_Read : std_logic;
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signal RX_Link_Up : std_logic;
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signal Bitslip : std_logic;
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6 |
N.Boukadid |
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| 40 |
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constant CLK_PERIOD : time := 10 ns;
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begin
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9 |
N.Boukadid |
uut : entity work.interlaken_receiver
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port map (
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write_clk => write_clk,
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clk => clk,
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reset => reset,
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RX_Data_In => RX_Data_In,
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RX_Data_Out => RX_Data_Out,
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RX_Enable => RX_Enable,
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RX_SOP => RX_SOP,
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RX_ValidBytes => RX_ValidBytes,
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RX_EOP => RX_EOP,
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RX_FlowControl => RX_FlowControl,
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RX_Channel => RX_Channel,
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RX_Link_Up => RX_Link_Up
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);
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6 |
N.Boukadid |
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9 |
N.Boukadid |
Clk_process :process
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begin
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write_clk <= '1';
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clk <= '1';
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wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
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clk <= '0';
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write_clk <= '0';
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wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
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end process;
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6 |
N.Boukadid |
simulation : process
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begin
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wait for 1 ps;
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RX_Data_In <= (others=>'0');
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reset <= '1';
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9 |
N.Boukadid |
wait for CLK_PERIOD*2;
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6 |
N.Boukadid |
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reset <= '0';
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reset <= '0';
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RX_Data_in <= "101" & X"1f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"3f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"4f21a2a3a4a5a6a7";
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"5f5e5a5c5b60f2a0";
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"70000FFF000000F0";
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wait for CLK_PERIOD*2;
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RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
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9 |
N.Boukadid |
wait for CLK_PERIOD*2;
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6 |
N.Boukadid |
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RX_Data_In <= "110" & X"8050505050050505";
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wait for CLK_PERIOD*3;
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RX_Data_In <= "101" & X"9486576758050505";
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"60b35d5dc4a582a7";
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD*12;
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RX_Data_In <= "111" & X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"1f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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| 122 |
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RX_Data_In <= "001" & X"5f5e5a5c5b60f2a0";
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"70000FFF000000F0";
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wait for CLK_PERIOD*21;
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RX_Data_In <= "001" & X"78f6_78f6_78f6_78f6"; --Sync &
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
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wait for CLK_PERIOD;
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| 136 |
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RX_Data_In <= "101" & X"3f5e5d5c5b5a5958";
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| 138 |
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wait for CLK_PERIOD;
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| 139 |
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| 140 |
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RX_Data_In <= "101" & X"4f21a2a3a4a5a6a7";
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| 141 |
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wait for CLK_PERIOD;
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| 142 |
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RX_Data_In <= "101" & X"5f5e5a5c5b60f2a0";
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| 144 |
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
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wait for CLK_PERIOD;
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| 149 |
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RX_Data_In <= "101" & X"70000FFF000000F0";
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wait for CLK_PERIOD*2;
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RX_Data_In <= "001" & X"2Bfe_d100_19e0_1dbd";
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"70000FFF000000F0";
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wait for CLK_PERIOD*2;
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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| 159 |
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"3f5e5d5c5b5a5958";
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wait for CLK_PERIOD*10;
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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| 166 |
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wait for CLK_PERIOD;
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RX_Data_In <= "001" & X"8050505050050505";
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| 169 |
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wait for CLK_PERIOD*3;
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| 171 |
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RX_Data_In <= "001" & X"9486576758050505";
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| 172 |
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wait for CLK_PERIOD;
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RX_Data_In <= "101" & X"4f21a2a3a4a5a6a7";
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wait for CLK_PERIOD*20;
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RX_Data_In <= "101" & X"5f5e5a5c5b60f2a0";
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| 179 |
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wait for CLK_PERIOD*10;
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| 180 |
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| 181 |
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RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
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| 182 |
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wait for CLK_PERIOD;
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| 183 |
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RX_Data_In <= "101" & X"5f5e5a5c5b60f2a0";
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| 185 |
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wait for CLK_PERIOD;
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| 186 |
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| 187 |
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RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
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| 188 |
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wait for CLK_PERIOD;
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| 189 |
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| 190 |
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RX_Data_In <= "101" & X"70000FFF000000F0";
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| 191 |
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wait for CLK_PERIOD*6;
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| 192 |
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| 193 |
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RX_Data_In <= "001" & X"8050505050050505";
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| 194 |
9 |
N.Boukadid |
wait for CLK_PERIOD*9;
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| 195 |
6 |
N.Boukadid |
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| 196 |
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RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
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| 197 |
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wait for CLK_PERIOD;
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| 198 |
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| 199 |
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RX_Data_In <= "110" & X"8050505050050505";
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| 200 |
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wait for CLK_PERIOD*3;
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| 201 |
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RX_Data_In <= "101" & X"9486576758050505";
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| 203 |
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wait for CLK_PERIOD;
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| 204 |
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| 205 |
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RX_Data_In <= "001" & X"1f5e5d5c5b5a5958";
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| 206 |
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wait for CLK_PERIOD;
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| 208 |
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RX_Data_In <= "010" & X"78f6_78f6_78f6_78f6"; --1
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| 209 |
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wait for CLK_PERIOD;
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| 210 |
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| 211 |
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RX_Data_In <= "001" & X"3f5e5d5c5b5a5958";
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| 212 |
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wait for CLK_PERIOD*23;
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| 213 |
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| 214 |
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RX_Data_In <= "010" & X"78f6_78f6_78f6_78f6";--2
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| 215 |
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wait for CLK_PERIOD;
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| 216 |
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| 217 |
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RX_Data_In <= "001" & X"5f5e5a5c5b60f2a0";
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| 218 |
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wait for CLK_PERIOD*23;
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| 219 |
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| 220 |
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RX_Data_In <= "010" & X"78f6_78f6_78f6_78f6";--3
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| 221 |
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wait for CLK_PERIOD;
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| 222 |
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| 223 |
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RX_Data_In <= "001" & X"70000FFF000000F0";
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| 224 |
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wait for CLK_PERIOD*23;
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| 225 |
9 |
N.Boukadid |
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| 226 |
6 |
N.Boukadid |
RX_Data_In <= "010" & X"78f6_78f6_78f6_78f6";--4 -> lock
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| 227 |
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wait for CLK_PERIOD;
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| 228 |
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| 229 |
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RX_Data_In <= "001" & X"5f5e5a5c5b60f2a0";
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| 230 |
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wait for CLK_PERIOD;
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| 231 |
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| 232 |
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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| 233 |
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wait for CLK_PERIOD;
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| 234 |
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| 235 |
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RX_Data_In <= "001" & X"70000FFF000000F0";
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| 236 |
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wait for CLK_PERIOD*21;
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| 237 |
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| 238 |
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RX_Data_In <= "010" & X"78f6_78f6_78f6_78f6"; --Sync &
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| 239 |
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wait for CLK_PERIOD;
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| 240 |
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| 241 |
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RX_Data_In <= "010" & X"2Bfe_d100_19e0_1dbd";
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| 242 |
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wait for CLK_PERIOD;
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| 243 |
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| 244 |
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RX_Data_In <= "010" & X"1e1e_1e1e_1e1e_1e1e";
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| 245 |
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wait for CLK_PERIOD;
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| 246 |
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| 247 |
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RX_Data_In <= "001" & X"70000FFF000000F0";
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| 248 |
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wait for CLK_PERIOD*2;
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| 249 |
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| 250 |
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RX_Data_In <= "010" & X"E000_0001_0000_0000";
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| 251 |
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wait for CLK_PERIOD*3;
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| 252 |
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| 253 |
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RX_Data_In <= "001" & X"9486576758050505";
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| 254 |
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wait for CLK_PERIOD;
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| 255 |
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| 256 |
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RX_Data_In <= "001" & X"60b35d5dc4a582a7";
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| 257 |
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wait for CLK_PERIOD;
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| 258 |
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| 259 |
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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| 260 |
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wait for CLK_PERIOD*5;
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| 261 |
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| 262 |
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RX_Data_In <= "001" & X"1f5e5d5c5b5a5958";
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| 263 |
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wait for CLK_PERIOD*3;
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| 264 |
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| 265 |
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RX_Data_In <= "010" & X"6400_0000_6222_431a";
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| 266 |
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wait for clk_period;
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| 267 |
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| 268 |
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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| 269 |
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wait for CLK_PERIOD;
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| 270 |
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| 271 |
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RX_Data_In <= "001" & X"9486576758050505";
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| 272 |
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wait for CLK_PERIOD*19;
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| 273 |
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| 274 |
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wait for CLK_PERIOD;
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| 275 |
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| 276 |
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RX_Data_In <= "001" & X"8050505050050505";
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| 277 |
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wait for CLK_PERIOD*3;
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| 278 |
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| 279 |
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RX_Data_In <= "001" & X"9486576758050505";
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| 280 |
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wait for CLK_PERIOD;
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| 281 |
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| 282 |
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RX_Data_In <= "001" & X"60b35d5dc4a582a7";
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| 283 |
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wait for CLK_PERIOD;
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| 284 |
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| 285 |
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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| 286 |
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wait for CLK_PERIOD*12;
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| 287 |
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| 288 |
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
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| 289 |
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wait for CLK_PERIOD;
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| 290 |
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| 291 |
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RX_Data_In <= "001" & X"1f5e5d5c5b5a5958";
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| 292 |
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wait for CLK_PERIOD;
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| 293 |
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| 294 |
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| 295 |
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RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
|
| 296 |
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wait for CLK_PERIOD;
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| 297 |
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| 298 |
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RX_Data_In <= "001" & X"3f5e5d5c5b5a5958";
|
| 299 |
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wait for CLK_PERIOD;
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| 300 |
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| 301 |
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RX_Data_In <= "001" & X"4f21a2a3a4a5a6a7";
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| 302 |
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wait for CLK_PERIOD;
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| 303 |
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| 304 |
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RX_Data_In <= "001" & X"5f5e5a5c5b60f2a0";
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| 305 |
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wait for CLK_PERIOD;
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| 306 |
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| 307 |
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RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
|
| 308 |
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wait for CLK_PERIOD;
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| 309 |
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| 310 |
|
|
RX_Data_In <= "001" & X"5f5e5a5c5b60f2a0";
|
| 311 |
|
|
wait for CLK_PERIOD;
|
| 312 |
|
|
|
| 313 |
|
|
RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
|
| 314 |
|
|
wait for CLK_PERIOD;
|
| 315 |
|
|
|
| 316 |
|
|
RX_Data_In <= "001" & X"70000FFF000000F0";
|
| 317 |
|
|
wait for CLK_PERIOD*2;
|
| 318 |
|
|
|
| 319 |
|
|
RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
|
| 320 |
|
|
wait for CLK_PERIOD;
|
| 321 |
|
|
|
| 322 |
|
|
RX_Data_In <= "001" & X"8050505050050505";
|
| 323 |
|
|
wait for CLK_PERIOD*3;
|
| 324 |
|
|
|
| 325 |
|
|
RX_Data_In <= "001" & X"9486576758050505";
|
| 326 |
|
|
wait for CLK_PERIOD;
|
| 327 |
|
|
|
| 328 |
|
|
RX_Data_In <= "001" & X"60b35d5dc4a582a7";
|
| 329 |
|
|
wait for CLK_PERIOD*60;
|
| 330 |
|
|
|
| 331 |
|
|
RX_Data_In <= "001" & X"8050505050050505";
|
| 332 |
|
|
wait for CLK_PERIOD*3;
|
| 333 |
|
|
|
| 334 |
|
|
RX_Data_In <= "001" & X"9486576758050505";
|
| 335 |
|
|
wait for CLK_PERIOD;
|
| 336 |
|
|
|
| 337 |
|
|
RX_Data_In <= "001" & X"60b35d5dc4a582a7";
|
| 338 |
|
|
wait for CLK_PERIOD;
|
| 339 |
|
|
|
| 340 |
|
|
RX_Data_In <= "101" & X"60b35d5dc4a582a7";
|
| 341 |
|
|
wait for CLK_PERIOD*60;
|
| 342 |
|
|
|
| 343 |
|
|
RX_Data_In <= "110" & X"8050505050050505";
|
| 344 |
|
|
wait for CLK_PERIOD*3;
|
| 345 |
|
|
|
| 346 |
|
|
RX_Data_In <= "101" & X"9486576758050505";
|
| 347 |
|
|
wait for CLK_PERIOD;
|
| 348 |
|
|
|
| 349 |
|
|
RX_Data_In <= "101" & X"60b35d5dc4a582a7";
|
| 350 |
|
|
wait for CLK_PERIOD;
|
| 351 |
|
|
|
| 352 |
|
|
RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
|
| 353 |
|
|
wait for CLK_PERIOD*12;
|
| 354 |
|
|
|
| 355 |
|
|
RX_Data_In <= "111" & X"2c8e5d5c5b5a5958";
|
| 356 |
|
|
wait for CLK_PERIOD;
|
| 357 |
|
|
|
| 358 |
|
|
RX_Data_In <= "101" & X"1f5e5d5c5b5a5958";
|
| 359 |
|
|
wait for CLK_PERIOD*26;
|
| 360 |
|
|
|
| 361 |
|
|
RX_Data_In <= "111" & X"2c8e5d5c5b5a5958";
|
| 362 |
|
|
wait for CLK_PERIOD*18;
|
| 363 |
|
|
|
| 364 |
|
|
RX_Data_In <= "101" & X"1f5e5d5c5b5a5958";
|
| 365 |
|
|
wait;
|
| 366 |
9 |
N.Boukadid |
|
| 367 |
6 |
N.Boukadid |
end process;
|
| 368 |
|
|
|
| 369 |
|
|
end architecture tb_interlaken_receiver;
|
| 370 |
|
|
|
| 371 |
|
|
|
