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[/] [core1990_interlaken/] [trunk/] [gateware/] [simulation/] [interlaken_transmitter_tb.vhd] - Blame information for rev 6

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1 6 N.Boukadid 
library ieee;
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use ieee.std_logic_1164.all;
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4 
entity testbench_interlaken_transmitter is
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end entity testbench_interlaken_transmitter;
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architecture tb_interlaken_transmitter of testbench_interlaken_transmitter is
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        signal write_clk   : std_logic;
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        signal clk   : std_logic;
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        signal reset : std_logic;
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        signal TX_Data_In       : std_logic_vector(63 downto 0);
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        signal TX_Data_Out : std_logic_vector (66 downto 0); -- later 66 downto 0
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        signal TX_Enable        : std_logic;                         -- Enable the TX
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        signal TX_SOP           : std_logic;                         -- Start of Packet
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        signal TX_ValidBytes    : std_logic_vector(2 downto 0);      -- Valid bytes packet contains
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        signal TX_EOP           : std_logic;                         -- End of Packet
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        signal TX_FlowControl   : std_logic_vector(15 downto 0);     -- Flow control data (yet unutilized)
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        signal TX_Channel       : std_logic_vector(7 downto 0);      -- Select transmit channel (yet unutilized)
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        signal TX_Link_Up       : std_logic;
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        signal TX_Valid_Out     : std_logic;
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        signal TX_Control_Out   : std_logic;
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constant CLK_PERIOD : time := 10 ns;
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begin
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  uut : entity work.interlaken_transmitter
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  port map (
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    write_clk => write_clk,
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    clk => clk,
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    reset => reset,
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    TX_Data_In => TX_Data_In,
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    TX_Data_Out => TX_Data_Out,
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    TX_Enable => TX_Enable,
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    TX_SOP => TX_SOP,
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        TX_ValidBytes => TX_ValidBytes,
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        TX_EOP => TX_EOP,
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        TX_FlowControl => TX_FlowControl,
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        TX_Channel => TX_Channel,
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        TX_Link_Up => TX_Link_Up,
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        TX_Valid_Out => TX_Valid_Out,
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        TX_Control_Out => TX_Control_Out
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  );
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   Clk_process :process
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     begin
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          write_clk <= '1';
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          clk <= '1';
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          wait for CLK_PERIOD/2;  --for half of clock period clk stays at '0'.
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          clk <= '0';
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          write_clk <= '0';
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          wait for CLK_PERIOD/2;  --for next half of clock period clk stays at '1'.
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     end process;
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    simulation : process
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    begin
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        wait for 1 ps;
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        TX_Enable <= '0';
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        TX_EOP <= '0';
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        TX_SOP <= '0';
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        TX_Channel <= X"01";
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        TX_ValidBytes <= "111";
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        TX_data_in <= (others=>'0');
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        reset <= '1';
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        TX_FlowControl <= (others => '0');
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        wait for CLK_PERIOD;
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        wait for CLK_PERIOD;
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        --FIFO_meta <= '1';
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        reset <= '0';
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        TX_Enable <= '1';
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        TX_Data_in <= X"1f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        wait for CLK_PERIOD*10;
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        TX_SOP <= '1';
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        TX_EOP <= '1';
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        TX_Data_in <= X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        TX_EOP <= '0';
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        TX_data_in <= X"3f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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               TX_SOP <= '0';
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               TX_EOP <= '0';
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        TX_EOP <= '0';
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        --reset <= '1';
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        TX_Data_in <= X"4f21a2a3a4a5a6a7";
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        wait for CLK_PERIOD;
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        TX_FlowControl(0) <= '1';
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        TX_SOP <= '1';
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        TX_data_in <= X"5f5e5a5c5b60f2a0";
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        wait for CLK_PERIOD;
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        TX_SOP <= '0';
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        TX_EOP <= '1';
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        TX_data_in  <= X"635e22a3a4a5a7a7";
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        wait for CLK_PERIOD;
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        TX_EOP <= '0';
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        --TX_SOP <= '1';
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        TX_data_in  <= X"70000FFF000000F0";
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        wait for CLK_PERIOD*2;
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        TX_SOP <= '1';
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        TX_Data_in <= X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        TX_SOP <= '0';
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        TX_EOP <= '1';
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        wait for CLK_PERIOD;
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        TX_EOP <= '0';
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        --TX_SOP <= '0';
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        TX_data_in  <= X"8050505050050505";
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        --wait for CLK_PERIOD*3;
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        wait for CLK_PERIOD;
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        TX_data_in  <= X"9486576758050505";
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        wait for CLK_PERIOD;
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        TX_EOP <= '1';
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        TX_data_in <= X"60b35d5dc4a582a7";
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        wait for CLK_PERIOD; --Test influencing pause state position
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        TX_EOP <= '0';
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        wait for CLK_period*16;
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        TX_SOP <= '1';
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        TX_Data_in <= X"4f21a2a3a4a5a6a7";
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        --wait for CLK_PERIOD;
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        TX_data_in <= X"995e5a5c5b60f2a0";
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        wait for CLK_PERIOD;
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        TX_data_in  <= X"635e22a3a4a5a7a7";
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        wait for CLK_PERIOD;
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        TX_data_in  <= X"70000FFF000000F0";
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        wait for CLK_PERIOD*2;
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        TX_Data_in <= X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        TX_Data_in <= X"4f21a2a3a4a5a6a7";
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        wait for CLK_PERIOD;
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        TX_data_in <= X"5f5e5a5c5b60f2a0";
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        wait for CLK_PERIOD;
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        TX_data_in  <= X"635e22a3a4a5a7a7";
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        wait for CLK_PERIOD;
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        TX_data_in  <= X"70000FFF000000F0";
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        wait for CLK_PERIOD*2;
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        TX_data_in <= X"2f5e5d5c5b5a5958";
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        wait for CLK_PERIOD*12;
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        TX_Data_in <= X"4f5e5d5c5b5a5958";
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        wait for CLK_PERIOD;
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        TX_SOP <= '0';
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        TX_EOP <= '1';
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        wait for CLK_PERIOD;
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        --FIFO_meta <= '0';
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        wait for CLK_PERIOD*4;
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        --FIFO_meta <= '1';
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        wait;
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    end process;
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end architecture tb_interlaken_transmitter;
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