OpenCores
URL https://opencores.org/ocsvn/core1990_interlaken/core1990_interlaken/trunk

Subversion Repositories core1990_interlaken

[/] [core1990_interlaken/] [trunk/] [gateware/] [simulation/] [interlaken_transmitter_tb.vhd] - Blame information for rev 7

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 N.Boukadid 
library ieee;
2 
use ieee.std_logic_1164.all;
3 
 
4 
entity testbench_interlaken_transmitter is
5 
end entity testbench_interlaken_transmitter;
6 
 
7 
architecture tb_interlaken_transmitter of testbench_interlaken_transmitter is
8 
 
9 
        signal write_clk   : std_logic;
10 
        signal clk   : std_logic;
11 
        signal reset : std_logic;
12 
 
13 
        signal TX_Data_In       : std_logic_vector(63 downto 0);
14 
        signal TX_Data_Out : std_logic_vector (66 downto 0); -- later 66 downto 0
15 
 
16 
        signal TX_Enable        : std_logic;                         -- Enable the TX
17 
        signal TX_SOP           : std_logic;                         -- Start of Packet
18 
        signal TX_ValidBytes    : std_logic_vector(2 downto 0);      -- Valid bytes packet contains
19 
        signal TX_EOP           : std_logic;                         -- End of Packet
20 
        signal TX_FlowControl   : std_logic_vector(15 downto 0);     -- Flow control data (yet unutilized)
21 
        signal TX_Channel       : std_logic_vector(7 downto 0);      -- Select transmit channel (yet unutilized)
22 
 
23 
        signal TX_Link_Up       : std_logic;
24 
 
25 
        signal TX_Valid_Out     : std_logic;
26 
        signal TX_Control_Out   : std_logic;
27 
 
28 
constant CLK_PERIOD : time := 10 ns;
29 
 
30 
begin
31 
  uut : entity work.interlaken_transmitter
32 
  port map (
33 
    write_clk => write_clk,
34 
    clk => clk,
35 
    reset => reset,
36 
    TX_Data_In => TX_Data_In,
37 
    TX_Data_Out => TX_Data_Out,
38 
    TX_Enable => TX_Enable,
39 
    TX_SOP => TX_SOP,
40 
        TX_ValidBytes => TX_ValidBytes,
41 
        TX_EOP => TX_EOP,
42 
        TX_FlowControl => TX_FlowControl,
43 
        TX_Channel => TX_Channel,
44 
 
45 
        TX_Link_Up => TX_Link_Up,
46 
        TX_Valid_Out => TX_Valid_Out,
47 
        TX_Control_Out => TX_Control_Out
48 
  );
49 
 
50 
   Clk_process :process
51 
     begin
52 
          write_clk <= '1';
53 
          clk <= '1';
54 
          wait for CLK_PERIOD/2;  --for half of clock period clk stays at '0'.
55 
          clk <= '0';
56 
          write_clk <= '0';
57 
          wait for CLK_PERIOD/2;  --for next half of clock period clk stays at '1'.
58 
     end process;
59 
 
60 
    simulation : process
61 
    begin
62 
        wait for 1 ps;
63 
        TX_Enable <= '0';
64 
        TX_EOP <= '0';
65 
        TX_SOP <= '0';
66 
        TX_Channel <= X"01";
67 
        TX_ValidBytes <= "111";
68 
        TX_data_in <= (others=>'0');
69 
        reset <= '1';
70 
        TX_FlowControl <= (others => '0');
71 
 
72 
        wait for CLK_PERIOD;
73 
 
74 
        wait for CLK_PERIOD;
75 
        --FIFO_meta <= '1';
76 
        reset <= '0';
77 
        TX_Enable <= '1';
78 
        TX_Data_in <= X"1f5e5d5c5b5a5958";
79 
        wait for CLK_PERIOD;
80 
 
81 
 
82 
        wait for CLK_PERIOD*10;
83 
        TX_SOP <= '1';
84 
        TX_EOP <= '1';
85 
        TX_Data_in <= X"2f5e5d5c5b5a5958";
86 
        wait for CLK_PERIOD;
87 
 
88 
        TX_EOP <= '0';
89 
        TX_data_in <= X"3f5e5d5c5b5a5958";
90 
        wait for CLK_PERIOD;
91 
 
92 
 
93 
               TX_SOP <= '0';
94 
               TX_EOP <= '0';
95 
        TX_EOP <= '0';
96 
        --reset <= '1';
97 
        TX_Data_in <= X"4f21a2a3a4a5a6a7";
98 
        wait for CLK_PERIOD;
99 
        TX_FlowControl(0) <= '1';
100 
        TX_SOP <= '1';
101 
        TX_data_in <= X"5f5e5a5c5b60f2a0";
102 
        wait for CLK_PERIOD;
103 
 
104 
        TX_SOP <= '0';
105 
        TX_EOP <= '1';
106 
        TX_data_in  <= X"635e22a3a4a5a7a7";
107 
        wait for CLK_PERIOD;
108 
 
109 
        TX_EOP <= '0';
110 
        --TX_SOP <= '1';
111 
        TX_data_in  <= X"70000FFF000000F0";
112 
        wait for CLK_PERIOD*2;
113 
 
114 
        TX_SOP <= '1';
115 
        TX_Data_in <= X"2f5e5d5c5b5a5958";
116 
        wait for CLK_PERIOD;
117 
 
118 
        TX_SOP <= '0';
119 
        TX_EOP <= '1';
120 
        wait for CLK_PERIOD;
121 
 
122 
        TX_EOP <= '0';
123 
        --TX_SOP <= '0';
124 
        TX_data_in  <= X"8050505050050505";
125 
        --wait for CLK_PERIOD*3;
126 
        wait for CLK_PERIOD;
127 
        TX_data_in  <= X"9486576758050505";
128 
        wait for CLK_PERIOD;
129 
 
130 
        TX_EOP <= '1';
131 
        TX_data_in <= X"60b35d5dc4a582a7";
132 
        wait for CLK_PERIOD; --Test influencing pause state position
133 
 
134 
        TX_EOP <= '0';
135 
        wait for CLK_period*16;
136 
 
137 
        TX_SOP <= '1';
138 
        TX_Data_in <= X"4f21a2a3a4a5a6a7";
139 
        --wait for CLK_PERIOD;
140 
 
141 
        TX_data_in <= X"995e5a5c5b60f2a0";
142 
        wait for CLK_PERIOD;
143 
 
144 
        TX_data_in  <= X"635e22a3a4a5a7a7";
145 
        wait for CLK_PERIOD;
146 
 
147 
        TX_data_in  <= X"70000FFF000000F0";
148 
        wait for CLK_PERIOD*2;
149 
 
150 
        TX_Data_in <= X"2f5e5d5c5b5a5958";
151 
        wait for CLK_PERIOD;
152 
 
153 
        TX_Data_in <= X"4f21a2a3a4a5a6a7";
154 
        wait for CLK_PERIOD;
155 
 
156 
        TX_data_in <= X"5f5e5a5c5b60f2a0";
157 
        wait for CLK_PERIOD;
158 
 
159 
        TX_data_in  <= X"635e22a3a4a5a7a7";
160 
        wait for CLK_PERIOD;
161 
 
162 
        TX_data_in  <= X"70000FFF000000F0";
163 
        wait for CLK_PERIOD*2;
164 
 
165 
 
166 
        TX_data_in <= X"2f5e5d5c5b5a5958";
167 
        wait for CLK_PERIOD*12;
168 
 
169 
        TX_Data_in <= X"4f5e5d5c5b5a5958";
170 
        wait for CLK_PERIOD;
171 
 
172 
        TX_SOP <= '0';
173 
        TX_EOP <= '1';
174 
        wait for CLK_PERIOD;
175 
 
176 
        --FIFO_meta <= '0';
177 
        wait for CLK_PERIOD*4;
178 
        --FIFO_meta <= '1';
179 
        wait;
180 
    end process;
181 
 
182 
end architecture tb_interlaken_transmitter;
183 
 
184 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.