OpenCores
URL https://opencores.org/ocsvn/core_arm/core_arm/trunk

Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [.config] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 tarookumic
#
2
# Automatically generated make config: don't edit
3
#
4
 
5
#
6
# Synthesis
7
#
8
# CONFIG_SYN_GENERIC is not set
9
# CONFIG_SYN_ATC35 is not set
10
# CONFIG_SYN_ATC25 is not set
11
# CONFIG_SYN_ATC18 is not set
12
# CONFIG_SYN_FS90 is not set
13
# CONFIG_SYN_UMC018 is not set
14
# CONFIG_SYN_TSMC025 is not set
15
# CONFIG_SYN_PROASIC is not set
16
# CONFIG_SYN_AXCEL is not set
17
# CONFIG_SYN_VIRTEX is not set
18
CONFIG_SYN_VIRTEX2=y
19
# CONFIG_SYN_INFER_RAM is not set
20
# CONFIG_SYN_INFER_REGF is not set
21
# CONFIG_SYN_INFER_ROM is not set
22
# CONFIG_SYN_INFER_PCI_PADS is not set
23
# CONFIG_SYN_INFER_MULT is not set
24
# CONFIG_SYN_RFTYPE is not set
25
# CONFIG_SYN_TRACE_DPRAM is not set
26
 
27
#
28
# ------------------ Xilinx Clock generation ------------------
29
#
30
 
31
#
32
# Clock generation
33
#
34
# CONFIG_CLK_VIRTEX is not set
35
# CONFIG_CLK_VIRTEX2 is not set
36
# CONFIG_PCI_DLL is not set
37
# CONFIG_PCI_SYSCLK is not set
38
 
39
#
40
# Target Architecture
41
#
42
CONFIG_TARGET_ARM=y
43
# CONFIG_TARGET_SPARC is not set
44
# CONFIG_TARGET_M68K is not set
45
 
46
#
47
# Target ARM
48
#
49
 
50
#
51
# Integer unit
52
#
53
 
54
#
55
# Cache system
56
#
57
 
58
#
59
# Instruction cache
60
#
61
CONFIG_ICACHE_ASSO1=y
62
# CONFIG_ICACHE_ASSO2 is not set
63
# CONFIG_ICACHE_ASSO3 is not set
64
# CONFIG_ICACHE_ASSO4 is not set
65
CONFIG_ICACHE_SZ1=y
66
# CONFIG_ICACHE_SZ2 is not set
67
# CONFIG_ICACHE_SZ4 is not set
68
# CONFIG_ICACHE_SZ8 is not set
69
# CONFIG_ICACHE_SZ16 is not set
70
# CONFIG_ICACHE_SZ32 is not set
71
# CONFIG_ICACHE_SZ64 is not set
72
CONFIG_ICACHE_LZ4=y
73
# CONFIG_ICACHE_LZ8 is not set
74
# CONFIG_GENICACHE_LOCK is not set
75
 
76
#
77
# Data cache
78
#
79
# CONFIG_DCACHE_WRITEBACK is not set
80
CONFIG_DCACHE_WRITETHROUGH=y
81
CONFIG_DCACHE_ASSO1=y
82
# CONFIG_DCACHE_ASSO2 is not set
83
# CONFIG_DCACHE_ASSO3 is not set
84
# CONFIG_DCACHE_ASSO4 is not set
85
CONFIG_DCACHE_SZ1=y
86
# CONFIG_DCACHE_SZ2 is not set
87
# CONFIG_DCACHE_SZ4 is not set
88
# CONFIG_DCACHE_SZ8 is not set
89
# CONFIG_DCACHE_SZ16 is not set
90
# CONFIG_DCACHE_SZ32 is not set
91
# CONFIG_DCACHE_SZ64 is not set
92
CONFIG_DCACHE_LZ4=y
93
# CONFIG_DCACHE_LZ8 is not set
94
# CONFIG_GENDCACHE_LOCK is not set
95
# CONFIG_DCACHE_WB_SZ1 is not set
96
CONFIG_DCACHE_WB_SZ2=y
97
# CONFIG_DCACHE_WB_SZ4 is not set
98
# CONFIG_DCACHE_WB_SZ8 is not set
99
# CONFIG_DCACHE_WB_SZ16 is not set
100
 
101
#
102
# Amba bus
103
#
104
CONFIG_AHB_DEFMST=0
105
# CONFIG_AHB_SPLIT is not set
106
# CONFIG_PERI_AHBSTAT is not set
107
 
108
#
109
# Peripherals
110
#
111
 
112
#
113
# Memory
114
#
115
 
116
#
117
#  Memory controller
118
#
119
CONFIG_MCTRL_8BIT=y
120
CONFIG_MCTRL_16BIT=y
121
CONFIG_PERI_WPROT=y
122
CONFIG_MCTRL_WFB=y
123
CONFIG_MCTRL_5CS=y
124
CONFIG_MCTRL_SDRAM=y
125
CONFIG_MCTRL_SDRAM_INVCLK=y
126
 
127
#
128
#  On chip ram
129
#
130
# CONFIG_AHBRAM_ENABLE is not set
131
 
132
#
133
# Serial
134
#
135
 
136
#
137
# VHDL Debugging
138
#
139
# CONFIG_DEBUG_UART is not set
140
 
141
#
142
# ARM debugging
143
#

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.