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tarookumic |
(progn
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(load "cdef_lib_b1")
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(load "cdef_lib_c1")
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(load "cdef_lib_g1")
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(load "cdef_lib_l1")
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(load "cdef_lib_m1")
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(load "cdef_lib_i1")
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(load "cdef_lib_h1")
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(load "cdef_lib_pc")
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(load "cdef_lib_pv")
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)
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(progn
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(if (load "cdef_lib_b1") ()(message "You have to set your elisp load-path variable, i.e: (setq load-path
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(append (list nil \"/home/eiselekd/vhdl_0.8/soft/cdef\") load-path)))"))
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(load "cdef_lib_c1")
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(load "cdef_lib_g1")
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(load "cdef_lib_l1")
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(load "cdef_lib_m1")
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(load "cdef_lib_i1")
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(load "cdef_lib_h1")
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(load "cdef_lib_pc")
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(load "cdef_lib_pv")
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(setq insn-help '(
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(c "Condition code")
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(op1 "Data processing opcode")
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(rn "Register rn")
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(rm "Register rm")
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(rs "Register rs")
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(rdl "Destination register long")
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(rd "Destination register rd")
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(sha "Shieft amount")
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(sh "Shieft direction")
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(dps "Update cpsr")
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(imm "Breakpoint imm part1")
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(imm2 "Breakpoint imm part2")
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(dsop "Dsp operand")
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(MS "Set cpsr")
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(MA "Multiply accumulate")
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(MU "Multiply unsigned")
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(SB "Swap byte")
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(LSP "pre-indexed")
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(LSU "add/sub base '1'=add")
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(LSW "writeback")
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(LSL "Load|Store '1'=Load")
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(S "Signed|Unsigned '1'=signed")
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(H "halfword|signedbyte '1'=halfword")
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(i81 "Immidiate8 part1")
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(i82 "Immidiate8 part2")
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(dpi "Immidiate8")
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(rot "Immidiate8 rotate")
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(rgl "register list")
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(R "Cpsr|Spsr '1'=Spsr")
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(MSK "move immidiate to status register mask")
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(LSB "Byte|word '1'=byte")
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(LMS "Set cpsr fro spsr")
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(BLL "Link")
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(BLH "Exchange")
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(Cp_N "Coprocessor n bit")
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(cpn "Coprocessor number")
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(crn "Coprocessor register rn")
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(crm "Coprocessor register rm")
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(of8 "offset8")
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(crd "Coprocessor destination register")
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(co1 "Coprocessor op1")
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(insn_dp_i_s "Data Processing immidiate shieft")
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(insn_msr "Move status register to register" )
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(insn_mrs "Move register to status register" )
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(insn_bex "Branch / exchange")
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(insn_clz "Count leading zero")
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(insn_blx "Branch and link /exchange")
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(insn_dsa "Dsp add|sub")
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(insn_brk "Breakpoint" )
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(insn_dsm "DSP multiply")
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(insn_dp_r_s "Data processing register shieft")
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(insn_mula "Multiply and accumulate")
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(insn_mull "Multiply long")
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(insn_swp "Swap|swap byte")
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(insn_ld1 "Load|Store halfword")
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(insn_ld2 "Load|Store halfword immidiate offset")
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(insn_ld3 "Load|Store two words register offset")
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(insn_ld4 "Load|Store signed halfword/byte register offset")
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(insn_ld5 "Load|Store two words register offset")
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(insn_ld6 "Load|Store signed halfword/byte immidiate offset")
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(insn_dp_i "Data processing immidiate")
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(insn_undef1 "Undefined instruction")
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(insn_misr "Move immidiate to status register")
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(insn_lsio "Load|Store imidiate offset")
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(insn_lsro "Load|Store register offset")
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(insn_undef2 "Undefined instruction2")
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(insn_undef3 "Undefined instruction3")
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(insn_lsm "Load|Store multiple")
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(insn_undef4 "Undefined instruction4")
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(insn_bwl "Branch with link")
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(insn_bwlth "Branch with link and change to thumb")
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(insn_cpldst "Coprocessor Load Store")
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(insn_cpdp "Coprocessor data processing")
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(insn_cpr "Coprocessor register transfer")
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(insn_swi "Software interrupt")
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(insn_undef "Undef")
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))
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;; list order 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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;; 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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(setq insn_dp_i_s '( c c c c 0 0 0 op1 op1 op1 op1 dps rn rn rn rn rd rd rd rd sha sha sha sha sha sh sh 0 rm rm rm rm ))
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(setq insn_msr '( c c c c 0 0 0 1 0 R 0 0 SBO SBO SBO SBO rd rd rd rd SBZ SBZ SBZ SBZ 0 0 0 0 SBZ2 SBZ2 SBZ2 SBZ2 ))
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(setq insn_mrs '( c c c c 0 0 0 1 0 R 1 0 msk msk msk msk SBO SBO SBO SBO SBZ SBZ SBZ SBZ 0 0 0 0 rm rm rm rm ))
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(setq insn_bex '( c c c c 0 0 0 1 0 0 1 0 SBO SBO SBO SBO SBO SBO SBO SBO SBO SBO SBO SBO 0 0 0 1 rm rm rm rm ))
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(setq insn_clz '( c c c c 0 0 0 1 0 1 1 0 SBO SBO SBO SBO rd rd rd rd SBO2 SBO2 SBO2 SBO2 0 0 0 1 rm rm rm rm ))
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(setq insn_blx '( c c c c 0 0 0 1 0 0 1 0 SBO SBO SBO SBO SBO SBO SBO SBO SBO SBO SBO SBO 0 0 1 1 rm rm rm rm ))
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(setq insn_dsa '( c c c c 0 0 0 1 0 dsop dsop 0 rn rn rn rn rd rd rd rd SBZ SBZ SBZ SBZ 0 1 0 1 rm rm rm rm ))
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(setq insn_brk '( c c c c 0 0 0 1 0 0 1 0 imm imm imm imm imm imm imm imm imm imm imm imm 0 1 1 1 imm2 imm2 imm2 imm2 ))
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(setq insn_dsm '( c c c c 0 0 0 1 0 dsop dsop 0 RD RD RD RD rn rn rn rn rs rs rs rs 1 y x 0 rm rm rm rm ))
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(setq insn_dp_r_s '( c c c c 0 0 0 op1 op1 op1 op1 dps rn rn rn rn rd rd rd rd rs rs rs rs 0 sh sh 1 rm rm rm rm ))
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(setq insn_mula '( c c c c 0 0 0 0 0 0 MA MS rd rd rd rd rn rn rn rn rs rs rs rs 1 0 0 1 rm rm rm rm ))
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(setq insn_mull '( c c c c 0 0 0 0 1 MU MA MS rd rd rd rd rdl rdl rdl rdl rs rs rs rs 1 0 0 1 rm rm rm rm ))
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(setq insn_swp '( c c c c 0 0 0 1 0 SB 0 0 rn rn rn rn rd rd rd rd sbz sbz sbz sbz 1 0 0 1 rm rm rm rm ))
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(setq insn_ld1 '( c c c c 0 0 0 LSP LSU 0 LSW LSL rn rn rn rn rd rd rd rd sbz sbz sbz sbz 1 0 1 1 rm rm rm rm ))
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(setq insn_ld2 '( c c c c 0 0 0 LSP LSU 1 LSW LSL rn rn rn rn rd rd rd rd i81 i81 i81 i81 1 0 1 1 i82 i82 i82 i82 ))
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(setq insn_ld3 '( c c c c 0 0 0 LSP LSU 0 LSW 0 rn rn rn rn rd rd rd rd i81 i81 i81 i81 1 1 S 1 i82 i82 i82 i82 ))
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(setq insn_ld4 '( c c c c 0 0 0 LSP LSU 0 LSW 1 rn rn rn rn rd rd rd rd i81 i81 i81 i81 1 1 H 1 i82 i82 i82 i82 ))
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(setq insn_ld5 '( c c c c 0 0 0 LSP LSU 1 LSW 0 rn rn rn rn rd rd rd rd i81 i81 i81 i81 1 1 S 1 i82 i82 i82 i82 ))
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(setq insn_ld6 '( c c c c 0 0 0 LSP LSU 1 LSW 1 rn rn rn rn rd rd rd rd i81 i81 i81 i81 1 1 H 1 i82 i82 i82 i82 ))
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(setq insn_dp_i '( c c c c 0 0 1 op1 op1 op1 op1 dps rn rn rn rn rd rd rd rd rot rot rot rot dpi dpi dpi dpi dpi dpi dpi dpi ))
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(setq insn_undef1 '( c c c c 0 0 1 1 0 X2 0 0 X X X X X X X X X X X X X X X X X X X X ))
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(setq insn_misr '( c c c c 0 0 1 1 0 R 1 0 MSK MSK MSK MSK SBQ SBQ SBQ SBQ rot rot rot rot dpi dpi dpi dpi dpi dpi dpi dpi ))
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(setq insn_lsio '( c c c c 0 1 0 LSP LSU LSB LSW LSL rn rn rn rn rd rd rd rd LSI LSI LSI LSI LSI LSI LSI LSI LSI LSI LSI LSI ))
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(setq insn_lsro '( c c c c 0 1 1 LSP LSU LSB LSW LSL rn rn rn rn rd rd rd rd sha sha sha sha sha sh sh 0 rm rm rm rm ))
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(setq insn_undef2 '( c c c c 0 1 1 X X X X X X X X X X X X X X X X X X X X 1 X2 X2 X2 X2 ))
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(setq insn_undef3 '( 1 1 1 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X ))
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(setq insn_lsm '( c c c c 0 1 1 LSP LSU LMS LSW LSL rn rn rn rn rgl rgl rgl rgl rgl rgl rgl rgl rgl rgl rgl rgl rgl rgl rgl rgl ))
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(setq insn_undef4 '( 1 1 1 1 1 0 0 X X X X X X X X X X X X X X X X X X X X X X X X X ))
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(setq insn_bwl '( c c c c 1 0 1 BLL blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo))
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(setq insn_bwlth '( 1 1 1 1 1 0 1 BLH blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo blo))
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(setq insn_cpldst '( c c c c 1 1 0 LSP LSU Cp_N LSW LSL rn rn rn rn crd crd crd crd cpn cpn cpn cpn of8 of8 of8 of8 of8 of8 of8 of8 ))
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(setq insn_cpdp '( c c c c 1 1 0 0 co1 co1 co1 co1 crn crn crn crn rd rd rd rd cpn cpn cpn cpn cp1 cp1 cp1 0 crm crm crm crm ))
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(setq insn_cpr '( c c c c 1 1 0 0 co1 co1 co1 LSL crn crn crn crn rd rd rd rd cpn cpn cpn cpn cp1 cp1 cp1 1 crm crm crm crm ))
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(setq insn_swi '( c c c c 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X ))
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(setq insn_undef '( 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X ))
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(setq insn '(
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insn_dp_i_s insn_msr insn_mrs insn_bex insn_clz insn_blx insn_dsa
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insn_brk insn_dsm insn_dp_r_s insn_mula insn_mull insn_swp insn_ld1
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insn_ld2 insn_ld3 insn_ld4 insn_ld5 insn_ld6 insn_dp_i insn_undef1
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insn_misr insn_lsio insn_lsro insn_undef2 insn_undef3 insn_lsm insn_undef4
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insn_bwl insn_bwlth insn_cpldst insn_cpdp insn_cpr insn_swi insn_undef
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))
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(setq h (create-decoder-setenc (or-insn-set insn) insn 0))
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;(insert (print-decoder h 0))
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(insert (print-decoder-c-pre h))
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(insert (print-decoder-c-structs insn insn-help))
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;(insert (print-decoder-vhd-pre h))
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)
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