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[/] [core_arm/] [trunk/] [soft/] [tbenchsoft/] [arm/] [romlocore.S] - Blame information for rev 6

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1 2 tarookumic 
#include "arm.h"
2 
 
3 
        /*
4 
         * Memctrl Initialization
5 
         */
6 
        nop
7 
 
8 
        mov r0,   #0x00810000
9 
        orr r0,r0,#0x0000000f
10 
        mov r1,   #0x80000014
11 
        str r0,[r1]
12 
 
13 
        mov r0,   #0x04000000
14 
        orr r0,r0,#0x00080000
15 
        orr r0,r0,#0x00000300
16 
        mov r1,   #0x80000000
17 
        str r0,[r1]
18 
        mov r0,   #0xd5000000
19 
        orr r0,r0,#0x00380000
20 
        orr r0,r0,#0x00004800
21 
        orr r0,r0,#0x00000030
22 
        mov r1,   #0x80000000
23 
        orr r1,r1,#0x00000004
24 
        str r0,[r1]
25 
        mov r0,   #0x000f0000
26 
        mov r1,   #0x80000000
27 
        orr r1,r1,#0x00000008
28 
        str r0,[r1]
29 
 
30 
 
31 
        mov     ip,#0x40000000
32 
        orr     ip,ip, #0x1000
33 
        mov     sp,#0x40000000
34 
        orr     sp,sp, #0x1000
35 
 
36 
        .globl  func1
37 
 
38 
        bl func1
39 
 
40 
 
41 
 
42 
 
43 
 
44 
        /* coprocessor */
45 
        mrc 15,1,r0,cr1,cr0
46 
        orr r0,r0,#0x00000001
47 
        mcr 15,0,r0,cr1,cr0
48 
        mrc 15,1,r0,cr1,cr0
49 
 
50 
 
51 
 
52 
 
53 
 
54 
        /*
55 
         * msr
56 
         * -- msr CPSR_[cxsf],#
57 
         * -- msr CPSR_[cxsf],
58 
         * -- msr SPSR_[cxsf],#
59 
         * -- msr SPSR_[cxsf],
60 
         */
61 
        mov r13,#0x13 /* svc */
62 
        mov r8,#0xaa
63 
 
64 
        msr CPSR_c,#0x17 /* abort */
65 
        mov r13,#0x17
66 
        mov r8,#0xaa
67 
 
68 
        msr CPSR_c,#0x1b /* undefined */
69 
        mov r13,#0x1b
70 
        mov r8,#0xaa
71 
 
72 
        msr CPSR_c,#0x12 /* irq */
73 
        mov r13,#0x12
74 
        mov r8,#0xaa
75 
 
76 
        msr CPSR_c,#0x11 /* fiq */
77 
        mov r13,#0x11
78 
        mov r8,#0x11
79 
        mov r12,#0x11
80 
 
81 
 
82 
        msr CPSR_c,#0x1f /* sys */
83 
        mov r13,#0x1f
84 
 
85 
 
86 
        /* read in sys */
87 
        msr CPSR_c,#0x1f
88 
        mov r1,r13
89 
        mov r1,r8
90 
 
91 
        /* read in abort */
92 
        msr CPSR_c,#0x17
93 
        mov r1,r13
94 
        mov r1,r8
95 
 
96 
        /* read in svc */
97 
        msr CPSR_c,#0x13
98 
        mov r1,r13
99 
        mov r1,r8
100 
 
101 
        /* read in irq */
102 
        msr CPSR_c,#0x12
103 
        mov r1,r13
104 
        mov r1,r8
105 
 
106 
        /* read in fiq */
107 
        msr CPSR_c,#0x11
108 
        mov r1,r13
109 
        mov r1,r8
110 
 
111 
        /* read in undef */
112 
        msr CPSR_c,#0x1b
113 
        mov r1,r13
114 
        mov r1,r8
115 
 
116 
 
117 
 
118 
 
119 
 
120 
 
121 
 
122 
 
123 
 
124 
 
125 
        mov r0,   #0x40000000
126 
        mov r1,   #0x1
127 
        ldr r1,[r0]
128 
        mov r1,   #0x2
129 
 
130 
        mov r0,   #0x40000000
131 
        orr r0,r0,#0x00001000
132 
        ldr r1,[r0]
133 
 
134 
        mov r0,   #0x40000000
135 
        orr r0,r0,#0x00002000
136 
        ldr r1,[r0]
137 
 
138 
        mov r0,   #0x40000000
139 
        swp r1,r1,[r0]
140 
        swp r1,r1,[r0]
141 
        swp r1,r2,[r0]
142 
 
143 
 
144 
        /* armcmd_lm.vhd
145 
        -- LRM/STM: Increment after  (regorder [0-15],start:+0,end(onwb):+4) :ldmia|stmia ,{}
146 
        -- LRM/STM: Increment before (regorder [0-15],start:+4,end(onwb):+0) :ldmib|stmib ,{}
147 
        -- LRM/STM: Decrement after  (regorder [15-0],start:-0,end(onwb):-4) :ldmda|stmda ,{}
148 
        -- LRM/STM: Decrement before (regorder [15-0],start:-4,end(onwb):-0) :ldmdb|stmdb ,{}
149 
        */
150 
 
151 
        mov r0,   #0x40000000
152 
        ldr r1,[r0]
153 
        orr r0,r0,#0x00000010
154 
        ldmia r0,{r1,r2,r3}
155 
        ldmib r0,{r1,r2,r3}
156 
        ldmda r0,{r1,r2,r3}
157 
        ldmdb r0,{r1,r2,r3}
158 
 
159 
        stmia r0,{r1,r2,r3}
160 
        stmib r0,{r1,r2,r3}
161 
        stmda r0,{r1,r2,r3}
162 
        stmdb r0,{r1,r2,r3}
163 
 
164 
        /* locking */
165 
        mov r0,   #0x40000000
166 
        orr r0,r0,#0x00000010
167 
        str r0,[r0]
168 
        ldr r0,[r0]
169 
        ldmia r0,{r1,r2,r3}
170 
 
171 
 
172 
 
173 
 
174 
        /*
175 
        armcmd_ld.vhd.am.LDSTAM_typ:
176 
          adm_LDSTAM_simm
177 
            -- adm_atyp_LSV4AM.adm_LSV4AM_reg:
178 
            -- - L/S MISC: Register offset            : [, #+/-]
179 
            -- - L/S MISC: Register offset pre-index  : [, #+/-] !
180 
            -- - L/S MISC: Register offset post-index : [], #+/-
181 
        */
182 
        mov r1,   #0x40000004
183 
        mov r2,   #0x00000004
184 
        orr r2,r2,#0x05000000
185 
        mov r0,   #0x01000000
186 
        orr r0,r0,#0x00020000
187 
        orr r0,r0,#0x00000300
188 
        orr r0,r0,#0x00000004
189 
        str r0,[r1]
190 
        strb r2,[r1]
191 
        ldr r0,[r1]
192 
 
193 
        mov r2,   #0x4
194 
        ldrb r0,[r1,#0]
195 
        ldrb r0,[r1,#1]
196 
        ldrb r0,[r1,#2]
197 
        ldrb r0,[r1,#3]
198 
 
199 
 
200 
        --ldr r0,[r1,r2]
201 
        --ldr r0,[r1,-r2]
202 
        ldrb r0,[r1,r2]
203 
 
204 
        /*
205 
            -- adm_atyp_LSV4AM.adm_LSV4AM_reg:
206 
            -- - L/S MISC: Immediate offset            : [, #+/-]
207 
            -- - L/S MISC: Immediate offset pre-index  : [, #+/-] !
208 
            -- - L/S MISC: Immediate offset post-index : [], #+/-
209 
        */
210 
        mov r1,   #0x40000004
211 
        mov r2,   #0x4
212 
        ldrsb r0,[r1,-r2]
213 
        ldrsb r0,[r1,r2]
214 
        ldrsh r0,[r1,-r2]
215 
        ldrsh r0,[r1,r2]!
216 
        strh r0,[r1,r2]
217 
        strh r0,[r1,-r2]!
218 
 
219 
 
220 
        /*
221 
        armcmd_ld.vhd.am.LDSTAM_typ:
222 
          adm_LDSTAM_simm
223 
        -- L/S W/UB: Register Offset                     : [, +/-]
224 
        -- L/S W/UB: Register Offset pre-indexed         : [, +/-]!
225 
        -- L/S W/UB: Register Offset post-indexed        : [], +/-
226 
        -- L/S W/UB: Scaled Register Offset              : [, +/-, ]
227 
        -- L/S W/UB: Scaled Register Offset pre-indexed  : [, +/-, ]!
228 
        -- L/S W/UB: Scaled Register Offset post-indexed : [], +/-,
229 
        -- : {LSL #}|{LSR #}|{ASR #}|{ROR #}|{RRX}
230 
        */
231 
        mov r1,   #0x40000004
232 
        mov r2,   #0x4
233 
        ldr r0,[r1,r2]
234 
        ldr r0,[r1,-r2]
235 
        ldrb r0,[r1,r2]
236 
 
237 
        ldr r0,[r1,r2]!
238 
        ldr r0,[r1],r2
239 
 
240 
        mov r1,   #0x40000004
241 
        mov r2,   #0x4
242 
        ldr r0,[r1,r2, lsl #1]
243 
        ldr r0,[r1,r2, lsl #1]
244 
        ldr r0,[r1,r2, lsr #1]
245 
        ldr r0,[r1,r2, asr #1]
246 
        ldr r0,[r1,r2, ror #1]
247 
        ldr r0,[r1,r2, rrx]
248 
        ldr r0,[r1,r2, lsl #1]!
249 
        ldr r0,[r1,r2, lsr #1]!
250 
        ldr r0,[r1,r2, asr #1]!
251 
        ldr r0,[r1,r2, ror #1]!
252 
        ldr r0,[r1,r2, rrx]!
253 
        ldr r0,[r1],r2, lsl #1
254 
        ldr r0,[r1],r2, lsr #1
255 
        ldr r0,[r1],r2, asr #1
256 
        ldr r0,[r1],r2, ror #1
257 
        ldr r0,[r1],r2, rrx
258 
 
259 
        mov r1,   #0x40000004
260 
        mov r2,   #0x4
261 
        str r0,[r1,r2]
262 
        str r0,[r1,-r2]
263 
        strb r0,[r1,r2]
264 
 
265 
        str r0,[r1,r2]!
266 
        str r0,[r1],r2
267 
 
268 
        mov r1,   #0x40000004
269 
        mov r2,   #0x4
270 
        str r0,[r1,r2, lsl #1]
271 
        str r0,[r1,r2, lsr #1]
272 
        str r0,[r1,r2, asr #1]
273 
        str r0,[r1,r2, ror #1]
274 
        str r0,[r1,r2, rrx]
275 
        str r0,[r1,r2, lsl #1]!
276 
        str r0,[r1,r2, lsr #1]!
277 
        str r0,[r1,r2, asr #1]!
278 
        str r0,[r1,r2, ror #1]!
279 
        str r0,[r1,r2, rrx]!
280 
        str r0,[r1],r2, lsl #1
281 
        str r0,[r1],r2, lsr #1
282 
        str r0,[r1],r2, asr #1
283 
        str r0,[r1],r2, ror #1
284 
        str r0,[r1],r2, rrx
285 
 
286 
        /*
287 
        armcmd_l1.vhd.am.LDSTAM_typ:
288 
          adm_LDSTAM_off =>
289 
        -- L/S W/UB: Immediate Offset              : [, #+/-]
290 
        -- L/S W/UB: Immediate Offset pre-indexed  : [, #+/-]!
291 
        -- L/S W/UB: Immediate Offset post-indexed : [], #+/-
292 
        */
293 
 
294 
        mov r1,   #0x40000004
295 
        mov r2,   #0x4
296 
        ldr r0,[r1,#4]
297 
        ldr r0,[r1,#4]!
298 
        ldr r0,[r1],#4
299 
 
300 
        str r0,[r1,#4]
301 
        str r0,[r1,#4]!
302 
        str r0,[r1],#4
303 
 
304 
        /* locking */
305 
        ldr r0,[r1,#4]
306 
        ldr r0,[r1,#4]!
307 
        add r0,r0,r1
308 
 
309 
 
310 
        /* armcmd_lm.vhd
311 
        -- LRM/STM: Increment after  (regorder [0-15],start:+0,end(onwb):+4) :ldmia|stmia ,{}
312 
        -- LRM/STM: Increment before (regorder [0-15],start:+4,end(onwb):+0) :ldmib|stmib ,{}
313 
        -- LRM/STM: Decrement after  (regorder [15-0],start:-0,end(onwb):-4) :ldmda|stmda ,{}
314 
        -- LRM/STM: Decrement before (regorder [15-0],start:-4,end(onwb):-0) :ldmdb|stmdb ,{}
315 
        */
316 
 
317 
        ldmia r0,{r1,r2,r3}
318 
        ldmib r0,{r1,r2,r3}
319 
        ldmda r0,{r1,r2,r3}
320 
        ldmdb r0,{r1,r2,r3}
321 
 
322 
        stmia r0,{r1,r2,r3}
323 
        stmib r0,{r1,r2,r3}
324 
        stmda r0,{r1,r2,r3}
325 
        stmdb r0,{r1,r2,r3}
326 
 
327 
        /* locking */
328 
        ldr r0,[r1]
329 
        ldmia r0,{r1,r2,r3}
330 
 
331 
 
332 
 
333 
 
334 
 
335 
 
336 
 
337 
 
338 
 
339 
 
340 
 
341 
 
342 
 
343 
 
344 
 
345 
 
346 
 
347 
 
348 
                mov r1,pc
349 
        sub r1,r1,#8
350 
        mov r0,#0x40000000
351 
        str r1,[r0]
352 
loop2:  ldr pc,[r0]
353 
        nop
354 
        nop
355 
        nop
356 
        nop
357 
        nop
358 
        nop
359 
        nop
360 
        nop
361 
        nop
362 
        nop
363 
        nop
364 
 
365 
        /* armcmd_lm.vhd
366 
        -- LRM/STM: Increment after  (regorder [0-15],start:+0,end(onwb):+4) :ldmia|stmia ,{}
367 
        -- LRM/STM: Increment before (regorder [0-15],start:+4,end(onwb):+0) :ldmib|stmib ,{}
368 
        -- LRM/STM: Decrement after  (regorder [15-0],start:-0,end(onwb):-4) :ldmda|stmda ,{}
369 
        -- LRM/STM: Decrement before (regorder [15-0],start:-4,end(onwb):-0) :ldmdb|stmdb ,{}
370 
        */
371 
 
372 
        mov r0   ,#0x40000000
373 
        orr r0,r0,#0x00000100
374 
        mov r1,#1
375 
        mov r2,#2
376 
        mov r3,#3
377 
        stmia r0,{r1,r2,r3}
378 
 
379 
        ldmia r0,{r1,r2,r3}
380 
        ldmib r0,{r1,r2,r3}
381 
        ldmda r0,{r1,r2,r3}
382 
        ldmdb r0,{r1,r2,r3}
383 
 
384 
        stmia r0,{r1,r2,r3}
385 
        stmib r0,{r1,r2,r3}
386 
        stmda r0,{r1,r2,r3}
387 
        stmdb r0,{r1,r2,r3}
388 
 
389 
 
390 
 
391 
        /* armcmd_sw.vhd
392 
        -- sw ,,[]
393 
        */
394 
        mov r0   ,#0x40000000
395 
        mov r1,#0
396 
        str r1,[r0]
397 
        mov r1,#1
398 
        mov r2,#2
399 
 
400 
        swp r1,r1,[r0]
401 
        swp r1,r1,[r0]
402 
        swp r1,r2,[r0]
403 
 
404 
 
405 
        /*
406 
        armcmd_al.vhd.am.DAPRAM_typ:
407 
          adm_DAPRAM_simm
408 
        -- DP op2: Register                     :
409 
        -- DP op2: Register  by Immediate : ,  #
410 
        -- DP op2: Register RRX                 : , RRX
411 
        -- : {LSL}|{LSR}|{ASR}|{ROR}
412 
        */
413 
        mov r0,   #0x0
414 
        mov r1,   #0x1
415 
        mov r2,   #0x2
416 
        mov r3,   #0x3
417 
        add r0,r1,r2
418 
        add r0,r1,r2, lsl #1
419 
        add r0,r1,r2, lsr #1
420 
        add r0,r1,r2, asr #1
421 
        add r0,r1,r2, ror #1
422 
        add r0,r1,r2, rrx
423 
 
424 
        /*
425 
        armcmd_al.vhd.am.DAPRAM_typ:
426 
          adm_DAPRAM_sreg
427 
        -- DP op2: Register  by Register  : ,
428 
        -- : {LSL}|{LSR}|{ASR}|{ROR}
429 
        */
430 
        add r0,r1,r2,lsl r3
431 
        add r0,r1,r2,lsr r3
432 
        add r0,r1,r2,asr r3
433 
        add r0,r1,r2,ror r3
434 
 
435 
        /*
436 
        armcmd_al.vhd.am.DAPRAM_typ:
437 
          adm_DAPRAM_immrot =>
438 
        -- DP op2: Immediate #
439 
        */
440 
        add r0,r1,#1
441 
 
442 
        /* locking */
443 
        add r0,r1,r2
444 
        add r0,r0,r1
445 
        add r0,r1,r0
446 
        add r0,r1,r0,lsl #1
447 
 
448 
 
449 
 
450 
 
451 
 
452 
 
453 
 
454 
 
455 
 
456 
 
457 
 
458 
 
459 
 
460 
 
461 
 
462 
 
463 
 
464 
 
465 
 
466 
 
467 
 
468 
 
469 
 
470 
 
471 
        /* adm_DAPRAMxLDSTAM_DAPRAM_sreg shiefter */
472 
        /* adm_slsl:
473 
          --if Rs[7:0] == 0 then
474 
          --  shifter_operand = Rm
475 
          --  shifter_carry_out = C Flag
476 
          --else if Rs[7:0] < 32 then
477 
          --  shifter_operand = Rm Logical_Shift_Left Rs[7:0]
478 
          --  shifter_carry_out = Rm[32 - Rs[7:0]]
479 
          --else if Rs[7:0] == 32 then
480 
          --  shifter_operand = 0
481 
          --  shifter_carry_out = Rm[0]
482 
          --else  Rs[7:0] > 32
483 
          --  shifter_operand = 0
484 
          --  shifter_carry_out = 0
485 
        */
486 
        movs r1,#0x1
487 
        movs r2,#0xc0000001
488 
        movs r3,#0
489 
        adds r0,r1,r2,lsl r3
490 
 
491 
        movs r1,#0x1
492 
        movs r2,#0xc0000001
493 
        mov  r3,#0
494 
        adds r0,r1,r2,lsl r3
495 
 
496 
 
497 
        movs r3,#1
498 
        adds r0,r1,r2,lsl r3
499 
        movcss r3,#32
500 
        addcss r0,r1,r2,lsl r3
501 
        movcss r3,#33
502 
        addcss r0,r1,r2,lsl r3
503 
 
504 
        movs r2,#0x40000001
505 
        movs r3,#1
506 
        adds r0,r1,r2,lsl r3  /* carry 0 */
507 
        movs r2,#0xc0000000
508 
        movs r3,#32
509 
        adds r0,r1,r2,lsl r3  /* carry 0 */
510 
 
511 
        /* adm_DAPRAMxLDSTAM_DAPRAM_sreg shiefter */
512 
        /* adm_slsr:
513 
          --if Rs[7:0] == 0 then
514 
          --  shifter_operand = Rm
515 
          --  shifter_carry_out = C Flag
516 
          --else if Rs[7:0] < 32 then
517 
          --  shifter_operand = Rm Logical_Shift_Right Rs[7:0]
518 
          --  shifter_carry_out = Rm[Rs[7:0] - 1]
519 
          --else if Rs[7:0] == 32 then
520 
          --  shifter_operand = 0
521 
          --  shifter_carry_out = Rm[31]
522 
          --else   Rs[7:0] > 32
523 
          --  shifter_operand = 0
524 
          --  shifter_carry_out = 0
525 
        */
526 
        mov r2,#0xc0000001
527 
        mov r3,#0
528 
        add r0,r1,r2,lsr r3
529 
        mov r3,#1
530 
        add r0,r1,r2,lsr r3
531 
        mov r3,#32
532 
        add r0,r1,r2,lsr r3
533 
        mov r3,#33
534 
        add r0,r1,r2,lsr r3
535 
 
536 
        mov r2,#0x40000001
537 
        mov r3,#1
538 
        add r0,r1,r2,lsr r3  /* carry 0 */
539 
        mov r2,#0x40000001
540 
        mov r3,#32
541 
        add r0,r1,r2,lsr r3  /* carry 0 */
542 
 
543 
        /* adm_DAPRAMxLDSTAM_DAPRAM_sreg shiefter */
544 
        /* adm_sasr:
545 
          --if Rs[7:0] == 0 then
546 
          --  shifter_operand = Rm
547 
          --  shifter_carry_out = C Flag
548 
          --else if Rs[7:0] < 32 then
549 
          --  shifter_operand = Rm Arithmetic_Shift_Right Rs[7:0]
550 
          --  shifter_carry_out = Rm[Rs[7:0] - 1]
551 
          --else  Rs[7:0] >= 32
552 
          --  if Rm[31] == 0 then
553 
          --    shifter_operand = 0
554 
          --    shifter_carry_out = Rm[31]
555 
          --  else  Rm[31] == 1
556 
          --    shifter_operand = 0xFFFFFFFF
557 
          --    shifter_carry_out = Rm[31]
558 
        */
559 
        mov r2,#0xc0000001
560 
        mov r3,#0
561 
        add r0,r1,r2,asr r3
562 
        mov r3,#1
563 
        add r0,r1,r2,asr r3
564 
        mov r2,#0xc0000001
565 
        mov r3,#32
566 
        add r0,r1,r2,asr r3
567 
        mov r2,#0x40000001
568 
        mov r3,#32
569 
        add r0,r1,r2,asr r3
570 
 
571 
        mov r2,#0x40000001
572 
        mov r3,#1
573 
        add r0,r1,r2,asr r3  /* carry 0 */
574 
        mov r2,#0x40000000
575 
        mov r3,#32
576 
        add r0,r1,r2,asr r3  /* carry 0 */
577 
 
578 
        /* adm_DAPRAMxLDSTAM_DAPRAM_sreg shiefter */
579 
        /* adm_sror:
580 
          --if Rs[7:0] == 0 then
581 
          --  shifter_operand = Rm
582 
          --  shifter_carry_out = C Flag
583 
          --else if Rs[4:0] == 0 then
584 
          --  shifter_operand = Rm
585 
          --  shifter_carry_out = Rm[31]
586 
          --else  Rs[4:0] > 0
587 
          --  shifter_operand = Rm Rotate_Right Rs[4:0]
588 
          --  shifter_carry_out = Rm[Rs[4:0] - 1]
589 
        */
590 
 
591 
        mov r2,#0x40000001
592 
        mov r3,#0
593 
        add r0,r1,r2,ror r3
594 
        mov r2,#0xc0000001
595 
        mov r3,#0
596 
        add r0,r1,r2,ror r3
597 
        mov r3,#1
598 
        add r0,r1,r2,ror r3
599 
        mov r3,#32
600 
        add r0,r1,r2,ror r3
601 
        mov r2,#0x40000001
602 
        mov r3,#32
603 
        add r0,r1,r2,ror r3
604 
 
605 
        mov r3,#33
606 
        add r0,r1,r2,ror r3
607 
 
608 
        /* adm_DAPRAMxLDSTAM_DAPRAM_sreg shiefter */
609 
        /* adm_srrx:
610 
          --shifter_operand = (C Flag Logical_Shift_Left 31) OR (Rm Logical_Shift_Right 1)
611 
          --shifter_carry_out = Rm[0]
612 
        */
613 
        mov r2,#0xc0000001
614 
        mov r3,#0
615 
        add r0,r1,r2,rrx
616 
 
617 
        /* adm_DAPRAMxLDSTAM_DAPRAMxLDSTAM_simm */
618 
        /* adm_slsl
619 
          --if shift_imm == 0 then
620 
          --  shifter_operand = Rm
621 
          --  shifter_carry_out = C Flag
622 
          --else  shift_imm > 0
623 
          --  shifter_operand = Rm Logical_Shift_Left shift_imm
624 
          --  shifter_carry_out = Rm[32 - shift_imm]
625 
        */
626 
        mov r2,#0xc0000001
627 
        add r0,r1,r2,lsl #0
628 
        add r0,r1,r2,lsl #1
629 
        add r0,r1,r2,lsl #3
630 
        add r0,r1,r2,lsl #31
631 
 
632 
        /* adm_DAPRAMxLDSTAM_DAPRAMxLDSTAM_simm */
633 
        /* adm_slsr
634 
          --if shift_imm == 0 then
635 
          --  shifter_operand = 0
636 
          --  shifter_carry_out = Rm[31]
637 
          --else shift_imm > 0
638 
          --  shifter_operand = Rm Logical_Shift_Right shift_imm
639 
          --  shifter_carry_out = Rm[shift_imm - 1]
640 
        */
641 
        mov r2,#0xc0000001
642 
        add r0,r1,r2,lsr #0
643 
        add r0,r1,r2,lsr #1
644 
        add r0,r1,r2,lsr #2
645 
        add r0,r1,r2,lsr #31
646 
 
647 
        /* adm_DAPRAMxLDSTAM_DAPRAMxLDSTAM_simm */
648 
        /* adm_sasr
649 
          --if shift_imm == 0 then
650 
          --  if Rm[31] == 0 then
651 
          --    shifter_operand = 0
652 
          --    shifter_carry_out = Rm[31]
653 
          --  else  Rm[31] == 1
654 
          --    shifter_operand = 0xFFFFFFFF
655 
          --    shifter_carry_out = Rm[31]
656 
          --else  shift_imm > 0
657 
          --  shifter_operand = Rm Arithmetic_Shift_Right
658 
          --  shifter_carry_out = Rm[shift_imm - 1]
659 
        */
660 
        mov r2,#0xc0000001
661 
        add r0,r1,r2,asr #1
662 
        add r0,r1,r2,asr #2
663 
        add r0,r1,r2,asr #31
664 
        mov r2,#0xc0000001
665 
        add r0,r1,r2,asr #0
666 
        mov r2,#0x40000001
667 
        add r0,r1,r2,asr #0
668 
 
669 
        /* adm_DAPRAMxLDSTAM_DAPRAMxLDSTAM_simm */
670 
        /* adm_sror
671 
          --if shift_imm == 0 then
672 
          --  adm_srrx case
673 
          --else shift_imm > 0
674 
          --  shifter_operand = Rm Rotate_Right shift_imm
675 
          --  shifter_carry_out = Rm[shift_imm - 1]
676 
        */
677 
        mov r2,#0xc0000001
678 
        add r0,r1,r2,ror #0
679 
        add r0,r1,r2,ror #1
680 
        add r0,r1,r2,ror #3
681 
        add r0,r1,r2,ror #31
682 
 
683 
        /* adm_DAPRAMxLDSTAM_DAPRAMxLDSTAM_simm */
684 
        /* adm_srrx
685 
          --shifter_operand = (C Flag Logical_Shift_Left 31) OR (Rm Logical_Shift_Right 1)
686 
          --shifter_carry_out = Rm[0]
687 
        */
688 
        mov r2,#0xc0000001
689 
        add r0,r1,r2,rrx
690 
        add r0,r1,r2,rrx
691 
 
692 
 
693 
 
694 
 
695 
 
696 
 
697 
 
698 
        /* coprocessor */
699 
        mrc 15,1,r0,cr1,cr0
700 
        orr r0,r0,#0x00000001
701 
        mcr 15,0,r0,cr1,cr0
702 
 
703 
 
704 
 
705 
 
706 
 
707 
 
708 
 
709 
 
710 
 
711 
 
712 
 
713 
 
714 
 
715 
 
716 
 
717 
 
718 
 
719 
 
720 
 
721 
 
722 
 
723 
 
724 
                nop
725 
 
726 
        mov r0,   #0x00810000
727 
        orr r0,r0,#0x0000000f
728 
        mov r1,   #0x80000014
729 
        str r0,[r1]
730 
 
731 
        mov r0,   #0x04000000
732 
        orr r0,r0,#0x00080000
733 
        orr r0,r0,#0x00000300
734 
        mov r1,   #0x80000000
735 
        str r0,[r1]
736 
        mov r0,   #0xd5000000
737 
        orr r0,r0,#0x00380000
738 
        orr r0,r0,#0x00004800
739 
        orr r0,r0,#0x00000030
740 
        mov r1,   #0x80000000
741 
        orr r1,r1,#0x00000004
742 
        str r0,[r1]
743 
        mov r0,   #0x000f0000
744 
        mov r1,   #0x80000000
745 
        orr r1,r1,#0x00000008
746 
        str r0,[r1]
747 
 
748 
 
749 
        mov r0,#0x40000000
750 
        mov r7,#0x12
751 
        mov r1,#0x11
752 
        mov r2,#0x12
753 
        /*str r2,[r1,r2]
754 
        nop*/
755 
        nop
756 
        str r7,[r0]
757 
        nop
758 
        ldr r7,[r0]
759 
Label:
760 
        nop
761 
        stmia r0,{r1,r2}
762 
        nop
763 
        ldmia r0,{r3,r4}
764 
        b Label
765 
 
766 
        /* # add, lock r0 */
767 
        adds r0,r0,r1  ; /* reg */
768 
        /* r0 = 3 */
769 
        /*adds r0,r1,r2,lsl #3*/  ; /* lsl imm */
770 
        /* r0 = 1 + (2 * 2^3) = 5 */
771 
 
772 
        mov r0,#3
773 
        adds r0,r1,r2,lsl r0  ; /* lsl reg */
774 
        /* r0 = 1 + (2 * 2^3) = 5 */
775 
        adds r0,r1,r4,lsr #1  ; /* lsr imm */
776 
        /* r0 = 1 + (4 / 2) = 3 */
777 
        adds r0,r1,r4,lsr r1  ; /* lsr reg */
778 
        /* r0 = 1 + (4 / 2) = 3 */
779 
        adds r0,r1,r7,asr #1  ; /* asr imm */
780 
        /* r0 = 0 */
781 
        adds r0,r1,r7,asr r1  ; /* asr reg */
782 
        /* r0 = 0 */
783 
        adds  r0,r1,r8,ror r2  ; /* ror reg */
784 
        /* r0 = 0x3c3c3c3c + 1 */
785 
        adds  r0,r1,r8,rrx     ; /* ror reg */
786 
        /* r0 = 0x78787878 + 1 */
787 
 
788 
 
789 
        /* # addc */
790 
        addcs r0,r1,r2  ; /* reg */
791 
 
792 
        /* # and */
793 
        ands r0,r1,r2  ; ; /* reg */
794 
 
795 
        /* # bic */
796 
        bic r0,r1,r2
797 
 
798 
        /* # cmn */
799 
 
800 
        ; /* # cmp */
801 
 
802 
        ; /* # eor */
803 
 
804 
        ; /* # mov */
805 
 
806 
        ; /* # mvn */
807 
 
808 
        ; /* # orr */
809 
        orr r0,r1,r2
810 
 
811 
        ; /* # rsb */
812 
 
813 
        ; /* # rsc */
814 
 
815 
        ; /* # sbc */
816 
        sbc r0,r1,r2
817 
 
818 
        ; /* # sub */
819 
        sub r0,r1,r2
820 
 
821 
        ; /* # teq */
822 
 
823 
        ; /* # tst */
824 
 
825 
 
826 
 
827 
        mul  r0,r1,r2
828 
 
829 
        mul  r0,r3,r4
830 
 
831 
 
832 
 
833 
        ; /* # load store */
834 
        ldrb r0,[r1], #4          ; /* addr word :       r1, r1 = r1 + 4 */
835 
 
836 
 
837 
        ldr r0,[r0]              ; /* addr word : r0 */
838 
        ldr r0,[r1,#4]           ; /* addr word : r3 + 4 */
839 
        ldr r0,[r1,#-4]          ; /* addr word : r3 + -4 */
840 
        str r0,[r1,#0x100]       ; /* addr word : r1 + 0x100 */
841 
 
842 
        ldrb r0,[r1]             ; /* addr byte :        r1 */
843 
        ldrb r0,[r1,#3]          ; /* addr byte :        r1 + 3 */
844 
        strb r4,[r1,#0x200]      ; /* addr byte :        r1 + 0x200 */
845 
 
846 
        ldr r0,[r1,r2]           ; /* addr word :        r1 + r2 */
847 
        strb r0,[r1,-r2]         ; /* addr byte :        r1 - r2 */
848 
 
849 
        ldr r0,[r1,r2,lsl #2]    ; /* addr word :        r1 + (r2 * 4) */
850 
        ldr r0,[r1,#4]!          ; /* addr word :        r1 + 4, write back */
851 
        strb r0,[r1,#-1]!        ; /* addr byte :        r1 - 1, write back */
852 
 
853 
 
854 
        ldr r0,[r1], #4          ; /* addr word :        r1, r1 = r1 + 4 */
855 
        str r0,[r1], #8          ; /* addr word :        r1, r1 = r1 + 8 */
856 
 
857 
        ldr r0,[pc,#40]          ; /* addr word :        pc + 0x40 = . + 8 + 0x40 */
858 
 
859 
        ldr r0,[r1], r2          ; /* addr word :        r1, r1 = r1 + r2  */
860 
 
861 
        /* miscelanous */
862 
        ldrh r1,[r0]             ; /* addr hword :       r0 */
863 
        ldrh r0,[r1,#2]          ; /* addr hword :       r1 + 2 */
864 
        ldrh r0,[r1,#-16]        ; /* addr hword :       r1 - 16 */
865 
        strh r0,[r1,#0x80]       ; /* addr hword :       r1 + 0x80 */
866 
 
867 
        ldrsh r0,[r1]            ; /* addr hword :       r1 (signed extend) */
868 
        ldrsb r0,[r1,#3]         ; /* addr byte :       r1 + 3 (signed extend) */
869 
        ldrsb r0,[r1,#0xc1]       ; /* addr byte :      r1 + 0xc1 (signed extend) */
870 
 
871 
        ldrh r0,[r1,r2]          ; /* addr hword :       r1 + r2
872 
        strh r0,[r1,-r2]         ; /* addr hword :       r1 - r2
873 
 
874 
        ldrsh r0,[r1,#2]         ; /* addr hword : r1 + 2 (signed extend */
875 
 
876 
 
877 
 
878 
 
879 
 
880 
 
881 
 
882 
 
883 
 
884 
 
885 
 
886 
 
887 
                /*
888 
         * msr
889 
         * -- msr CPSR_[cxsf],#
890 
         * -- msr CPSR_[cxsf],
891 
         * -- msr SPSR_[cxsf],#
892 
         * -- msr SPSR_[cxsf],
893 
         */
894 
        mov r13,#0x13 /* svc */
895 
        mov r8,#0xaa
896 
 
897 
        msr CPSR_c,#0x17 /* abort */
898 
        mov r13,#0x17
899 
        mov r8,#0xaa
900 
 
901 
        msr CPSR_c,#0x1b /* undefined */
902 
        mov r13,#0x1b
903 
        mov r8,#0xaa
904 
 
905 
        msr CPSR_c,#0x12 /* irq */
906 
        mov r13,#0x12
907 
        mov r8,#0xaa
908 
 
909 
        msr CPSR_c,#0x11 /* fiq */
910 
        mov r13,#0x11
911 
        mov r8,#0x11
912 
        mov r12,#0x11
913 
 
914 
 
915 
        msr CPSR_c,#0x1f /* sys */
916 
        mov r13,#0x1f
917 
 
918 
 
919 
        /* read in sys */
920 
        msr CPSR_c,#0x1f
921 
        mov r1,r13
922 
        mov r1,r8
923 
 
924 
        /* read in abort */
925 
        msr CPSR_c,#0x17
926 
        mov r1,r13
927 
        mov r1,r8
928 
 
929 
        /* read in svc */
930 
        msr CPSR_c,#0x13
931 
        mov r1,r13
932 
        mov r1,r8
933 
 
934 
        /* read in irq */
935 
        msr CPSR_c,#0x12
936 
        mov r1,r13
937 
        mov r1,r8
938 
 
939 
        /* read in fiq */
940 
        msr CPSR_c,#0x11
941 
        mov r1,r13
942 
        mov r1,r8
943 
 
944 
        /* read in undef */
945 
        msr CPSR_c,#0x1b
946 
        mov r1,r13
947 
        mov r1,r8
948 
 
949 
 
950 
 
951 
 
952 
 
953 
 
954 
 
955 
 
956 
        /*
957 
         * msr
958 
         * -- msr CPSR_[cxsf],#
959 
         * -- msr CPSR_[cxsf],
960 
         * -- msr SPSR_[cxsf],#
961 
         * -- msr SPSR_[cxsf],
962 
         */
963 
        mov r13,#0x13 /* svc */
964 
        msr SPSR_c,#0x1 /* svc */
965 
 
966 
        msr CPSR_c,#0x17 /* abort */
967 
        msr SPSR_c,#0x2 /* abort */
968 
 
969 
        msr CPSR_c,#0x1b /* undefined */
970 
        msr SPSR_c,#0x3 /* undefined */
971 
 
972 
        msr CPSR_c,#0x12 /* irq */
973 
        msr SPSR_c,#0x4 /* irq*/
974 
 
975 
        msr CPSR_c,#0x11 /* fiq */
976 
        msr SPSR_c,#0x5 /* fiq */
977 
 
978 
        msr CPSR_c,#0x1f /* sys */
979 
        msr SPSR_c,#0x6 /* sys */
980 
 
981 
        mrs r0,SPSR /* sys */
982 
 
983 
        msr CPSR_c,#0x11 /* fiq */
984 
        mrs r0,SPSR /* fiq : 0x5 */
985 
 
986 
        msr CPSR_c,#0x12 /* irq */
987 
        mrs r0,SPSR /* irq : 0x4 */
988 
 
989 
        msr CPSR_c,#0x1b /* undefined */
990 
        mrs r0,SPSR /* undefined : 0x3 */
991 
 
992 
        msr CPSR_c,#0x17 /* abort */
993 
        mrs r0,SPSR /* abort : 0x2 */
994 
 
995 
        msr CPSR_c,#0x13 /* svc */
996 
        mrs r0,SPSR /* svc : 0x1 */
997 
 
998 
 
999 
 
1000 
 
1001 
 
1002 
 
1003 
 
1004 
 
1005 
 
1006 
 
1007 
 
1008 
 
1009 
 
1010 
 
1011 
 
1012 
 
1013 
 
1014 
 
1015 
 
1016 
 
1017 
 
1018 
 
1019 
 
1020 
                mov r0,   #0x40000000
1021 
        mov r1,   #0x1
1022 
        ldr r1,[r0]
1023 
        mov r1,   #0x2
1024 
 
1025 
 
1026 
        mov r1,#8
1027 
        sub r1,r1,r1
1028 
        bne loop5
1029 
        beq loop4
1030 
 
1031 
 
1032 
        swi 10
1033 
 
1034 
loop4:  mov r1,#10
1035 
loop5:  mov r1,#10
1036 
 
1037 
                        mov r1,pc
1038 
        sub r1,r1,#8
1039 
        mov r0,#0x40000000
1040 
        str r1,[r0]
1041 
loop3:  ldr pc,[r0]
1042 
        nop
1043 
        nop
1044 
        nop
1045 
        nop
1046 
        nop
1047 
        nop
1048 
        nop
1049 
        nop
1050 
        nop
1051 
        nop
1052 
 

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