Subversion Repositories core_arm

# vsim tbench

# Loading c:/Modeltech_5.4e/win32/../std.standard

# Loading c:/Modeltech_5.4e/win32/../ieee.std_logic_1164(body)

# Loading work.tbench_comp

# Loading c:/Modeltech_5.4e/win32/../ieee.std_logic_arith(body)

# Loading work.leon_target

# Loading work.leon_device

# Loading c:/Modeltech_5.4e/win32/../std.textio(body)

# Loading work.leon_config

# Loading work.debug(body)

# Loading work.mmuconfig

# Loading work.sparcv8

# Loading work.leon_iface

# Loading work.core_config

# Loading work.corelib

# Loading work.amba

# Loading work.peri_serial_comp

# Loading work.peri_io_comp

# Loading work.peri_mem_comp

# Loading work.core_comp

# Loading work.tbenchmem_comp

# Loading work.tbench

# Loading work.tbench_config(behav)

# Loading work.memdef(body)

# Loading work.config

# Loading work.tech_map

# Loading work.ctrl_comp

# Loading c:/Modeltech_5.4e/win32/../ieee.std_logic_unsigned(body)

# Loading work.macro(body)

# Loading work.mti_pkg(body)

# Loading work.tbench_gen(behav)

# Loading work.bus_comp

# Loading work.cache_config

# Loading work.int(body)

# Loading work.gencmem_lib(body)

# Loading work.gendc_lib(body)

# Loading work.genic_lib(body)

# Loading work.genwb_lib

# Loading work.cache_comp

# Loading work.armpmodel(body)

# Loading work.armshiefter(body)

# Loading work.armdecode(body)

# Loading work.armpctrl(body)

# Loading work.arm_comp

# Loading work.tech_generic

# Loading work.tech_virtex

# Loading work.tech_virtex2

# Loading work.tech_atc18

# Loading work.tech_atc25

# Loading work.tech_atc35

# Loading work.tech_fs90

# Loading work.tech_umc18

# Loading work.tech_tsmc25

# Loading work.core(rtl)

# Loading work.peri_mem_config

# Loading work.ctrl_config

# Loading work.log(body)

# Loading work.soc_gen(rtl)

# Loading work.ahbarb(rtl)

# Loading work.apbmst(rtl)

# Loading work.armcoproc(body)

# Loading work.armcp_comp

# Loading work.arm_proc(rtl)

# Loading work.armdebug(body)

# Loading work.armcmd(body)

# Loading work.armldst(body)

# Loading work.armcmd_comp

# Loading work.armctrl(body)

# Loading work.armsctrl(body)

# Loading work.armiu(rtl)

# Loading work.armiu_imstg(rtl)

# Loading work.armiu_festg(rtl)

# Loading work.armiu_destg(rtl)

# Loading work.armiu_drstg(rtl)

# Loading work.armcmd_al(rtl)

# Loading work.armcmd_sr(rtl)

# Loading work.armcmd_ld(rtl)

# Loading work.armcmd_st(rtl)

# Loading work.armcmd_lm(rtl)

# Loading work.armcmd_sm(rtl)

# Loading work.armcmd_sw(rtl)

# Loading work.armcmd_cr(rtl)

# Loading work.armcmd_cl(rtl)

# Loading work.armcmd_cs(rtl)

# Loading work.armcmd_bl(rtl)

# Loading work.tech_proasic

# Loading work.tech_axcel

# Loading work.armiu_rrstg(rtl)

# Loading work.tech_atc18_syn

# Loading work.tech_atc25_syn

# Loading work.tech_atc35_syn

# Loading work.tech_fs90_syn

# Loading work.tech_umc18_syn

# Loading work.tech_tsmc25_syn

# Loading work.regfile_iu(rtl)

# Loading work.virtex2_complib

# Loading work.virtex2_regfile(behav)

# Loading work.virtex2_dpram(behav)

# Loading work.ramb16_s36_s36(behav)

# Loading work.ram16_sx_sx(behav)

# Loading work.armiu_rsstg(rtl)

# Loading work.armiu_exstg(rtl)

# Loading work.armiu_dmstg(rtl)

# Loading work.armiu_mestg(rtl)

# Loading work.armiu_wrstg(rtl)

# Loading work.armcp_sctrl(rtl)

# Loading work.setrepl_lib(body)

# Loading work.arith_cnt_comp

# Loading work.armcache(rtl)

# Loading work.genic(rtl)

# Loading work.gendc(rtl)

# Loading work.arith_cnt8(rtl)

# Loading work.setrepl(rtl)

# Loading work.genwb(rtl)

# Loading work.genwbfifo(rtl)

# Loading work.gencmem(rtl)

# Loading work.virtex_complib

# Loading work.syncram(behav)

# Loading work.virtex2_syncram(behav)

# Loading work.ramb16_s36(behav)

# Loading work.generic_syncram(behavioral)

# Loading work.ahbmst_mp(rtl)

# Loading work.mctrl(rtl)

# Loading work.sdmctrl(rtl)

# Loading work.timers(rtl)

# Loading work.irqctrl(rtl)

# Loading work.clkgen(rtl)

# Loading work.generic_clkgen(rtl)

# Loading work.smpad(rtl)

# Loading work.gensmpad(rtl)

# Loading work.rstgen(rtl)

# Loading work.outpad(rtl)

# Loading work.genoutpad(rtl)

# Loading work.iopad(rtl)

# Loading work.geniopad(rtl)

# Loading work.inpad(rtl)

# Loading work.geninpad(rtl)

# Loading work.smiopad(rtl)

# Loading work.iram(behavioral)

# Loading work.mt48lc16m16a2(behave)

view wave

# .wave

do vsim/sctrl

write format wave -window .wave C:/cygwin/home/eiselekd/vhdl_0.8/vsim/sctrl

write format wave -window .wave C:/cygwin/home/eiselekd/vhdl_0.8/vsim/sctrl

view atm

# Bad window name: atm

view vsim/arm

# Bad window name: vsim/arm

do vsim/arm

run 10000

# Core generic testbench

# 32 kbyte 32-bit rom, 0-ws

# 2x128 kbyte 32-bit ram, 2x64 Mbyte SDRAM

#