URL https://opencores.org/ocsvn/core_arm/core_arm/trunk

Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [vhdl/] [.dep] - Blame information for rev 5

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ambacomp=trans
fpulib=trans
fp=exclude
fp1eu=exclude
fpu_core=exclude
core_comp=trans
ctrl_comp=trans
peri_serial_comp=trans
peri_io_comp=trans
peri_mem_comp=trans
bus_comp=trans
arm_comp=trans
armcp_comp=trans
armcmd_comp=trans
cache_comp=trans
tbenchmem_comp=trans
tbench_comp=trans
tbench_proc_comp=trans
arith_cnt_comp=trans

Line No.	Rev	Author	Line
1	2	tarookumic	`ambacomp=trans`
2			`fpulib=trans`
3			`fp=exclude`
4			`fp1eu=exclude`
5			`fpu_core=exclude`
6			`core_comp=trans`
7			`ctrl_comp=trans`
8			`peri_serial_comp=trans`
9			`peri_io_comp=trans`
10			`peri_mem_comp=trans`
11			`bus_comp=trans`
12			`arm_comp=trans`
13			`armcp_comp=trans`
14			`armcmd_comp=trans`
15			`cache_comp=trans`
16			`tbenchmem_comp=trans`
17			`tbench_comp=trans`
18			`tbench_proc_comp=trans`
19			`arith_cnt_comp=trans`

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Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [vhdl/] [.dep] - Blame information for rev 5