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https://opencores.org/ocsvn/core_arm/core_arm/trunk
[/] [core_arm/] [trunk/] [vhdl/] [Makefile] - Blame information for rev 4
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tarookumic |
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targets = sim
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sim_target =
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sim_files =
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sim_hostcompile =
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sim_subdirs = mem/cache/c_model peripherals/mem/c_model bus/c_model
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