URL https://opencores.org/ocsvn/core_arm/core_arm/trunk

Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [vhdl/] [Makefile] - Blame information for rev 5

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targets          = sim
 
sim_target       =
sim_files        =
sim_hostcompile  =
sim_subdirs      = mem/cache/c_model peripherals/mem/c_model bus/c_model
 
 

Line No.	Rev	Author	Line
1	2	tarookumic
2			`targets = sim`
3
4			`sim_target =`
5			`sim_files =`
6			`sim_hostcompile =`
7			`sim_subdirs = mem/cache/c_model peripherals/mem/c_model bus/c_model`
8
9

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Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [vhdl/] [Makefile] - Blame information for rev 5