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[/] [core_arm/] [trunk/] [vhdl/] [arm/] [armiu_drstg.vhd] - Blame information for rev 4

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Line No. Rev Author Line
1 2 tarookumic 
-- $(lic)
2 
-- $(help_generic)
3 
-- $(help_local)
4 
 
5 
library ieee;
6 
use ieee.std_logic_1164.all;
7 
use work.int.all;
8 
use work.memdef.all;
9 
use work.armdecode.all;
10 
use work.armshiefter.all;
11 
use work.armpmodel.all;
12 
use work.armdebug.all;
13 
use work.armpctrl.all;
14 
use work.armcmd.all;
15 
use work.armldst.all;
16 
use work.armcmd_comp.all;
17 
use work.arm_comp.all;
18 
 
19 
entity armiu_drstg is
20 
  port (
21 
    rst     : in  std_logic;
22 
    clk     : in  std_logic;
23 
    i       : in  armiu_drstg_typ_in;
24 
    o       : out armiu_drstg_typ_out
25 
    );
26 
end armiu_drstg;
27 
 
28 
architecture rtl of armiu_drstg is
29 
 
30 
  type armiu_drstg_tmp_type is record
31 
    o       : armiu_drstg_typ_out;
32 
    cmdali  : armcmd_al_typ_in;
33 
    cmdsri  : armcmd_sr_typ_in;
34 
    cmdldi  : armcmd_ld_typ_in;
35 
    cmdsti  : armcmd_st_typ_in;
36 
    cmdlmi  : armcmd_lm_typ_in;
37 
    cmdsmi  : armcmd_sm_typ_in;
38 
    cmdswi  : armcmd_sw_typ_in;
39 
    cmdcri  : armcmd_cr_typ_in;
40 
    cmdcli  : armcmd_cl_typ_in;
41 
    cmdcsi  : armcmd_cs_typ_in;
42 
    cmdbli  : armcmd_bl_typ_in;
43 
 
44 
    ctrli : acm_ctrlin;
45 
    ctrlo : acm_ctrlout;
46 
    pctrl, pctrl_bypass : apc_pctrl;
47 
 
48 
    commit : std_logic;
49 
    insn : std_logic_vector(31 downto 0);
50 
    trap   : apm_trapctrl;
51 
    nextmicro, mem : std_logic;
52 
    micro : apc_micro;
53 
    am : ade_amode;
54 
 
55 
    r1_src, r2_src : acm_regsrc;
56 
    rd_src : acm_rdsrc;
57 
 
58 
    rn, rm, rd, rs, rlink, rpc : std_logic_vector(APM_REG_U downto APM_REG_D);
59 
    nr : std_logic_vector(APM_REG_U downto APM_REG_D);
60 
    nr_i : integer;
61 
    nr_c : std_logic;
62 
    startoff, endoff, incval : std_logic_vector(31 downto 0);
63 
    m1, m2, md: std_logic_vector(APM_REG_U downto APM_REG_D);
64 
    m1_valid, m2_valid: std_logic;
65 
    rr1, rr2, rrd: std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
66 
    rmode : std_logic_vector(4 downto 0);
67 
 
68 
  end record;
69 
  type armiu_drstg_reg_type is record
70 
    cnt : std_logic_vector(ACM_CNT_SZ-1 downto 0);
71 
    reglist : std_logic_vector(APM_REGLIST_SZ-1 downto 0);
72 
  end record;
73 
  type armiu_drstg_dbg_type is record
74 
     dummy : std_logic;
75 
     -- pragma translate_off
76 
     dbg : armiu_drstg_tmp_type;
77 
     dbgpmode : adg_dbgpmode;
78 
     dbgrmode : adg_dbgpmode;
79 
     -- pragma translate_on
80 
  end record;
81 
  signal r, c       : armiu_drstg_reg_type;
82 
  signal rdbg, cdbg : armiu_drstg_dbg_type;
83 
 
84 
  signal cmdali : armcmd_al_typ_in;
85 
  signal cmdalo : armcmd_al_typ_out;
86 
  signal cmdsri : armcmd_sr_typ_in;
87 
  signal cmdsro : armcmd_sr_typ_out;
88 
  signal cmdldi : armcmd_ld_typ_in;
89 
  signal cmdldo : armcmd_ld_typ_out;
90 
  signal cmdsti : armcmd_st_typ_in;
91 
  signal cmdsto : armcmd_st_typ_out;
92 
  signal cmdlmi : armcmd_lm_typ_in;
93 
  signal cmdlmo : armcmd_lm_typ_out;
94 
  signal cmdsmi : armcmd_sm_typ_in;
95 
  signal cmdsmo : armcmd_sm_typ_out;
96 
  signal cmdswi : armcmd_sw_typ_in;
97 
  signal cmdswo : armcmd_sw_typ_out;
98 
  signal cmdcri : armcmd_cr_typ_in;
99 
  signal cmdcro : armcmd_cr_typ_out;
100 
  signal cmdcli : armcmd_cl_typ_in;
101 
  signal cmdcso : armcmd_cs_typ_out;
102 
  signal cmdcsi : armcmd_cs_typ_in;
103 
  signal cmdclo : armcmd_cl_typ_out;
104 
  signal cmdbli : armcmd_bl_typ_in;
105 
  signal cmdblo : armcmd_bl_typ_out;
106 
 
107 
begin
108 
 
109 
  p0: process (clk, rst, r, i,
110 
               cmdalo, cmdsro, cmdldo, cmdsto, cmdlmo, cmdsmo, cmdswo,
111 
               cmdcro, cmdclo, cmdcso, cmdblo )
112 
    variable v    : armiu_drstg_reg_type;
113 
    variable t    : armiu_drstg_tmp_type;
114 
    variable vdbg : armiu_drstg_dbg_type;
115 
  begin
116 
 
117 
    -- $(init(t:armiu_drstg_tmp_type))
118 
    -- $(init-automatically-generated-for-synthesis:(t:armiu_drstg_tmp_type))
119 
    t.o.nextinsn_v := '0';
120 
    t.o.toRR_micro_v.pctrl.insn.pc_8 := (others => '0');
121 
    t.o.toRR_micro_v.pctrl.insn.insn := (others => '0');
122 
    t.o.toRR_micro_v.pctrl.insn.insntyp := ade_typmem;
123 
    t.o.toRR_micro_v.pctrl.insn.decinsn := type_arm_invalid;
124 
    t.o.toRR_micro_v.pctrl.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
125 
    t.o.toRR_micro_v.pctrl.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
126 
    t.o.toRR_micro_v.pctrl.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
127 
    t.o.toRR_micro_v.pctrl.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
128 
    t.o.toRR_micro_v.pctrl.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
129 
    t.o.toRR_micro_v.pctrl.insn.am.LDSTAMxLSV4AM_uacc := '0';
130 
    t.o.toRR_micro_v.pctrl.insn.am.LDSTAMxLSV4AM_wb := '0';
131 
    t.o.toRR_micro_v.pctrl.insn.valid := '0';
132 
    t.o.toRR_micro_v.pctrl.insn.id := (others => '0');
133 
    t.o.toRR_micro_v.pctrl.valid := '0';
134 
    t.o.toRR_micro_v.pctrl.rr.dummy := '0';
135 
    t.o.toRR_micro_v.pctrl.rs.rsop_op1_src := apc_opsrc_through;
136 
    t.o.toRR_micro_v.pctrl.rs.rsop_op2_src := apc_opsrc_through;
137 
    t.o.toRR_micro_v.pctrl.rs.rsop_buf1_src := apc_bufsrc_none;
138 
    t.o.toRR_micro_v.pctrl.rs.rsop_buf2_src := apc_bufsrc_none;
139 
    t.o.toRR_micro_v.pctrl.rs.rsop_styp := ash_styp_none;
140 
    t.o.toRR_micro_v.pctrl.rs.rsop_sdir := ash_sdir_snone;
141 
    t.o.toRR_micro_v.pctrl.rs.rs_shieftcarryout := '0';
142 
    t.o.toRR_micro_v.pctrl.ex.exop_aluop := (others => '0');
143 
    t.o.toRR_micro_v.pctrl.ex.exop_data_src := apc_datasrc_aluout;
144 
    t.o.toRR_micro_v.pctrl.ex.exop_buf_src := apc_exbufsrc_none;
145 
    t.o.toRR_micro_v.pctrl.ex.exop_setcpsr := '0';
146 
    t.o.toRR_micro_v.pctrl.ex.ex_cpsr.ex.n := '0';
147 
    t.o.toRR_micro_v.pctrl.ex.ex_cpsr.ex.z := '0';
148 
    t.o.toRR_micro_v.pctrl.ex.ex_cpsr.ex.c := '0';
149 
    t.o.toRR_micro_v.pctrl.ex.ex_cpsr.ex.v := '0';
150 
    t.o.toRR_micro_v.pctrl.ex.ex_cpsr.wr.i := '0';
151 
    t.o.toRR_micro_v.pctrl.ex.ex_cpsr.wr.f := '0';
152 
    t.o.toRR_micro_v.pctrl.ex.ex_cpsr.wr.t := '0';
153 
    t.o.toRR_micro_v.pctrl.ex.ex_cpsr.wr.mode := (others => '0');
154 
    t.o.toRR_micro_v.pctrl.dm.dummy := '0';
155 
    t.o.toRR_micro_v.pctrl.me.meop_enable := '0';
156 
    t.o.toRR_micro_v.pctrl.me.meop_param.size := lmd_word;
157 
    t.o.toRR_micro_v.pctrl.me.meop_param.read := '0';
158 
    t.o.toRR_micro_v.pctrl.me.meop_param.lock := '0';
159 
    t.o.toRR_micro_v.pctrl.me.meop_param.writedata := '0';
160 
    t.o.toRR_micro_v.pctrl.me.meop_param.addrin := '0';
161 
    t.o.toRR_micro_v.pctrl.me.meop_param.signed := '0';
162 
    t.o.toRR_micro_v.pctrl.me.mexc := '0';
163 
    t.o.toRR_micro_v.pctrl.wr.wrop_rd := (others => '0');
164 
    t.o.toRR_micro_v.pctrl.wr.wrop_rdvalid := '0';
165 
    t.o.toRR_micro_v.pctrl.wr.wrop_setspsr := '0';
166 
    t.o.toRR_micro_v.pctrl.wr.wrop_trap.traptype := apm_trap_reset;
167 
    t.o.toRR_micro_v.pctrl.wr.wrop_trap.trap := '0';
168 
    t.o.toRR_micro_v.pctrl.data1 := (others => '0');
169 
    t.o.toRR_micro_v.pctrl.data2 := (others => '0');
170 
    t.o.toRR_micro_v.valid := '0';
171 
    t.o.toRR_micro_v.r1 := (others => '0');
172 
    t.o.toRR_micro_v.r2 := (others => '0');
173 
    t.o.toRR_micro_v.r1_valid := '0';
174 
    t.o.toRR_micro_v.r2_valid := '0';
175 
    t.o.id := (others => '0');
176 
    t.cmdali.ctrli.cnt := (others => '0');
177 
    t.cmdali.ctrli.insn.pc_8 := (others => '0');
178 
    t.cmdali.ctrli.insn.insn := (others => '0');
179 
    t.cmdali.ctrli.insn.insntyp := ade_typmem;
180 
    t.cmdali.ctrli.insn.decinsn := type_arm_invalid;
181 
    t.cmdali.ctrli.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
182 
    t.cmdali.ctrli.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
183 
    t.cmdali.ctrli.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
184 
    t.cmdali.ctrli.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
185 
    t.cmdali.ctrli.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
186 
    t.cmdali.ctrli.insn.am.LDSTAMxLSV4AM_uacc := '0';
187 
    t.cmdali.ctrli.insn.am.LDSTAMxLSV4AM_wb := '0';
188 
    t.cmdali.ctrli.insn.valid := '0';
189 
    t.cmdali.ctrli.insn.id := (others => '0');
190 
    t.cmdali.ctrli.ctrlo.nextinsn := '0';
191 
    t.cmdali.ctrli.ctrlo.nextcnt := '0';
192 
    t.cmdali.ctrli.ctrlo.hold := '0';
193 
    t.cmdsri.ctrli.cnt := (others => '0');
194 
    t.cmdsri.ctrli.insn.pc_8 := (others => '0');
195 
    t.cmdsri.ctrli.insn.insn := (others => '0');
196 
    t.cmdsri.ctrli.insn.insntyp := ade_typmem;
197 
    t.cmdsri.ctrli.insn.decinsn := type_arm_invalid;
198 
    t.cmdsri.ctrli.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
199 
    t.cmdsri.ctrli.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
200 
    t.cmdsri.ctrli.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
201 
    t.cmdsri.ctrli.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
202 
    t.cmdsri.ctrli.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
203 
    t.cmdsri.ctrli.insn.am.LDSTAMxLSV4AM_uacc := '0';
204 
    t.cmdsri.ctrli.insn.am.LDSTAMxLSV4AM_wb := '0';
205 
    t.cmdsri.ctrli.insn.valid := '0';
206 
    t.cmdsri.ctrli.insn.id := (others => '0');
207 
    t.cmdsri.ctrli.ctrlo.nextinsn := '0';
208 
    t.cmdsri.ctrli.ctrlo.nextcnt := '0';
209 
    t.cmdsri.ctrli.ctrlo.hold := '0';
210 
    t.cmdsri.deid := (others => '0');
211 
    t.cmdsri.exid := (others => '0');
212 
    t.cmdsri.exvalid := '0';
213 
    t.cmdsri.wrid := (others => '0');
214 
    t.cmdsri.wrvalid := '0';
215 
    t.cmdldi.ctrli.cnt := (others => '0');
216 
    t.cmdldi.ctrli.insn.pc_8 := (others => '0');
217 
    t.cmdldi.ctrli.insn.insn := (others => '0');
218 
    t.cmdldi.ctrli.insn.insntyp := ade_typmem;
219 
    t.cmdldi.ctrli.insn.decinsn := type_arm_invalid;
220 
    t.cmdldi.ctrli.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
221 
    t.cmdldi.ctrli.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
222 
    t.cmdldi.ctrli.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
223 
    t.cmdldi.ctrli.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
224 
    t.cmdldi.ctrli.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
225 
    t.cmdldi.ctrli.insn.am.LDSTAMxLSV4AM_uacc := '0';
226 
    t.cmdldi.ctrli.insn.am.LDSTAMxLSV4AM_wb := '0';
227 
    t.cmdldi.ctrli.insn.valid := '0';
228 
    t.cmdldi.ctrli.insn.id := (others => '0');
229 
    t.cmdldi.ctrli.ctrlo.nextinsn := '0';
230 
    t.cmdldi.ctrli.ctrlo.nextcnt := '0';
231 
    t.cmdldi.ctrli.ctrlo.hold := '0';
232 
    t.cmdldi.ctrlmemo.data1 := (others => '0');
233 
    t.cmdldi.ctrlmemo.data2 := (others => '0');
234 
    t.cmdldi.ctrlmemo.r1_src := acm_none;
235 
    t.cmdldi.ctrlmemo.r2_src := acm_none;
236 
    t.cmdldi.ctrlmemo.rd_src := acm_rdnone;
237 
    t.cmdldi.ctrlmemo.rsop_op1_src := apc_opsrc_through;
238 
    t.cmdldi.ctrlmemo.rsop_op2_src := apc_opsrc_through;
239 
    t.cmdldi.ctrlmemo.rsop_buf1_src := apc_bufsrc_none;
240 
    t.cmdldi.ctrlmemo.rsop_buf2_src := apc_bufsrc_none;
241 
    t.cmdldi.ctrlmemo.exop_data_src := apc_datasrc_aluout;
242 
    t.cmdldi.ctrlmemo.exop_buf_src := apc_exbufsrc_none;
243 
    t.cmdldi.ctrlmemo.meop_param.size := lmd_word;
244 
    t.cmdldi.ctrlmemo.meop_param.read := '0';
245 
    t.cmdldi.ctrlmemo.meop_param.lock := '0';
246 
    t.cmdldi.ctrlmemo.meop_param.writedata := '0';
247 
    t.cmdldi.ctrlmemo.meop_param.addrin := '0';
248 
    t.cmdldi.ctrlmemo.meop_param.signed := '0';
249 
    t.cmdldi.ctrlmemo.meop_enable := '0';
250 
    t.cmdsti.ctrli.cnt := (others => '0');
251 
    t.cmdsti.ctrli.insn.pc_8 := (others => '0');
252 
    t.cmdsti.ctrli.insn.insn := (others => '0');
253 
    t.cmdsti.ctrli.insn.insntyp := ade_typmem;
254 
    t.cmdsti.ctrli.insn.decinsn := type_arm_invalid;
255 
    t.cmdsti.ctrli.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
256 
    t.cmdsti.ctrli.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
257 
    t.cmdsti.ctrli.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
258 
    t.cmdsti.ctrli.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
259 
    t.cmdsti.ctrli.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
260 
    t.cmdsti.ctrli.insn.am.LDSTAMxLSV4AM_uacc := '0';
261 
    t.cmdsti.ctrli.insn.am.LDSTAMxLSV4AM_wb := '0';
262 
    t.cmdsti.ctrli.insn.valid := '0';
263 
    t.cmdsti.ctrli.insn.id := (others => '0');
264 
    t.cmdsti.ctrli.ctrlo.nextinsn := '0';
265 
    t.cmdsti.ctrli.ctrlo.nextcnt := '0';
266 
    t.cmdsti.ctrli.ctrlo.hold := '0';
267 
    t.cmdsti.ctrlmemo.data1 := (others => '0');
268 
    t.cmdsti.ctrlmemo.data2 := (others => '0');
269 
    t.cmdsti.ctrlmemo.r1_src := acm_none;
270 
    t.cmdsti.ctrlmemo.r2_src := acm_none;
271 
    t.cmdsti.ctrlmemo.rd_src := acm_rdnone;
272 
    t.cmdsti.ctrlmemo.rsop_op1_src := apc_opsrc_through;
273 
    t.cmdsti.ctrlmemo.rsop_op2_src := apc_opsrc_through;
274 
    t.cmdsti.ctrlmemo.rsop_buf1_src := apc_bufsrc_none;
275 
    t.cmdsti.ctrlmemo.rsop_buf2_src := apc_bufsrc_none;
276 
    t.cmdsti.ctrlmemo.exop_data_src := apc_datasrc_aluout;
277 
    t.cmdsti.ctrlmemo.exop_buf_src := apc_exbufsrc_none;
278 
    t.cmdsti.ctrlmemo.meop_param.size := lmd_word;
279 
    t.cmdsti.ctrlmemo.meop_param.read := '0';
280 
    t.cmdsti.ctrlmemo.meop_param.lock := '0';
281 
    t.cmdsti.ctrlmemo.meop_param.writedata := '0';
282 
    t.cmdsti.ctrlmemo.meop_param.addrin := '0';
283 
    t.cmdsti.ctrlmemo.meop_param.signed := '0';
284 
    t.cmdsti.ctrlmemo.meop_enable := '0';
285 
    t.cmdlmi.ctrli.cnt := (others => '0');
286 
    t.cmdlmi.ctrli.insn.pc_8 := (others => '0');
287 
    t.cmdlmi.ctrli.insn.insn := (others => '0');
288 
    t.cmdlmi.ctrli.insn.insntyp := ade_typmem;
289 
    t.cmdlmi.ctrli.insn.decinsn := type_arm_invalid;
290 
    t.cmdlmi.ctrli.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
291 
    t.cmdlmi.ctrli.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
292 
    t.cmdlmi.ctrli.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
293 
    t.cmdlmi.ctrli.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
294 
    t.cmdlmi.ctrli.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
295 
    t.cmdlmi.ctrli.insn.am.LDSTAMxLSV4AM_uacc := '0';
296 
    t.cmdlmi.ctrli.insn.am.LDSTAMxLSV4AM_wb := '0';
297 
    t.cmdlmi.ctrli.insn.valid := '0';
298 
    t.cmdlmi.ctrli.insn.id := (others => '0');
299 
    t.cmdlmi.ctrli.ctrlo.nextinsn := '0';
300 
    t.cmdlmi.ctrli.ctrlo.nextcnt := '0';
301 
    t.cmdlmi.ctrli.ctrlo.hold := '0';
302 
    t.cmdlmi.ctrlmulti.ctrlmemo.data1 := (others => '0');
303 
    t.cmdlmi.ctrlmulti.ctrlmemo.data2 := (others => '0');
304 
    t.cmdlmi.ctrlmulti.ctrlmemo.r1_src := acm_none;
305 
    t.cmdlmi.ctrlmulti.ctrlmemo.r2_src := acm_none;
306 
    t.cmdlmi.ctrlmulti.ctrlmemo.rd_src := acm_rdnone;
307 
    t.cmdlmi.ctrlmulti.ctrlmemo.rsop_op1_src := apc_opsrc_through;
308 
    t.cmdlmi.ctrlmulti.ctrlmemo.rsop_op2_src := apc_opsrc_through;
309 
    t.cmdlmi.ctrlmulti.ctrlmemo.rsop_buf1_src := apc_bufsrc_none;
310 
    t.cmdlmi.ctrlmulti.ctrlmemo.rsop_buf2_src := apc_bufsrc_none;
311 
    t.cmdlmi.ctrlmulti.ctrlmemo.exop_data_src := apc_datasrc_aluout;
312 
    t.cmdlmi.ctrlmulti.ctrlmemo.exop_buf_src := apc_exbufsrc_none;
313 
    t.cmdlmi.ctrlmulti.ctrlmemo.meop_param.size := lmd_word;
314 
    t.cmdlmi.ctrlmulti.ctrlmemo.meop_param.read := '0';
315 
    t.cmdlmi.ctrlmulti.ctrlmemo.meop_param.lock := '0';
316 
    t.cmdlmi.ctrlmulti.ctrlmemo.meop_param.writedata := '0';
317 
    t.cmdlmi.ctrlmulti.ctrlmemo.meop_param.addrin := '0';
318 
    t.cmdlmi.ctrlmulti.ctrlmemo.meop_param.signed := '0';
319 
    t.cmdlmi.ctrlmulti.ctrlmemo.meop_enable := '0';
320 
    t.cmdlmi.ctrlmulti.ival := (others => '0');
321 
    t.cmdlmi.ctrlmulti.soff := (others => '0');
322 
    t.cmdlmi.ctrlmulti.eoff := (others => '0');
323 
    t.cmdlmi.ctrlmulti.reglist := (others => '0');
324 
    t.cmdlmi.ctrlmulti.mem := '0';
325 
    t.cmdlmi.ctrlmulti.dabort := '0';
326 
    t.cmdsmi.ctrli.cnt := (others => '0');
327 
    t.cmdsmi.ctrli.insn.pc_8 := (others => '0');
328 
    t.cmdsmi.ctrli.insn.insn := (others => '0');
329 
    t.cmdsmi.ctrli.insn.insntyp := ade_typmem;
330 
    t.cmdsmi.ctrli.insn.decinsn := type_arm_invalid;
331 
    t.cmdsmi.ctrli.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
332 
    t.cmdsmi.ctrli.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
333 
    t.cmdsmi.ctrli.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
334 
    t.cmdsmi.ctrli.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
335 
    t.cmdsmi.ctrli.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
336 
    t.cmdsmi.ctrli.insn.am.LDSTAMxLSV4AM_uacc := '0';
337 
    t.cmdsmi.ctrli.insn.am.LDSTAMxLSV4AM_wb := '0';
338 
    t.cmdsmi.ctrli.insn.valid := '0';
339 
    t.cmdsmi.ctrli.insn.id := (others => '0');
340 
    t.cmdsmi.ctrli.ctrlo.nextinsn := '0';
341 
    t.cmdsmi.ctrli.ctrlo.nextcnt := '0';
342 
    t.cmdsmi.ctrli.ctrlo.hold := '0';
343 
    t.cmdsmi.ctrlmulti.ctrlmemo.data1 := (others => '0');
344 
    t.cmdsmi.ctrlmulti.ctrlmemo.data2 := (others => '0');
345 
    t.cmdsmi.ctrlmulti.ctrlmemo.r1_src := acm_none;
346 
    t.cmdsmi.ctrlmulti.ctrlmemo.r2_src := acm_none;
347 
    t.cmdsmi.ctrlmulti.ctrlmemo.rd_src := acm_rdnone;
348 
    t.cmdsmi.ctrlmulti.ctrlmemo.rsop_op1_src := apc_opsrc_through;
349 
    t.cmdsmi.ctrlmulti.ctrlmemo.rsop_op2_src := apc_opsrc_through;
350 
    t.cmdsmi.ctrlmulti.ctrlmemo.rsop_buf1_src := apc_bufsrc_none;
351 
    t.cmdsmi.ctrlmulti.ctrlmemo.rsop_buf2_src := apc_bufsrc_none;
352 
    t.cmdsmi.ctrlmulti.ctrlmemo.exop_data_src := apc_datasrc_aluout;
353 
    t.cmdsmi.ctrlmulti.ctrlmemo.exop_buf_src := apc_exbufsrc_none;
354 
    t.cmdsmi.ctrlmulti.ctrlmemo.meop_param.size := lmd_word;
355 
    t.cmdsmi.ctrlmulti.ctrlmemo.meop_param.read := '0';
356 
    t.cmdsmi.ctrlmulti.ctrlmemo.meop_param.lock := '0';
357 
    t.cmdsmi.ctrlmulti.ctrlmemo.meop_param.writedata := '0';
358 
    t.cmdsmi.ctrlmulti.ctrlmemo.meop_param.addrin := '0';
359 
    t.cmdsmi.ctrlmulti.ctrlmemo.meop_param.signed := '0';
360 
    t.cmdsmi.ctrlmulti.ctrlmemo.meop_enable := '0';
361 
    t.cmdsmi.ctrlmulti.ival := (others => '0');
362 
    t.cmdsmi.ctrlmulti.soff := (others => '0');
363 
    t.cmdsmi.ctrlmulti.eoff := (others => '0');
364 
    t.cmdsmi.ctrlmulti.reglist := (others => '0');
365 
    t.cmdsmi.ctrlmulti.mem := '0';
366 
    t.cmdsmi.ctrlmulti.dabort := '0';
367 
    t.cmdswi.ctrli.cnt := (others => '0');
368 
    t.cmdswi.ctrli.insn.pc_8 := (others => '0');
369 
    t.cmdswi.ctrli.insn.insn := (others => '0');
370 
    t.cmdswi.ctrli.insn.insntyp := ade_typmem;
371 
    t.cmdswi.ctrli.insn.decinsn := type_arm_invalid;
372 
    t.cmdswi.ctrli.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
373 
    t.cmdswi.ctrli.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
374 
    t.cmdswi.ctrli.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
375 
    t.cmdswi.ctrli.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
376 
    t.cmdswi.ctrli.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
377 
    t.cmdswi.ctrli.insn.am.LDSTAMxLSV4AM_uacc := '0';
378 
    t.cmdswi.ctrli.insn.am.LDSTAMxLSV4AM_wb := '0';
379 
    t.cmdswi.ctrli.insn.valid := '0';
380 
    t.cmdswi.ctrli.insn.id := (others => '0');
381 
    t.cmdswi.ctrli.ctrlo.nextinsn := '0';
382 
    t.cmdswi.ctrli.ctrlo.nextcnt := '0';
383 
    t.cmdswi.ctrli.ctrlo.hold := '0';
384 
    t.cmdswi.ctrlmemo.data1 := (others => '0');
385 
    t.cmdswi.ctrlmemo.data2 := (others => '0');
386 
    t.cmdswi.ctrlmemo.r1_src := acm_none;
387 
    t.cmdswi.ctrlmemo.r2_src := acm_none;
388 
    t.cmdswi.ctrlmemo.rd_src := acm_rdnone;
389 
    t.cmdswi.ctrlmemo.rsop_op1_src := apc_opsrc_through;
390 
    t.cmdswi.ctrlmemo.rsop_op2_src := apc_opsrc_through;
391 
    t.cmdswi.ctrlmemo.rsop_buf1_src := apc_bufsrc_none;
392 
    t.cmdswi.ctrlmemo.rsop_buf2_src := apc_bufsrc_none;
393 
    t.cmdswi.ctrlmemo.exop_data_src := apc_datasrc_aluout;
394 
    t.cmdswi.ctrlmemo.exop_buf_src := apc_exbufsrc_none;
395 
    t.cmdswi.ctrlmemo.meop_param.size := lmd_word;
396 
    t.cmdswi.ctrlmemo.meop_param.read := '0';
397 
    t.cmdswi.ctrlmemo.meop_param.lock := '0';
398 
    t.cmdswi.ctrlmemo.meop_param.writedata := '0';
399 
    t.cmdswi.ctrlmemo.meop_param.addrin := '0';
400 
    t.cmdswi.ctrlmemo.meop_param.signed := '0';
401 
    t.cmdswi.ctrlmemo.meop_enable := '0';
402 
    t.cmdcri.ctrli.cnt := (others => '0');
403 
    t.cmdcri.ctrli.insn.pc_8 := (others => '0');
404 
    t.cmdcri.ctrli.insn.insn := (others => '0');
405 
    t.cmdcri.ctrli.insn.insntyp := ade_typmem;
406 
    t.cmdcri.ctrli.insn.decinsn := type_arm_invalid;
407 
    t.cmdcri.ctrli.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
408 
    t.cmdcri.ctrli.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
409 
    t.cmdcri.ctrli.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
410 
    t.cmdcri.ctrli.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
411 
    t.cmdcri.ctrli.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
412 
    t.cmdcri.ctrli.insn.am.LDSTAMxLSV4AM_uacc := '0';
413 
    t.cmdcri.ctrli.insn.am.LDSTAMxLSV4AM_wb := '0';
414 
    t.cmdcri.ctrli.insn.valid := '0';
415 
    t.cmdcri.ctrli.insn.id := (others => '0');
416 
    t.cmdcri.ctrli.ctrlo.nextinsn := '0';
417 
    t.cmdcri.ctrli.ctrlo.nextcnt := '0';
418 
    t.cmdcri.ctrli.ctrlo.hold := '0';
419 
    t.cmdcri.fromCP_busy := '0';
420 
    t.cmdcli.ctrli.cnt := (others => '0');
421 
    t.cmdcli.ctrli.insn.pc_8 := (others => '0');
422 
    t.cmdcli.ctrli.insn.insn := (others => '0');
423 
    t.cmdcli.ctrli.insn.insntyp := ade_typmem;
424 
    t.cmdcli.ctrli.insn.decinsn := type_arm_invalid;
425 
    t.cmdcli.ctrli.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
426 
    t.cmdcli.ctrli.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
427 
    t.cmdcli.ctrli.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
428 
    t.cmdcli.ctrli.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
429 
    t.cmdcli.ctrli.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
430 
    t.cmdcli.ctrli.insn.am.LDSTAMxLSV4AM_uacc := '0';
431 
    t.cmdcli.ctrli.insn.am.LDSTAMxLSV4AM_wb := '0';
432 
    t.cmdcli.ctrli.insn.valid := '0';
433 
    t.cmdcli.ctrli.insn.id := (others => '0');
434 
    t.cmdcli.ctrli.ctrlo.nextinsn := '0';
435 
    t.cmdcli.ctrli.ctrlo.nextcnt := '0';
436 
    t.cmdcli.ctrli.ctrlo.hold := '0';
437 
    t.cmdcli.ctrlmemo.data1 := (others => '0');
438 
    t.cmdcli.ctrlmemo.data2 := (others => '0');
439 
    t.cmdcli.ctrlmemo.r1_src := acm_none;
440 
    t.cmdcli.ctrlmemo.r2_src := acm_none;
441 
    t.cmdcli.ctrlmemo.rd_src := acm_rdnone;
442 
    t.cmdcli.ctrlmemo.rsop_op1_src := apc_opsrc_through;
443 
    t.cmdcli.ctrlmemo.rsop_op2_src := apc_opsrc_through;
444 
    t.cmdcli.ctrlmemo.rsop_buf1_src := apc_bufsrc_none;
445 
    t.cmdcli.ctrlmemo.rsop_buf2_src := apc_bufsrc_none;
446 
    t.cmdcli.ctrlmemo.exop_data_src := apc_datasrc_aluout;
447 
    t.cmdcli.ctrlmemo.exop_buf_src := apc_exbufsrc_none;
448 
    t.cmdcli.ctrlmemo.meop_param.size := lmd_word;
449 
    t.cmdcli.ctrlmemo.meop_param.read := '0';
450 
    t.cmdcli.ctrlmemo.meop_param.lock := '0';
451 
    t.cmdcli.ctrlmemo.meop_param.writedata := '0';
452 
    t.cmdcli.ctrlmemo.meop_param.addrin := '0';
453 
    t.cmdcli.ctrlmemo.meop_param.signed := '0';
454 
    t.cmdcli.ctrlmemo.meop_enable := '0';
455 
    t.cmdcli.fromCP_busy := '0';
456 
    t.cmdcli.fromCP_last := '0';
457 
    t.cmdcsi.ctrli.cnt := (others => '0');
458 
    t.cmdcsi.ctrli.insn.pc_8 := (others => '0');
459 
    t.cmdcsi.ctrli.insn.insn := (others => '0');
460 
    t.cmdcsi.ctrli.insn.insntyp := ade_typmem;
461 
    t.cmdcsi.ctrli.insn.decinsn := type_arm_invalid;
462 
    t.cmdcsi.ctrli.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
463 
    t.cmdcsi.ctrli.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
464 
    t.cmdcsi.ctrli.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
465 
    t.cmdcsi.ctrli.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
466 
    t.cmdcsi.ctrli.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
467 
    t.cmdcsi.ctrli.insn.am.LDSTAMxLSV4AM_uacc := '0';
468 
    t.cmdcsi.ctrli.insn.am.LDSTAMxLSV4AM_wb := '0';
469 
    t.cmdcsi.ctrli.insn.valid := '0';
470 
    t.cmdcsi.ctrli.insn.id := (others => '0');
471 
    t.cmdcsi.ctrli.ctrlo.nextinsn := '0';
472 
    t.cmdcsi.ctrli.ctrlo.nextcnt := '0';
473 
    t.cmdcsi.ctrli.ctrlo.hold := '0';
474 
    t.cmdcsi.ctrlmemo.data1 := (others => '0');
475 
    t.cmdcsi.ctrlmemo.data2 := (others => '0');
476 
    t.cmdcsi.ctrlmemo.r1_src := acm_none;
477 
    t.cmdcsi.ctrlmemo.r2_src := acm_none;
478 
    t.cmdcsi.ctrlmemo.rd_src := acm_rdnone;
479 
    t.cmdcsi.ctrlmemo.rsop_op1_src := apc_opsrc_through;
480 
    t.cmdcsi.ctrlmemo.rsop_op2_src := apc_opsrc_through;
481 
    t.cmdcsi.ctrlmemo.rsop_buf1_src := apc_bufsrc_none;
482 
    t.cmdcsi.ctrlmemo.rsop_buf2_src := apc_bufsrc_none;
483 
    t.cmdcsi.ctrlmemo.exop_data_src := apc_datasrc_aluout;
484 
    t.cmdcsi.ctrlmemo.exop_buf_src := apc_exbufsrc_none;
485 
    t.cmdcsi.ctrlmemo.meop_param.size := lmd_word;
486 
    t.cmdcsi.ctrlmemo.meop_param.read := '0';
487 
    t.cmdcsi.ctrlmemo.meop_param.lock := '0';
488 
    t.cmdcsi.ctrlmemo.meop_param.writedata := '0';
489 
    t.cmdcsi.ctrlmemo.meop_param.addrin := '0';
490 
    t.cmdcsi.ctrlmemo.meop_param.signed := '0';
491 
    t.cmdcsi.ctrlmemo.meop_enable := '0';
492 
    t.cmdcsi.fromCP_busy := '0';
493 
    t.cmdcsi.fromCP_last := '0';
494 
    t.cmdbli.ctrli.cnt := (others => '0');
495 
    t.cmdbli.ctrli.insn.pc_8 := (others => '0');
496 
    t.cmdbli.ctrli.insn.insn := (others => '0');
497 
    t.cmdbli.ctrli.insn.insntyp := ade_typmem;
498 
    t.cmdbli.ctrli.insn.decinsn := type_arm_invalid;
499 
    t.cmdbli.ctrli.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
500 
    t.cmdbli.ctrli.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
501 
    t.cmdbli.ctrli.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
502 
    t.cmdbli.ctrli.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
503 
    t.cmdbli.ctrli.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
504 
    t.cmdbli.ctrli.insn.am.LDSTAMxLSV4AM_uacc := '0';
505 
    t.cmdbli.ctrli.insn.am.LDSTAMxLSV4AM_wb := '0';
506 
    t.cmdbli.ctrli.insn.valid := '0';
507 
    t.cmdbli.ctrli.insn.id := (others => '0');
508 
    t.cmdbli.ctrli.ctrlo.nextinsn := '0';
509 
    t.cmdbli.ctrli.ctrlo.nextcnt := '0';
510 
    t.cmdbli.ctrli.ctrlo.hold := '0';
511 
    t.ctrli.cnt := (others => '0');
512 
    t.ctrli.insn.pc_8 := (others => '0');
513 
    t.ctrli.insn.insn := (others => '0');
514 
    t.ctrli.insn.insntyp := ade_typmem;
515 
    t.ctrli.insn.decinsn := type_arm_invalid;
516 
    t.ctrli.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
517 
    t.ctrli.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
518 
    t.ctrli.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
519 
    t.ctrli.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
520 
    t.ctrli.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
521 
    t.ctrli.insn.am.LDSTAMxLSV4AM_uacc := '0';
522 
    t.ctrli.insn.am.LDSTAMxLSV4AM_wb := '0';
523 
    t.ctrli.insn.valid := '0';
524 
    t.ctrli.insn.id := (others => '0');
525 
    t.ctrli.ctrlo.nextinsn := '0';
526 
    t.ctrli.ctrlo.nextcnt := '0';
527 
    t.ctrli.ctrlo.hold := '0';
528 
    t.ctrlo.nextinsn := '0';
529 
    t.ctrlo.nextcnt := '0';
530 
    t.ctrlo.hold := '0';
531 
    t.pctrl.insn.pc_8 := (others => '0');
532 
    t.pctrl.insn.insn := (others => '0');
533 
    t.pctrl.insn.insntyp := ade_typmem;
534 
    t.pctrl.insn.decinsn := type_arm_invalid;
535 
    t.pctrl.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
536 
    t.pctrl.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
537 
    t.pctrl.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
538 
    t.pctrl.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
539 
    t.pctrl.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
540 
    t.pctrl.insn.am.LDSTAMxLSV4AM_uacc := '0';
541 
    t.pctrl.insn.am.LDSTAMxLSV4AM_wb := '0';
542 
    t.pctrl.insn.valid := '0';
543 
    t.pctrl.insn.id := (others => '0');
544 
    t.pctrl.valid := '0';
545 
    t.pctrl.rr.dummy := '0';
546 
    t.pctrl.rs.rsop_op1_src := apc_opsrc_through;
547 
    t.pctrl.rs.rsop_op2_src := apc_opsrc_through;
548 
    t.pctrl.rs.rsop_buf1_src := apc_bufsrc_none;
549 
    t.pctrl.rs.rsop_buf2_src := apc_bufsrc_none;
550 
    t.pctrl.rs.rsop_styp := ash_styp_none;
551 
    t.pctrl.rs.rsop_sdir := ash_sdir_snone;
552 
    t.pctrl.rs.rs_shieftcarryout := '0';
553 
    t.pctrl.ex.exop_aluop := (others => '0');
554 
    t.pctrl.ex.exop_data_src := apc_datasrc_aluout;
555 
    t.pctrl.ex.exop_buf_src := apc_exbufsrc_none;
556 
    t.pctrl.ex.exop_setcpsr := '0';
557 
    t.pctrl.ex.ex_cpsr.ex.n := '0';
558 
    t.pctrl.ex.ex_cpsr.ex.z := '0';
559 
    t.pctrl.ex.ex_cpsr.ex.c := '0';
560 
    t.pctrl.ex.ex_cpsr.ex.v := '0';
561 
    t.pctrl.ex.ex_cpsr.wr.i := '0';
562 
    t.pctrl.ex.ex_cpsr.wr.f := '0';
563 
    t.pctrl.ex.ex_cpsr.wr.t := '0';
564 
    t.pctrl.ex.ex_cpsr.wr.mode := (others => '0');
565 
    t.pctrl.dm.dummy := '0';
566 
    t.pctrl.me.meop_enable := '0';
567 
    t.pctrl.me.meop_param.size := lmd_word;
568 
    t.pctrl.me.meop_param.read := '0';
569 
    t.pctrl.me.meop_param.lock := '0';
570 
    t.pctrl.me.meop_param.writedata := '0';
571 
    t.pctrl.me.meop_param.addrin := '0';
572 
    t.pctrl.me.meop_param.signed := '0';
573 
    t.pctrl.me.mexc := '0';
574 
    t.pctrl.wr.wrop_rd := (others => '0');
575 
    t.pctrl.wr.wrop_rdvalid := '0';
576 
    t.pctrl.wr.wrop_setspsr := '0';
577 
    t.pctrl.wr.wrop_trap.traptype := apm_trap_reset;
578 
    t.pctrl.wr.wrop_trap.trap := '0';
579 
    t.pctrl.data1 := (others => '0');
580 
    t.pctrl.data2 := (others => '0');
581 
    t.pctrl_bypass.insn.pc_8 := (others => '0');
582 
    t.pctrl_bypass.insn.insn := (others => '0');
583 
    t.pctrl_bypass.insn.insntyp := ade_typmem;
584 
    t.pctrl_bypass.insn.decinsn := type_arm_invalid;
585 
    t.pctrl_bypass.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
586 
    t.pctrl_bypass.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
587 
    t.pctrl_bypass.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
588 
    t.pctrl_bypass.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
589 
    t.pctrl_bypass.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
590 
    t.pctrl_bypass.insn.am.LDSTAMxLSV4AM_uacc := '0';
591 
    t.pctrl_bypass.insn.am.LDSTAMxLSV4AM_wb := '0';
592 
    t.pctrl_bypass.insn.valid := '0';
593 
    t.pctrl_bypass.insn.id := (others => '0');
594 
    t.pctrl_bypass.valid := '0';
595 
    t.pctrl_bypass.rr.dummy := '0';
596 
    t.pctrl_bypass.rs.rsop_op1_src := apc_opsrc_through;
597 
    t.pctrl_bypass.rs.rsop_op2_src := apc_opsrc_through;
598 
    t.pctrl_bypass.rs.rsop_buf1_src := apc_bufsrc_none;
599 
    t.pctrl_bypass.rs.rsop_buf2_src := apc_bufsrc_none;
600 
    t.pctrl_bypass.rs.rsop_styp := ash_styp_none;
601 
    t.pctrl_bypass.rs.rsop_sdir := ash_sdir_snone;
602 
    t.pctrl_bypass.rs.rs_shieftcarryout := '0';
603 
    t.pctrl_bypass.ex.exop_aluop := (others => '0');
604 
    t.pctrl_bypass.ex.exop_data_src := apc_datasrc_aluout;
605 
    t.pctrl_bypass.ex.exop_buf_src := apc_exbufsrc_none;
606 
    t.pctrl_bypass.ex.exop_setcpsr := '0';
607 
    t.pctrl_bypass.ex.ex_cpsr.ex.n := '0';
608 
    t.pctrl_bypass.ex.ex_cpsr.ex.z := '0';
609 
    t.pctrl_bypass.ex.ex_cpsr.ex.c := '0';
610 
    t.pctrl_bypass.ex.ex_cpsr.ex.v := '0';
611 
    t.pctrl_bypass.ex.ex_cpsr.wr.i := '0';
612 
    t.pctrl_bypass.ex.ex_cpsr.wr.f := '0';
613 
    t.pctrl_bypass.ex.ex_cpsr.wr.t := '0';
614 
    t.pctrl_bypass.ex.ex_cpsr.wr.mode := (others => '0');
615 
    t.pctrl_bypass.dm.dummy := '0';
616 
    t.pctrl_bypass.me.meop_enable := '0';
617 
    t.pctrl_bypass.me.meop_param.size := lmd_word;
618 
    t.pctrl_bypass.me.meop_param.read := '0';
619 
    t.pctrl_bypass.me.meop_param.lock := '0';
620 
    t.pctrl_bypass.me.meop_param.writedata := '0';
621 
    t.pctrl_bypass.me.meop_param.addrin := '0';
622 
    t.pctrl_bypass.me.meop_param.signed := '0';
623 
    t.pctrl_bypass.me.mexc := '0';
624 
    t.pctrl_bypass.wr.wrop_rd := (others => '0');
625 
    t.pctrl_bypass.wr.wrop_rdvalid := '0';
626 
    t.pctrl_bypass.wr.wrop_setspsr := '0';
627 
    t.pctrl_bypass.wr.wrop_trap.traptype := apm_trap_reset;
628 
    t.pctrl_bypass.wr.wrop_trap.trap := '0';
629 
    t.pctrl_bypass.data1 := (others => '0');
630 
    t.pctrl_bypass.data2 := (others => '0');
631 
    t.commit := '0';
632 
    t.insn := (others => '0');
633 
    t.trap.traptype := apm_trap_reset;
634 
    t.trap.trap := '0';
635 
    t.nextmicro := '0';
636 
    t.mem := '0';
637 
    t.micro.pctrl.insn.pc_8 := (others => '0');
638 
    t.micro.pctrl.insn.insn := (others => '0');
639 
    t.micro.pctrl.insn.insntyp := ade_typmem;
640 
    t.micro.pctrl.insn.decinsn := type_arm_invalid;
641 
    t.micro.pctrl.insn.am.DAPRAM_typ := ade_DAPRAM_simm;
642 
    t.micro.pctrl.insn.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
643 
    t.micro.pctrl.insn.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
644 
    t.micro.pctrl.insn.am.LDSTAMxLSV4AM_pos := ade_pre;
645 
    t.micro.pctrl.insn.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
646 
    t.micro.pctrl.insn.am.LDSTAMxLSV4AM_uacc := '0';
647 
    t.micro.pctrl.insn.am.LDSTAMxLSV4AM_wb := '0';
648 
    t.micro.pctrl.insn.valid := '0';
649 
    t.micro.pctrl.insn.id := (others => '0');
650 
    t.micro.pctrl.valid := '0';
651 
    t.micro.pctrl.rr.dummy := '0';
652 
    t.micro.pctrl.rs.rsop_op1_src := apc_opsrc_through;
653 
    t.micro.pctrl.rs.rsop_op2_src := apc_opsrc_through;
654 
    t.micro.pctrl.rs.rsop_buf1_src := apc_bufsrc_none;
655 
    t.micro.pctrl.rs.rsop_buf2_src := apc_bufsrc_none;
656 
    t.micro.pctrl.rs.rsop_styp := ash_styp_none;
657 
    t.micro.pctrl.rs.rsop_sdir := ash_sdir_snone;
658 
    t.micro.pctrl.rs.rs_shieftcarryout := '0';
659 
    t.micro.pctrl.ex.exop_aluop := (others => '0');
660 
    t.micro.pctrl.ex.exop_data_src := apc_datasrc_aluout;
661 
    t.micro.pctrl.ex.exop_buf_src := apc_exbufsrc_none;
662 
    t.micro.pctrl.ex.exop_setcpsr := '0';
663 
    t.micro.pctrl.ex.ex_cpsr.ex.n := '0';
664 
    t.micro.pctrl.ex.ex_cpsr.ex.z := '0';
665 
    t.micro.pctrl.ex.ex_cpsr.ex.c := '0';
666 
    t.micro.pctrl.ex.ex_cpsr.ex.v := '0';
667 
    t.micro.pctrl.ex.ex_cpsr.wr.i := '0';
668 
    t.micro.pctrl.ex.ex_cpsr.wr.f := '0';
669 
    t.micro.pctrl.ex.ex_cpsr.wr.t := '0';
670 
    t.micro.pctrl.ex.ex_cpsr.wr.mode := (others => '0');
671 
    t.micro.pctrl.dm.dummy := '0';
672 
    t.micro.pctrl.me.meop_enable := '0';
673 
    t.micro.pctrl.me.meop_param.size := lmd_word;
674 
    t.micro.pctrl.me.meop_param.read := '0';
675 
    t.micro.pctrl.me.meop_param.lock := '0';
676 
    t.micro.pctrl.me.meop_param.writedata := '0';
677 
    t.micro.pctrl.me.meop_param.addrin := '0';
678 
    t.micro.pctrl.me.meop_param.signed := '0';
679 
    t.micro.pctrl.me.mexc := '0';
680 
    t.micro.pctrl.wr.wrop_rd := (others => '0');
681 
    t.micro.pctrl.wr.wrop_rdvalid := '0';
682 
    t.micro.pctrl.wr.wrop_setspsr := '0';
683 
    t.micro.pctrl.wr.wrop_trap.traptype := apm_trap_reset;
684 
    t.micro.pctrl.wr.wrop_trap.trap := '0';
685 
    t.micro.pctrl.data1 := (others => '0');
686 
    t.micro.pctrl.data2 := (others => '0');
687 
    t.micro.valid := '0';
688 
    t.micro.r1 := (others => '0');
689 
    t.micro.r2 := (others => '0');
690 
    t.micro.r1_valid := '0';
691 
    t.micro.r2_valid := '0';
692 
    t.am.DAPRAM_typ := ade_DAPRAM_simm;
693 
    t.am.LDSTAM_typ := ade_LDSTAMxLSV4AM_imm;
694 
    t.am.LSV4AM_typ := ade_LDSTAMxLSV4AM_imm;
695 
    t.am.LDSTAMxLSV4AM_pos := ade_pre;
696 
    t.am.DAPRAMxLDSTAM_sdir := ash_sdir_snone;
697 
    t.am.LDSTAMxLSV4AM_uacc := '0';
698 
    t.am.LDSTAMxLSV4AM_wb := '0';
699 
    t.r1_src := acm_none;
700 
    t.r2_src := acm_none;
701 
    t.rd_src := acm_rdnone;
702 
    t.rn := (others => '0');
703 
    t.rm := (others => '0');
704 
    t.rd := (others => '0');
705 
    t.rs := (others => '0');
706 
    t.rlink := (others => '0');
707 
    t.rpc := (others => '0');
708 
    t.nr := (others => '0');
709 
    t.nr_i := 0;
710 
    t.nr_c := '0';
711 
    t.startoff := (others => '0');
712 
    t.endoff := (others => '0');
713 
    t.incval := (others => '0');
714 
    t.m1 := (others => '0');
715 
    t.m2 := (others => '0');
716 
    t.md := (others => '0');
717 
    t.m1_valid := '0';
718 
    t.m2_valid := '0';
719 
    t.rr1 := (others => '0');
720 
    t.rr2 := (others => '0');
721 
    t.rrd := (others => '0');
722 
    t.rmode := (others => '0');
723 
 
724 
    -- $(/init-automatically-generated-for-synthesis:(t:armiu_drstg_tmp_type))
725 
 
726 
    v := r;
727 
    t.commit := not i.flush_v;
728 
 
729 
    t.insn := i.fromDE_insn_r.insn.insn;
730 
    t.am := i.fromDE_insn_r.insn.am;
731 
    t.rn := t.insn(ADE_RN_U downto ADE_RN_D);
732 
    t.rm := t.insn(ADE_RM_U downto ADE_RM_D);
733 
    t.rs := t.insn(ADE_SREG_U downto ADE_SREG_D);
734 
    t.rd := t.insn(ADE_RD_U downto ADE_RD_D);
735 
    t.rlink := APM_REG_LINK;
736 
    t.r1_src    := acm_none;
737 
    t.r2_src    := acm_none;
738 
    t.rmode := i.pstate.fromEX_cpsr_r.wr.mode;
739 
    t.m1 := t.rd;
740 
    t.m2 := t.rd;
741 
    t.md := t.rd;
742 
    t.nr_c := '1';
743 
 
744 
    -- cmd lm, sm:
745 
    t.nr := als_getnextpos(t.insn, r.reglist);
746 
    t.nr_i := lin_convint(t.nr);
747 
 
748 
    als_offsets (t.insn, t.startoff, t.endoff, t.incval );
749 
 
750 
    t.mem := '0';
751 
    if apc_is_mem(i.pstate.fromRR_pctrl_r) or
752 
       apc_is_mem(i.pstate.fromRS_pctrl_r) or
753 
       apc_is_mem(i.pstate.fromEX_pctrl_r) or
754 
       apc_is_mem(i.pstate.fromDM_pctrl_r) or
755 
       apc_is_mem(i.pstate.fromME_pctrl_r) or
756 
       apc_is_mem(i.pstate.fromWR_pctrl_r) then
757 
      t.mem := '1';
758 
    end if;
759 
 
760 
    t.ctrlo.nextinsn := '1';
761 
    t.ctrlo.nextcnt := '1';
762 
    t.ctrlo.hold := '0';
763 
 
764 
    t.ctrli.cnt := r.cnt;
765 
    t.ctrli.insn := i.fromDE_insn_r.insn;
766 
    t.ctrli.ctrlo := t.ctrlo;
767 
 
768 
    t.pctrl.insn := i.fromDE_insn_r.insn;
769 
    t.pctrl.ex.exop_aluop := i.fromDE_insn_r.insn.insn(ADE_OP_U downto ADE_OP_D);
770 
    t.pctrl_bypass := t.pctrl;
771 
 
772 
    case i.fromDE_insn_r.insn.decinsn is
773 
      when type_arm_invalid =>
774 
      when type_arm_nop =>
775 
 
776 
-------------------------------------------------------------------------------
777 
 
778 
      when type_arm_mrs |
779 
           type_arm_msr =>
780 
 
781 
        t.cmdsri.ctrli := t.ctrli;
782 
        t.cmdsri.deid := i.fromDE_insn_r.insn.id;
783 
        t.cmdsri.exid := i.pstate.fromEX_pctrl_r.insn.id;
784 
        t.cmdsri.exvalid := i.pstate.fromEX_pctrl_r.valid;
785 
        t.cmdsri.wrid := i.pstate.fromWR_pctrl_r.insn.id;
786 
        t.cmdsri.wrvalid := i.pstate.fromWR_pctrl_r.valid;
787 
        t.ctrlo := cmdsro.ctrlo;
788 
 
789 
        t.r1_src := acm_none;
790 
        t.r2_src := cmdsro.r2_src;
791 
        t.rd_src := cmdsro.rd_src;
792 
 
793 
         -- rsstg:
794 
        t.pctrl.rs.rsop_op1_src := apc_opsrc_none;
795 
        t.pctrl.rs.rsop_op2_src := cmdsro.rsop_op2_src;
796 
        t.pctrl.rs.rsop_styp := cmdsro.rsop_styp;
797 
        t.pctrl.rs.rsop_sdir := cmdsro.rsop_sdir;
798 
 
799 
        -- exstg:
800 
        t.pctrl.ex.exop_setcpsr := cmdsro.exop_setcpsr;
801 
 
802 
-------------------------------------------------------------------------------
803 
 
804 
      when type_arm_bx =>
805 
      when type_arm_mul =>
806 
      when type_arm_mla =>
807 
      when type_arm_sumull =>
808 
      when type_arm_sumlal =>
809 
 
810 
-------------------------------------------------------------------------------
811 
 
812 
      when type_arm_teq |
813 
           type_arm_cmn |
814 
           type_arm_tst |
815 
           type_arm_cmp |
816 
           type_arm_and |
817 
           type_arm_sub |
818 
           type_arm_eor |
819 
           type_arm_rsb |
820 
           type_arm_add |
821 
           type_arm_orr |
822 
           type_arm_bic |
823 
           type_arm_mov |
824 
           type_arm_mvn |
825 
           type_arm_sbc |
826 
           type_arm_adc |
827 
           type_arm_rsc =>
828 
 
829 
        t.cmdali.ctrli := t.ctrli;
830 
 
831 
        t.ctrlo := cmdalo.ctrlo;
832 
 
833 
        -- rrstg
834 
        t.r1_src := cmdalo.r1_src;      -- (micro.r1)
835 
        t.r2_src := cmdalo.r2_src;      -- (micro.r2)
836 
        t.rd_src := cmdalo.rd_src;      -- (pctrl.wr.wrop_rd)
837 
 
838 
        -- rsstg:
839 
        t.pctrl.rs.rsop_op1_src := cmdalo.rsop_op1_src; -- EXSTG operand1 source
840 
        t.pctrl.rs.rsop_op2_src := cmdalo.rsop_op2_src; -- EXSTG operand2 source
841 
        t.pctrl.rs.rsop_buf2_src := cmdalo.rsop_buf2_src; -- RSSTG buffer1 source
842 
        t.pctrl.rs.rsop_styp := ash_styp_none;
843 
        t.pctrl.rs.rsop_sdir := t.am.DAPRAMxLDSTAM_sdir;
844 
        case t.am.DAPRAM_typ is
845 
          when ade_DAPRAM_immrot => t.pctrl.rs.rsop_styp := ash_styp_immrot;
846 
          when ade_DAPRAM_simm   => t.pctrl.rs.rsop_styp := ash_styp_simm;
847 
          when ade_DAPRAM_sreg   => t.pctrl.rs.rsop_styp := ash_styp_sreg;
848 
          when others => null;
849 
        end case;
850 
 
851 
        t.pctrl.ex.exop_setcpsr := t.insn(ADE_SETCPSR_C);
852 
 
853 
-------------------------------------------------------------------------------
854 
 
855 
      when type_arm_str1 | type_arm_str2 | type_arm_str3 |
856 
           type_arm_strhb =>
857 
 
858 
        t.cmdsti.ctrli := t.ctrli;
859 
 
860 
        t.ctrlo := cmdsto.ctrlo;
861 
 
862 
        acm_initmempctrl(t.pctrl, t.r1_src, t.r2_src, t.rd_src, cmdsto.ctrlmemo );
863 
 
864 
        case i.fromDE_insn_r.insn.decinsn is
865 
          when type_arm_str1 |
866 
               type_arm_str2 |
867 
               type_arm_str3  =>
868 
            als_LDSTAM_init_size(t.insn, t.pctrl);
869 
          when others =>
870 
            als_LSV4AM_init_size(t.insn, t.pctrl);
871 
        end case;
872 
 
873 
        als_LDSTAMxLSV4AM_init_addsub(t.insn, t.pctrl);
874 
 
875 
        t.pctrl.rs.rsop_styp := cmdsto.rsop_styp; -- RSSTG shieft op
876 
        t.pctrl.rs.rsop_sdir := cmdsto.rsop_sdir; -- RSSTG shieft dir
877 
 
878 
-------------------------------------------------------------------------------
879 
 
880 
      when type_arm_ldr1 |
881 
           type_arm_ldrhb =>
882 
 
883 
        t.cmdldi.ctrli := t.ctrli;
884 
 
885 
        t.ctrlo := cmdldo.ctrlo;
886 
 
887 
        acm_initmempctrl(t.pctrl, t.r1_src, t.r2_src, t.rd_src, cmdldo.ctrlmemo );
888 
 
889 
        case i.fromDE_insn_r.insn.decinsn is
890 
          when type_arm_ldr1 =>
891 
            als_LDSTAM_init_size(t.insn, t.pctrl);
892 
          when others =>
893 
            als_LSV4AM_init_size(t.insn, t.pctrl);
894 
        end case;
895 
 
896 
        als_LDSTAMxLSV4AM_init_addsub(t.insn, t.pctrl);
897 
 
898 
        t.pctrl.rs.rsop_styp := cmdldo.rsop_styp; -- RSSTG shieft op
899 
        t.pctrl.rs.rsop_sdir := cmdldo.rsop_sdir; -- RSSTG shieft dir
900 
 
901 
-------------------------------------------------------------------------------
902 
 
903 
      when type_arm_stm =>
904 
 
905 
        t.cmdsmi.ctrli := t.ctrli;
906 
 
907 
        t.cmdsmi.ctrlmulti.ival := t.incval;
908 
        t.cmdsmi.ctrlmulti.soff := t.startoff;
909 
        t.cmdsmi.ctrlmulti.eoff := t.endoff;
910 
        t.cmdsmi.ctrlmulti.reglist := r.reglist;
911 
        t.cmdsmi.ctrlmulti.mem := t.mem;
912 
        t.cmdsmi.ctrlmulti.dabort := i.fromWR_dabort_v;
913 
 
914 
        t.ctrlo := cmdsmo.ctrlo;
915 
 
916 
        acm_initmempctrl(t.pctrl, t.r1_src, t.r2_src, t.rd_src, cmdsmo.ctrlmemo );
917 
 
918 
        t.pctrl.ex.exop_aluop := ADE_OP_ADD;
919 
 
920 
        t.m1 := t.nr;               -- acm_local
921 
        t.nr_c := r.cnt(0);         -- every second cycle
922 
 
923 
-------------------------------------------------------------------------------
924 
 
925 
      when type_arm_ldm =>
926 
 
927 
        t.cmdlmi.ctrli := t.ctrli;
928 
 
929 
        t.cmdlmi.ctrlmulti.ival := t.incval;
930 
        t.cmdlmi.ctrlmulti.soff := t.startoff;
931 
        t.cmdlmi.ctrlmulti.eoff := t.endoff;
932 
        t.cmdlmi.ctrlmulti.reglist := r.reglist;
933 
        t.cmdlmi.ctrlmulti.mem := t.mem;
934 
        t.cmdlmi.ctrlmulti.dabort := i.fromWR_dabort_v;
935 
 
936 
        t.ctrlo := cmdlmo.ctrlo;
937 
 
938 
        acm_initmempctrl(t.pctrl, t.r1_src, t.r2_src, t.rd_src, cmdlmo.ctrlmemo );
939 
 
940 
        t.pctrl.ex.exop_aluop := ADE_OP_ADD;
941 
 
942 
        t.md := t.nr;                   -- acm_rdlocal
943 
 
944 
-------------------------------------------------------------------------------
945 
 
946 
      when type_arm_b =>
947 
 
948 
        t.ctrlo := cmdblo.ctrlo;
949 
 
950 
        t.r1_src := cmdblo.r1_src;
951 
        t.r2_src := cmdblo.r2_src;
952 
        t.rd_src := cmdblo.rd_src;
953 
        t.pctrl.data2 := cmdblo.data2;
954 
 
955 
        -- rsstg:
956 
        t.pctrl.rs.rsop_op2_src := cmdblo.rsop_op2_src;
957 
        -- exstg:
958 
        t.pctrl.ex.exop_aluop := ADE_OP_ADD;
959 
 
960 
        t.m1 := APM_REG_PC;            -- acm_local
961 
 
962 
-------------------------------------------------------------------------------
963 
 
964 
      when type_arm_swp =>
965 
 
966 
        t.cmdswi.ctrli := t.ctrli;
967 
 
968 
        t.ctrlo := cmdswo.ctrlo;
969 
 
970 
        t.pctrl.ex.exop_aluop := ADE_OP_ORR;
971 
 
972 
        acm_initmempctrl(t.pctrl, t.r1_src, t.r2_src, t.rd_src, cmdswo.ctrlmemo );
973 
 
974 
-------------------------------------------------------------------------------
975 
 
976 
      when type_arm_stc =>
977 
        t.cmdcsi.ctrli := t.ctrli;
978 
 
979 
        t.cmdcsi.fromCP_busy := i.fromCPDE_busy;
980 
        t.cmdcsi.fromCP_last := i.fromCPDE_last;
981 
        t.ctrlo := cmdcso.ctrlo;
982 
 
983 
      when type_arm_ldc =>
984 
        t.cmdcli.ctrli := t.ctrli;
985 
        t.cmdcli.fromCP_busy := i.fromCPDE_busy;
986 
        t.cmdcli.fromCP_last := i.fromCPDE_last;
987 
        t.ctrlo := cmdclo.ctrlo;
988 
 
989 
      when type_arm_mrc |
990 
           type_arm_mcr =>
991 
 
992 
        t.cmdcri.fromCP_busy := i.fromCPDE_busy;
993 
        t.cmdcri.ctrli := t.ctrli;
994 
        t.ctrlo := cmdcro.ctrlo;
995 
        t.r1_src := cmdcro.r1_src;
996 
        t.rd_src := cmdcro.rd_src;
997 
 
998 
        t.pctrl.ex.exop_data_src := apc_datasrc_none;  -- keep pctrl.data1
999 
 
1000 
      when type_arm_swi =>
1001 
        t.trap.trap := '1';
1002 
        t.trap.traptype := apm_trap_swi;
1003 
 
1004 
      when type_arm_undefined =>
1005 
        t.trap.trap := '1';
1006 
        t.trap.traptype := apm_trap_undef;
1007 
 
1008 
      when type_arm_cdp =>
1009 
      when others =>
1010 
    end case;
1011 
 
1012 
    if i.fromDE_insn_r.trap = '1' then
1013 
      t.trap.trap := '1';
1014 
      t.trap.traptype := apm_trap_prefch;
1015 
    end if;
1016 
 
1017 
    -- traps
1018 
    if t.trap.trap = '1' then
1019 
 
1020 
      t.m1_valid := '0';
1021 
      t.m2_valid := '0';
1022 
 
1023 
      -- [frame:] r14 calculation
1024 
      --
1025 
      --            RRSTG       RSSTG       EXSTG       DMSTG       MESTG       WRSTG
1026 
      --       --+-----------+-----------+-----------+-----------+-----------+----------+
1027 
      -- <pc+8>->+-----------+----------op1          |           |           |
1028 
      --         |           |           | \         |           |           |
1029 
      --         |  (regread)| (noshift) | +(aluop)  |  (trans)  | (dcache)  | +->(write)
1030 
      --         |           |           | /   |     |           |           | |
1031 
      --         |           |  <offset>op2    |     |           |           | |
1032 
      --       --+-----------+-----------+-----+-----+-----------+-----------+-+--------+
1033 
      --                                       |                               |
1034 
      --         pctrl.data1 (as r14-data) :   +-------------------------------+
1035 
 
1036 
      t.pctrl := t.pctrl_bypass;
1037 
      t.r1_src := acm_none;
1038 
      t.r2_src := acm_none;
1039 
      t.rd_src := acm_rdnone;
1040 
 
1041 
      t.pctrl.rs.rsop_op1_src := apc_opsrc_none;
1042 
      t.pctrl.rs.rsop_op2_src := apc_opsrc_none;
1043 
      t.pctrl.ex.exop_data_src := apc_datasrc_aluout;
1044 
      t.pctrl.data1 := i.fromDE_insn_r.insn.pc_8;
1045 
      t.pctrl.data2 := (others => '0');
1046 
 
1047 
      case t.trap.traptype is
1048 
        when apm_trap_reset    =>
1049 
 
1050 
-- $(del)
1051 
-- R14_svc = UNPREDICTABLE value
1052 
-- SPSR_svc = UNPREDICTABLE value
1053 
-- CPSR[4:0] = 0b10011 /* Enter Supervisor mode */
1054 
-- CPSR[5] = 0 /* Execute in ARM state */
1055 
-- CPSR[6] = 1 /* Disable fast interrupts */
1056 
-- CPSR[7] = 1 /* Disable normal interrupts */
1057 
-- if high vectors configured then
1058 
-- PC = 0xFFFF0000
1059 
-- else
1060 
-- PC = 0x00000000
1061 
-- $(/del)
1062 
 
1063 
        when apm_trap_undef =>
1064 
 
1065 
-- $(del)
1066 
-- R14_und = address of next instruction after the undefined instruction
1067 
-- SPSR_und = CPSR
1068 
-- CPSR[4:0] = 0b11011 /* Enter Undefined mode */
1069 
-- CPSR[5] = 0 /* Execute in ARM state */
1070 
-- /* CPSR[6] is unchanged */
1071 
-- CPSR[7] = 1 /* Disable normal interrupts */
1072 
-- if high vectors configured then
1073 
-- PC = 0xFFFF0004
1074 
-- else
1075 
-- PC = 0x00000004
1076 
-- $(/del)
1077 
 
1078 
          t.pctrl.data2 := LIN_MINFOUR;
1079 
 
1080 
        when apm_trap_swi      =>
1081 
 
1082 
-- $(del)
1083 
-- R14_svc = address of next instruction after the SWI instruction
1084 
-- SPSR_svc = CPSR
1085 
-- CPSR[4:0] = 0b10011 /* Enter Supervisor mode */
1086 
-- CPSR[5] = 0 /* Execute in ARM state */
1087 
-- /* CPSR[6] is unchanged */
1088 
-- CPSR[7] = 1 /* Disable normal interrupts */
1089 
-- if high vectors configured then
1090 
-- PC = 0xFFFF0008
1091 
-- else
1092 
-- PC = 0x00000008
1093 
-- $(/del)
1094 
 
1095 
          t.pctrl.data2 := LIN_MINFOUR;
1096 
 
1097 
        when apm_trap_prefch =>
1098 
 
1099 
-- $(del)
1100 
-- R14_abt = address of the aborted instruction + 4
1101 
-- SPSR_abt = CPSR
1102 
-- CPSR[4:0] = 0b10111 /* Enter Abort mode */
1103 
-- CPSR[5] = 0 /* Execute in ARM state */
1104 
-- /* CPSR[6] is unchanged */
1105 
-- CPSR[7] = 1 /* Disable normal interrupts */
1106 
-- if high vectors configured then
1107 
-- PC = 0xFFFF000C
1108 
-- else
1109 
-- PC = 0x0000000C
1110 
-- $(/del)
1111 
 
1112 
          t.pctrl.data2 := LIN_MINFOUR;
1113 
 
1114 
        when apm_trap_dabort   =>
1115 
 
1116 
-- $(del)
1117 
-- R14_abt = address of the aborted instruction + 8
1118 
-- SPSR_abt = CPSR
1119 
-- CPSR[4:0] = 0b10111 /* Enter Abort mode */
1120 
-- CPSR[5] = 0 /* Execute in ARM state */
1121 
-- /* CPSR[6] is unchanged */
1122 
-- CPSR[7] = 1 /* Disable normal interrupts */
1123 
-- if high vectors configured then
1124 
-- PC = 0xFFFF0010
1125 
-- else
1126 
-- PC = 0x00000010
1127 
-- $(/del)
1128 
          -- will not happen (later in pipeline)
1129 
          -- pragma translate_off
1130 
          assert false report "Wrong initialization of trap type" severity failure;
1131 
          -- pragma translate_on
1132 
 
1133 
        when apm_trap_irq      =>
1134 
 
1135 
-- $(del)
1136 
-- R14_irq = address of next instruction to be executed + 4
1137 
-- SPSR_irq = CPSR
1138 
-- CPSR[4:0] = 0b10010 /* Enter IRQ mode */
1139 
-- CPSR[5] = 0 /* Execute in ARM state */
1140 
-- /* CPSR[6] is unchanged */
1141 
-- CPSR[7] = 1 /* Disable normal interrupts */
1142 
-- if high vectors configured then
1143 
-- PC = 0xFFFF0018
1144 
-- else
1145 
-- PC = 0x00000018
1146 
-- $(/del)
1147 
 
1148 
          --v.pctrl.MESTGxWRSTG_data := t.regshiefto.RSSTG_pc_4;
1149 
 
1150 
        when apm_trap_fiq      =>
1151 
 
1152 
-- $(del)
1153 
-- R14_fiq = address of next instruction to be executed + 4
1154 
-- SPSR_fiq = CPSR
1155 
-- CPSR[4:0] = 0b10001 /* Enter FIQ mode */
1156 
-- CPSR[5] = 0 /* Execute in ARM state */
1157 
-- CPSR[6] = 1 /* Disable fast interrupts */
1158 
-- CPSR[7] = 1 /* Disable normal interrupts */
1159 
-- if high vectors configured then
1160 
-- PC = 0xFFFF001C
1161 
-- else
1162 
-- PC = 0x0000001C
1163 
-- $(/del)
1164 
 
1165 
          --v.pctrl.MESTGxWRSTG_data := t.regshiefto.RSSTG_pc_4;
1166 
 
1167 
        when others            =>
1168 
      end case;
1169 
 
1170 
    end if;
1171 
    t.pctrl.wr.wrop_trap := t.trap;
1172 
 
1173 
    -- src registers
1174 
    t.m1_valid  := '1';
1175 
    case t.r1_src is
1176 
      when acm_rrn  => t.m1 := t.rn;
1177 
      when acm_rrm  => t.m1 := t.rm;
1178 
      when acm_rrs  => t.m1 := t.rs;
1179 
      when acm_rrd  => t.m1 := t.rd;
1180 
      when acm_none => t.m1_valid := '0';
1181 
      when acm_local => t.m1_valid := '1';
1182 
      when others => null;
1183 
    end case;
1184 
    t.rr1 := apm_bankreg(t.rmode,t.m1);
1185 
 
1186 
    t.m2_valid  := '1';
1187 
    case t.r2_src is
1188 
      when acm_rrn  => t.m2 := t.rn;
1189 
      when acm_rrm  => t.m2 := t.rm;
1190 
      when acm_rrs  => t.m2 := t.rs;
1191 
      when acm_rrd  => t.m2 := t.rd;
1192 
      when acm_none => t.m2_valid := '0';
1193 
      when acm_local => t.m2_valid := '1';
1194 
      when others =>
1195 
    end case;
1196 
    t.rr2 := apm_bankreg(t.rmode,t.m2);
1197 
 
1198 
    t.pctrl.wr.wrop_rdvalid := '1';
1199 
    case t.rd_src is
1200 
      when acm_rdrrn  => t.md := t.rn;
1201 
      when acm_rdrrd  => t.md := t.rd;
1202 
      when acm_rdpc   => t.md := APM_REG_PC;
1203 
      when acm_rdlink => t.md := APM_REG_LINK;
1204 
      when acm_rdnone => t.pctrl.wr.wrop_rdvalid := '0';
1205 
      when acm_rdlocal => t.pctrl.wr.wrop_rdvalid := '1';
1206 
      when others =>
1207 
    end case;
1208 
    t.pctrl.wr.wrop_rd := apm_bankreg(t.rmode,t.md);
1209 
 
1210 
    t.micro.pctrl := t.pctrl;
1211 
    t.micro.r1 := t.rr1;
1212 
    t.micro.r2 := t.rr2;
1213 
    t.micro.r1_valid := t.m1_valid;
1214 
    t.micro.r2_valid := t.m2_valid;
1215 
    t.micro.pctrl.valid := '0';
1216 
    t.micro.valid := '1';
1217 
 
1218 
    -- microcode counter
1219 
    t.nextmicro := i.fromRR_nextmicro_v;
1220 
 
1221 
    if t.ctrlo.hold = '1' then
1222 
      t.nextmicro := '0';
1223 
      t.micro.valid := '0';
1224 
    end if;
1225 
 
1226 
    -- invalid insn & pipeline flush
1227 
    if (i.fromDE_insn_r.insn.valid = '0') or
1228 
       (not (t.commit = '1')) then
1229 
      t.ctrlo.nextinsn := '1';
1230 
      t.nextmicro := '1';
1231 
      t.micro.valid := '0';
1232 
    end if;
1233 
    t.o.toRR_micro_v := t.micro;
1234 
 
1235 
    if i.pstate.hold_r.hold = '0' then
1236 
      if t.nextmicro = '1' then
1237 
        if t.ctrlo.nextinsn = '1' then
1238 
          v.cnt := (others => '0');
1239 
          v.reglist := i.fromDE_insn_v.insn.insn(ADE_REGLIST_U downto ADE_REGLIST_D);
1240 
        else
1241 
          if t.ctrlo.nextcnt = '1' then
1242 
            lin_incdec(r.cnt,v.cnt,'1','1');
1243 
            if t.nr_c = '1' then
1244 
              v.reglist(t.nr_i) := '0';
1245 
            end if;
1246 
          end if;
1247 
        end if;
1248 
      else
1249 
        t.ctrlo.nextinsn := '0';
1250 
      end if;
1251 
    end if;
1252 
 
1253 
 
1254 
    t.o.nextinsn_v := t.ctrlo.nextinsn;
1255 
    t.o.id := i.fromDE_insn_r.insn.id;
1256 
 
1257 
    -- reset
1258 
    if ( rst = '0' ) then
1259 
    end if;
1260 
 
1261 
    c <= v;
1262 
 
1263 
    cmdali <= t.cmdali;
1264 
    cmdsri <= t.cmdsri;
1265 
    cmdldi <= t.cmdldi;
1266 
    cmdsti <= t.cmdsti;
1267 
    cmdlmi <= t.cmdlmi;
1268 
    cmdsmi <= t.cmdsmi;
1269 
    cmdswi <= t.cmdswi;
1270 
    cmdcri <= t.cmdcri;
1271 
    cmdcli <= t.cmdcli;
1272 
    cmdcsi <= t.cmdcsi;
1273 
    cmdbli <= t.cmdbli;
1274 
 
1275 
    o <= t.o;
1276 
 
1277 
    -- pragma translate_off
1278 
    vdbg := rdbg;
1279 
    vdbg.dbg := t;
1280 
    vdbg.dbgpmode := adg_todbgpmode(i.pstate.fromEX_cpsr_r.wr.mode);
1281 
    vdbg.dbgrmode := adg_todbgpmode(t.rmode);
1282 
    cdbg <= vdbg;
1283 
    -- pragma translate_on
1284 
 
1285 
  end process p0;
1286 
 
1287 
  pregs : process (clk, c)
1288 
  begin
1289 
    if rising_edge(clk) then
1290 
      r <= c;
1291 
      -- pragma translate_off
1292 
      rdbg <= cdbg;
1293 
      -- pragma translate_on
1294 
    end if;
1295 
  end process;
1296 
 
1297 
  al0: armcmd_al port map ( rst, clk, cmdali, cmdalo );
1298 
  sr0: armcmd_sr port map ( rst, clk, cmdsri, cmdsro );
1299 
  ld0: armcmd_ld port map ( rst, clk, cmdldi, cmdldo );
1300 
  st0: armcmd_st port map ( rst, clk, cmdsti, cmdsto );
1301 
  lm0: armcmd_lm port map ( rst, clk, cmdlmi, cmdlmo );
1302 
  sm0: armcmd_sm port map ( rst, clk, cmdsmi, cmdsmo );
1303 
  sw0: armcmd_sw port map ( rst, clk, cmdswi, cmdswo );
1304 
  cr0: armcmd_cr port map ( rst, clk, cmdcri, cmdcro );
1305 
  cl0: armcmd_cl port map ( rst, clk, cmdcli, cmdclo );
1306 
  cs0: armcmd_cs port map ( rst, clk, cmdcsi, cmdcso );
1307 
  bl0: armcmd_bl port map ( rst, clk, cmdbli, cmdblo );
1308 
 
1309 
end rtl;

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