1 |
2 |
tarookumic |
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2 |
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typedef struct _proc_state {} proc_state;
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3 |
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typedef struct _insn_dp_i_s_struct {
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4 |
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/*Data Processing immidiate shieft*/
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5 |
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int (*func) (struct _insn_dp_i_s_struct *s, proc_state *state);
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6 |
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unsigned int c: 5; /*Condition code*/
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7 |
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unsigned int op1: 5; /*Data processing opcode*/
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8 |
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unsigned int dps: 2; /*Update cpsr*/
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9 |
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unsigned int rn: 5; /*Register rn*/
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10 |
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unsigned int rd: 5; /*Destination register rd*/
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11 |
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unsigned int sha: 6; /*Shieft amount*/
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12 |
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unsigned int sh: 3; /*Shieft direction*/
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13 |
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unsigned int rm: 5; /*Register rm*/
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14 |
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} insn_dp_i_s_struct;
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15 |
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typedef struct _insn_msr_struct {
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16 |
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/*Move status register to register*/
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17 |
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int (*func) (struct _insn_msr_struct *s, proc_state *state);
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18 |
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unsigned int c: 5; /*Condition code*/
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19 |
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unsigned int R: 2; /*Cpsr|Spsr '1'=Spsr*/
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20 |
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unsigned int SBO: 5; /**/
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21 |
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unsigned int rd: 5; /*Destination register rd*/
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22 |
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unsigned int SBZ: 5; /**/
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23 |
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unsigned int SBZ2: 5; /**/
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24 |
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} insn_msr_struct;
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25 |
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typedef struct _insn_mrs_struct {
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26 |
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/*Move register to status register*/
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27 |
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int (*func) (struct _insn_mrs_struct *s, proc_state *state);
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28 |
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unsigned int c: 5; /*Condition code*/
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29 |
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unsigned int R: 2; /*Cpsr|Spsr '1'=Spsr*/
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30 |
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unsigned int msk: 5; /**/
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31 |
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unsigned int SBO: 5; /**/
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32 |
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unsigned int SBZ: 5; /**/
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33 |
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unsigned int rm: 5; /*Register rm*/
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34 |
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} insn_mrs_struct;
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35 |
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typedef struct _insn_bex_struct {
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36 |
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/*Branch / exchange*/
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37 |
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int (*func) (struct _insn_bex_struct *s, proc_state *state);
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38 |
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unsigned int c: 5; /*Condition code*/
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39 |
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unsigned int SBO: 13; /**/
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40 |
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unsigned int rm: 5; /*Register rm*/
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41 |
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} insn_bex_struct;
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42 |
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typedef struct _insn_clz_struct {
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43 |
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/*Count leading zero*/
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44 |
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int (*func) (struct _insn_clz_struct *s, proc_state *state);
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45 |
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unsigned int c: 5; /*Condition code*/
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46 |
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unsigned int SBO: 5; /**/
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47 |
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unsigned int rd: 5; /*Destination register rd*/
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48 |
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unsigned int SBO2: 5; /**/
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49 |
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unsigned int rm: 5; /*Register rm*/
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50 |
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} insn_clz_struct;
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51 |
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typedef struct _insn_blx_struct {
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52 |
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/*Branch and link /exchange*/
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53 |
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int (*func) (struct _insn_blx_struct *s, proc_state *state);
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54 |
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unsigned int c: 5; /*Condition code*/
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55 |
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unsigned int SBO: 13; /**/
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56 |
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unsigned int rm: 5; /*Register rm*/
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57 |
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} insn_blx_struct;
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58 |
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typedef struct _insn_dsa_struct {
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59 |
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/*Dsp add|sub*/
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60 |
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int (*func) (struct _insn_dsa_struct *s, proc_state *state);
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61 |
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unsigned int c: 5; /*Condition code*/
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62 |
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unsigned int dsop: 3; /*Dsp operand*/
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63 |
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unsigned int rn: 5; /*Register rn*/
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64 |
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unsigned int rd: 5; /*Destination register rd*/
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65 |
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unsigned int SBZ: 5; /**/
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66 |
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unsigned int rm: 5; /*Register rm*/
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67 |
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} insn_dsa_struct;
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68 |
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typedef struct _insn_brk_struct {
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/*Breakpoint*/
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70 |
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int (*func) (struct _insn_brk_struct *s, proc_state *state);
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71 |
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unsigned int c: 5; /*Condition code*/
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72 |
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unsigned int imm: 13; /*Breakpoint imm part1*/
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73 |
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unsigned int imm2: 5; /*Breakpoint imm part2*/
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} insn_brk_struct;
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typedef struct _insn_dsm_struct {
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/*DSP multiply*/
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77 |
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int (*func) (struct _insn_dsm_struct *s, proc_state *state);
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78 |
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unsigned int c: 5; /*Condition code*/
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79 |
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unsigned int dsop: 3; /*Dsp operand*/
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80 |
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unsigned int RD: 5; /**/
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81 |
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unsigned int rn: 5; /*Register rn*/
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unsigned int rs: 5; /*Register rs*/
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83 |
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unsigned int y: 2; /**/
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84 |
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unsigned int x: 2; /**/
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85 |
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unsigned int rm: 5; /*Register rm*/
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86 |
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} insn_dsm_struct;
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87 |
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typedef struct _insn_dp_r_s_struct {
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88 |
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/*Data processing register shieft*/
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89 |
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int (*func) (struct _insn_dp_r_s_struct *s, proc_state *state);
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90 |
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unsigned int c: 5; /*Condition code*/
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91 |
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unsigned int op1: 5; /*Data processing opcode*/
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92 |
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unsigned int dps: 2; /*Update cpsr*/
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93 |
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unsigned int rn: 5; /*Register rn*/
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94 |
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unsigned int rd: 5; /*Destination register rd*/
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95 |
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unsigned int rs: 5; /*Register rs*/
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96 |
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unsigned int sh: 3; /*Shieft direction*/
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97 |
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unsigned int rm: 5; /*Register rm*/
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98 |
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} insn_dp_r_s_struct;
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99 |
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typedef struct _insn_mula_struct {
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/*Multiply and accumulate*/
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101 |
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int (*func) (struct _insn_mula_struct *s, proc_state *state);
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102 |
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unsigned int c: 5; /*Condition code*/
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103 |
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unsigned int MA: 2; /*Multiply accumulate*/
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104 |
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unsigned int MS: 2; /*Set cpsr*/
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105 |
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unsigned int rd: 5; /*Destination register rd*/
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106 |
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unsigned int rn: 5; /*Register rn*/
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107 |
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unsigned int rs: 5; /*Register rs*/
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108 |
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unsigned int rm: 5; /*Register rm*/
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109 |
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} insn_mula_struct;
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110 |
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typedef struct _insn_mull_struct {
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111 |
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/*Multiply long*/
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112 |
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int (*func) (struct _insn_mull_struct *s, proc_state *state);
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113 |
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unsigned int c: 5; /*Condition code*/
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114 |
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unsigned int MU: 2; /*Multiply unsigned*/
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115 |
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unsigned int MA: 2; /*Multiply accumulate*/
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116 |
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unsigned int MS: 2; /*Set cpsr*/
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117 |
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unsigned int rd: 5; /*Destination register rd*/
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118 |
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unsigned int rdl: 5; /*Destination register long*/
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119 |
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unsigned int rs: 5; /*Register rs*/
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120 |
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unsigned int rm: 5; /*Register rm*/
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121 |
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} insn_mull_struct;
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122 |
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typedef struct _insn_swp_struct {
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123 |
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/*Swap|swap byte*/
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124 |
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int (*func) (struct _insn_swp_struct *s, proc_state *state);
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125 |
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unsigned int c: 5; /*Condition code*/
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126 |
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unsigned int SB: 2; /*Swap byte*/
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127 |
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unsigned int rn: 5; /*Register rn*/
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128 |
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unsigned int rd: 5; /*Destination register rd*/
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129 |
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unsigned int sbz: 5; /**/
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130 |
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unsigned int rm: 5; /*Register rm*/
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131 |
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} insn_swp_struct;
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132 |
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typedef struct _insn_ld1_struct {
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133 |
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/*Load|Store halfword*/
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134 |
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int (*func) (struct _insn_ld1_struct *s, proc_state *state);
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135 |
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unsigned int c: 5; /*Condition code*/
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136 |
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unsigned int LSP: 2; /*pre-indexed*/
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137 |
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unsigned int LSU: 2; /*add/sub base '1'=add*/
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138 |
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unsigned int LSW: 2; /*writeback*/
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139 |
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unsigned int LSL: 2; /*Load|Store '1'=Load*/
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140 |
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unsigned int rn: 5; /*Register rn*/
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141 |
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unsigned int rd: 5; /*Destination register rd*/
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142 |
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unsigned int sbz: 5; /**/
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143 |
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unsigned int rm: 5; /*Register rm*/
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144 |
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} insn_ld1_struct;
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145 |
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typedef struct _insn_ld2_struct {
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146 |
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/*Load|Store halfword immidiate offset*/
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147 |
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int (*func) (struct _insn_ld2_struct *s, proc_state *state);
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148 |
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unsigned int c: 5; /*Condition code*/
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149 |
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unsigned int LSP: 2; /*pre-indexed*/
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150 |
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unsigned int LSU: 2; /*add/sub base '1'=add*/
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151 |
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unsigned int LSW: 2; /*writeback*/
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152 |
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unsigned int LSL: 2; /*Load|Store '1'=Load*/
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153 |
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unsigned int rn: 5; /*Register rn*/
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154 |
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unsigned int rd: 5; /*Destination register rd*/
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155 |
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unsigned int i81: 5; /*Immidiate8 part1*/
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156 |
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unsigned int i82: 5; /*Immidiate8 part2*/
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157 |
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} insn_ld2_struct;
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158 |
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typedef struct _insn_ld3_struct {
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159 |
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/*Load|Store two words register offset*/
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160 |
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int (*func) (struct _insn_ld3_struct *s, proc_state *state);
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161 |
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unsigned int c: 5; /*Condition code*/
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162 |
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unsigned int LSP: 2; /*pre-indexed*/
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163 |
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unsigned int LSU: 2; /*add/sub base '1'=add*/
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164 |
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unsigned int LSW: 2; /*writeback*/
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165 |
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unsigned int rn: 5; /*Register rn*/
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166 |
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unsigned int rd: 5; /*Destination register rd*/
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167 |
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unsigned int i81: 5; /*Immidiate8 part1*/
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168 |
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unsigned int S: 2; /*Signed|Unsigned '1'=signed*/
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169 |
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unsigned int i82: 5; /*Immidiate8 part2*/
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170 |
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} insn_ld3_struct;
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171 |
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typedef struct _insn_ld4_struct {
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172 |
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/*Load|Store signed halfword/byte register offset*/
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173 |
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int (*func) (struct _insn_ld4_struct *s, proc_state *state);
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174 |
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unsigned int c: 5; /*Condition code*/
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175 |
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unsigned int LSP: 2; /*pre-indexed*/
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176 |
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unsigned int LSU: 2; /*add/sub base '1'=add*/
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177 |
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unsigned int LSW: 2; /*writeback*/
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178 |
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unsigned int rn: 5; /*Register rn*/
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179 |
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unsigned int rd: 5; /*Destination register rd*/
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180 |
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unsigned int i81: 5; /*Immidiate8 part1*/
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181 |
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unsigned int H: 2; /*halfword|signedbyte '1'=halfword*/
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182 |
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unsigned int i82: 5; /*Immidiate8 part2*/
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183 |
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} insn_ld4_struct;
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184 |
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typedef struct _insn_ld5_struct {
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185 |
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/*Load|Store two words register offset*/
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186 |
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int (*func) (struct _insn_ld5_struct *s, proc_state *state);
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187 |
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unsigned int c: 5; /*Condition code*/
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188 |
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unsigned int LSP: 2; /*pre-indexed*/
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189 |
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unsigned int LSU: 2; /*add/sub base '1'=add*/
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190 |
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unsigned int LSW: 2; /*writeback*/
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191 |
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unsigned int rn: 5; /*Register rn*/
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192 |
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unsigned int rd: 5; /*Destination register rd*/
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193 |
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unsigned int i81: 5; /*Immidiate8 part1*/
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194 |
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unsigned int S: 2; /*Signed|Unsigned '1'=signed*/
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195 |
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unsigned int i82: 5; /*Immidiate8 part2*/
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196 |
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} insn_ld5_struct;
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197 |
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typedef struct _insn_ld6_struct {
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198 |
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/*Load|Store signed halfword/byte immidiate offset*/
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199 |
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int (*func) (struct _insn_ld6_struct *s, proc_state *state);
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200 |
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unsigned int c: 5; /*Condition code*/
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201 |
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unsigned int LSP: 2; /*pre-indexed*/
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202 |
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unsigned int LSU: 2; /*add/sub base '1'=add*/
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203 |
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unsigned int LSW: 2; /*writeback*/
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204 |
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unsigned int rn: 5; /*Register rn*/
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205 |
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unsigned int rd: 5; /*Destination register rd*/
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206 |
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unsigned int i81: 5; /*Immidiate8 part1*/
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207 |
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unsigned int H: 2; /*halfword|signedbyte '1'=halfword*/
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208 |
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unsigned int i82: 5; /*Immidiate8 part2*/
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209 |
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} insn_ld6_struct;
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210 |
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typedef struct _insn_dp_i_struct {
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211 |
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/*Data processing immidiate*/
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212 |
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int (*func) (struct _insn_dp_i_struct *s, proc_state *state);
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213 |
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unsigned int c: 5; /*Condition code*/
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214 |
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unsigned int op1: 5; /*Data processing opcode*/
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215 |
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unsigned int dps: 2; /*Update cpsr*/
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216 |
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unsigned int rn: 5; /*Register rn*/
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217 |
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unsigned int rd: 5; /*Destination register rd*/
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218 |
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unsigned int rot: 5; /*Immidiate8 rotate*/
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219 |
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unsigned int dpi: 9; /*Immidiate8*/
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220 |
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} insn_dp_i_struct;
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221 |
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typedef struct _insn_undef1_struct {
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222 |
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/*Undefined instruction*/
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223 |
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int (*func) (struct _insn_undef1_struct *s, proc_state *state);
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224 |
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unsigned int c: 5; /*Condition code*/
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225 |
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unsigned int X2: 2; /**/
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226 |
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unsigned int X: 21; /**/
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227 |
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} insn_undef1_struct;
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228 |
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typedef struct _insn_misr_struct {
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229 |
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/*Move immidiate to status register*/
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230 |
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int (*func) (struct _insn_misr_struct *s, proc_state *state);
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231 |
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unsigned int c: 5; /*Condition code*/
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232 |
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unsigned int R: 2; /*Cpsr|Spsr '1'=Spsr*/
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233 |
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unsigned int MSK: 5; /*move immidiate to status register mask*/
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234 |
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unsigned int SBQ: 5; /**/
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235 |
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unsigned int rot: 5; /*Immidiate8 rotate*/
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236 |
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unsigned int dpi: 9; /*Immidiate8*/
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237 |
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} insn_misr_struct;
|
238 |
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typedef struct _insn_lsio_struct {
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239 |
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/*Load|Store imidiate offset*/
|
240 |
|
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int (*func) (struct _insn_lsio_struct *s, proc_state *state);
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241 |
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unsigned int c: 5; /*Condition code*/
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242 |
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unsigned int LSP: 2; /*pre-indexed*/
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243 |
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unsigned int LSU: 2; /*add/sub base '1'=add*/
|
244 |
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unsigned int LSB: 2; /*Byte|word '1'=byte*/
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245 |
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unsigned int LSW: 2; /*writeback*/
|
246 |
|
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unsigned int LSL: 2; /*Load|Store '1'=Load*/
|
247 |
|
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unsigned int rn: 5; /*Register rn*/
|
248 |
|
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unsigned int rd: 5; /*Destination register rd*/
|
249 |
|
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unsigned int LSI: 13; /**/
|
250 |
|
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} insn_lsio_struct;
|
251 |
|
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typedef struct _insn_lsro_struct {
|
252 |
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/*Load|Store register offset*/
|
253 |
|
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int (*func) (struct _insn_lsro_struct *s, proc_state *state);
|
254 |
|
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unsigned int c: 5; /*Condition code*/
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255 |
|
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unsigned int LSP: 2; /*pre-indexed*/
|
256 |
|
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unsigned int LSU: 2; /*add/sub base '1'=add*/
|
257 |
|
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unsigned int LSB: 2; /*Byte|word '1'=byte*/
|
258 |
|
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unsigned int LSW: 2; /*writeback*/
|
259 |
|
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unsigned int LSL: 2; /*Load|Store '1'=Load*/
|
260 |
|
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unsigned int rn: 5; /*Register rn*/
|
261 |
|
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unsigned int rd: 5; /*Destination register rd*/
|
262 |
|
|
unsigned int sha: 6; /*Shieft amount*/
|
263 |
|
|
unsigned int sh: 3; /*Shieft direction*/
|
264 |
|
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unsigned int rm: 5; /*Register rm*/
|
265 |
|
|
} insn_lsro_struct;
|
266 |
|
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typedef struct _insn_undef2_struct {
|
267 |
|
|
/*Undefined instruction2*/
|
268 |
|
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int (*func) (struct _insn_undef2_struct *s, proc_state *state);
|
269 |
|
|
unsigned int c: 5; /*Condition code*/
|
270 |
|
|
unsigned int X: 21; /**/
|
271 |
|
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unsigned int X2: 5; /**/
|
272 |
|
|
} insn_undef2_struct;
|
273 |
|
|
typedef struct _insn_undef3_struct {
|
274 |
|
|
/*Undefined instruction3*/
|
275 |
|
|
int (*func) (struct _insn_undef3_struct *s, proc_state *state);
|
276 |
|
|
unsigned int X: 28; /**/
|
277 |
|
|
} insn_undef3_struct;
|
278 |
|
|
typedef struct _insn_lsm_struct {
|
279 |
|
|
/*Load|Store multiple*/
|
280 |
|
|
int (*func) (struct _insn_lsm_struct *s, proc_state *state);
|
281 |
|
|
unsigned int c: 5; /*Condition code*/
|
282 |
|
|
unsigned int LSP: 2; /*pre-indexed*/
|
283 |
|
|
unsigned int LSU: 2; /*add/sub base '1'=add*/
|
284 |
|
|
unsigned int LMS: 2; /*Set cpsr fro spsr*/
|
285 |
|
|
unsigned int LSW: 2; /*writeback*/
|
286 |
|
|
unsigned int LSL: 2; /*Load|Store '1'=Load*/
|
287 |
|
|
unsigned int rn: 5; /*Register rn*/
|
288 |
|
|
unsigned int rgl: 17; /*register list*/
|
289 |
|
|
} insn_lsm_struct;
|
290 |
|
|
typedef struct _insn_undef4_struct {
|
291 |
|
|
/*Undefined instruction4*/
|
292 |
|
|
int (*func) (struct _insn_undef4_struct *s, proc_state *state);
|
293 |
|
|
unsigned int X: 26; /**/
|
294 |
|
|
} insn_undef4_struct;
|
295 |
|
|
typedef struct _insn_bwl_struct {
|
296 |
|
|
/*Branch with link*/
|
297 |
|
|
int (*func) (struct _insn_bwl_struct *s, proc_state *state);
|
298 |
|
|
unsigned int c: 5; /*Condition code*/
|
299 |
|
|
unsigned int BLL: 2; /*Link*/
|
300 |
|
|
unsigned int blo: 25; /**/
|
301 |
|
|
} insn_bwl_struct;
|
302 |
|
|
typedef struct _insn_bwlth_struct {
|
303 |
|
|
/*Branch with link and change to thumb*/
|
304 |
|
|
int (*func) (struct _insn_bwlth_struct *s, proc_state *state);
|
305 |
|
|
unsigned int BLH: 2; /*Exchange*/
|
306 |
|
|
unsigned int blo: 25; /**/
|
307 |
|
|
} insn_bwlth_struct;
|
308 |
|
|
typedef struct _insn_cpldst_struct {
|
309 |
|
|
/*Coprocessor Load Store*/
|
310 |
|
|
int (*func) (struct _insn_cpldst_struct *s, proc_state *state);
|
311 |
|
|
unsigned int c: 5; /*Condition code*/
|
312 |
|
|
unsigned int LSP: 2; /*pre-indexed*/
|
313 |
|
|
unsigned int LSU: 2; /*add/sub base '1'=add*/
|
314 |
|
|
unsigned int Cp_N: 2; /*Coprocessor n bit*/
|
315 |
|
|
unsigned int LSW: 2; /*writeback*/
|
316 |
|
|
unsigned int LSL: 2; /*Load|Store '1'=Load*/
|
317 |
|
|
unsigned int rn: 5; /*Register rn*/
|
318 |
|
|
unsigned int crd: 5; /*Coprocessor destination register*/
|
319 |
|
|
unsigned int cpn: 5; /*Coprocessor number*/
|
320 |
|
|
unsigned int of8: 9; /*offset8*/
|
321 |
|
|
} insn_cpldst_struct;
|
322 |
|
|
typedef struct _insn_cpdp_struct {
|
323 |
|
|
/*Coprocessor data processing*/
|
324 |
|
|
int (*func) (struct _insn_cpdp_struct *s, proc_state *state);
|
325 |
|
|
unsigned int c: 5; /*Condition code*/
|
326 |
|
|
unsigned int co1: 5; /*Coprocessor op1*/
|
327 |
|
|
unsigned int crn: 5; /*Coprocessor register rn*/
|
328 |
|
|
unsigned int rd: 5; /*Destination register rd*/
|
329 |
|
|
unsigned int cpn: 5; /*Coprocessor number*/
|
330 |
|
|
unsigned int cp1: 4; /**/
|
331 |
|
|
unsigned int crm: 5; /*Coprocessor register rm*/
|
332 |
|
|
} insn_cpdp_struct;
|
333 |
|
|
typedef struct _insn_cpr_struct {
|
334 |
|
|
/*Coprocessor register transfer*/
|
335 |
|
|
int (*func) (struct _insn_cpr_struct *s, proc_state *state);
|
336 |
|
|
unsigned int c: 5; /*Condition code*/
|
337 |
|
|
unsigned int co1: 4; /*Coprocessor op1*/
|
338 |
|
|
unsigned int LSL: 2; /*Load|Store '1'=Load*/
|
339 |
|
|
unsigned int crn: 5; /*Coprocessor register rn*/
|
340 |
|
|
unsigned int rd: 5; /*Destination register rd*/
|
341 |
|
|
unsigned int cpn: 5; /*Coprocessor number*/
|
342 |
|
|
unsigned int cp1: 4; /**/
|
343 |
|
|
unsigned int crm: 5; /*Coprocessor register rm*/
|
344 |
|
|
} insn_cpr_struct;
|
345 |
|
|
typedef struct _insn_swi_struct {
|
346 |
|
|
/*Software interrupt*/
|
347 |
|
|
int (*func) (struct _insn_swi_struct *s, proc_state *state);
|
348 |
|
|
unsigned int c: 5; /*Condition code*/
|
349 |
|
|
unsigned int X: 25; /**/
|
350 |
|
|
} insn_swi_struct;
|
351 |
|
|
typedef struct _insn_undef_struct {
|
352 |
|
|
/*Undef*/
|
353 |
|
|
int (*func) (struct _insn_undef_struct *s, proc_state *state);
|
354 |
|
|
unsigned int X: 25; /**/
|
355 |
|
|
} insn_undef_struct;
|
356 |
|
|
typedef union _insn_union {
|
357 |
|
|
insn_dp_i_s_struct insn_dp_i_s;
|
358 |
|
|
insn_msr_struct insn_msr;
|
359 |
|
|
insn_mrs_struct insn_mrs;
|
360 |
|
|
insn_bex_struct insn_bex;
|
361 |
|
|
insn_clz_struct insn_clz;
|
362 |
|
|
insn_blx_struct insn_blx;
|
363 |
|
|
insn_dsa_struct insn_dsa;
|
364 |
|
|
insn_brk_struct insn_brk;
|
365 |
|
|
insn_dsm_struct insn_dsm;
|
366 |
|
|
insn_dp_r_s_struct insn_dp_r_s;
|
367 |
|
|
insn_mula_struct insn_mula;
|
368 |
|
|
insn_mull_struct insn_mull;
|
369 |
|
|
insn_swp_struct insn_swp;
|
370 |
|
|
insn_ld1_struct insn_ld1;
|
371 |
|
|
insn_ld2_struct insn_ld2;
|
372 |
|
|
insn_ld3_struct insn_ld3;
|
373 |
|
|
insn_ld4_struct insn_ld4;
|
374 |
|
|
insn_ld5_struct insn_ld5;
|
375 |
|
|
insn_ld6_struct insn_ld6;
|
376 |
|
|
insn_dp_i_struct insn_dp_i;
|
377 |
|
|
insn_undef1_struct insn_undef1;
|
378 |
|
|
insn_misr_struct insn_misr;
|
379 |
|
|
insn_lsio_struct insn_lsio;
|
380 |
|
|
insn_lsro_struct insn_lsro;
|
381 |
|
|
insn_undef2_struct insn_undef2;
|
382 |
|
|
insn_undef3_struct insn_undef3;
|
383 |
|
|
insn_lsm_struct insn_lsm;
|
384 |
|
|
insn_undef4_struct insn_undef4;
|
385 |
|
|
insn_bwl_struct insn_bwl;
|
386 |
|
|
insn_bwlth_struct insn_bwlth;
|
387 |
|
|
insn_cpldst_struct insn_cpldst;
|
388 |
|
|
insn_cpdp_struct insn_cpdp;
|
389 |
|
|
insn_cpr_struct insn_cpr;
|
390 |
|
|
insn_swi_struct insn_swi;
|
391 |
|
|
insn_undef_struct insn_undef;
|
392 |
|
|
} insn_union;
|
393 |
|
|
int func_insn_dp_i_s (struct _insn_dp_i_s_struct *s, proc_state *state) {
|
394 |
|
|
/*Data Processing immidiate shieft*/
|
395 |
|
|
};
|
396 |
|
|
int func_insn_msr (struct _insn_msr_struct *s, proc_state *state) {
|
397 |
|
|
/*Move status register to register*/
|
398 |
|
|
};
|
399 |
|
|
int func_insn_mrs (struct _insn_mrs_struct *s, proc_state *state) {
|
400 |
|
|
/*Move register to status register*/
|
401 |
|
|
};
|
402 |
|
|
int func_insn_bex (struct _insn_bex_struct *s, proc_state *state) {
|
403 |
|
|
/*Branch / exchange*/
|
404 |
|
|
};
|
405 |
|
|
int func_insn_clz (struct _insn_clz_struct *s, proc_state *state) {
|
406 |
|
|
/*Count leading zero*/
|
407 |
|
|
};
|
408 |
|
|
int func_insn_blx (struct _insn_blx_struct *s, proc_state *state) {
|
409 |
|
|
/*Branch and link /exchange*/
|
410 |
|
|
};
|
411 |
|
|
int func_insn_dsa (struct _insn_dsa_struct *s, proc_state *state) {
|
412 |
|
|
/*Dsp add|sub*/
|
413 |
|
|
};
|
414 |
|
|
int func_insn_brk (struct _insn_brk_struct *s, proc_state *state) {
|
415 |
|
|
/*Breakpoint*/
|
416 |
|
|
};
|
417 |
|
|
int func_insn_dsm (struct _insn_dsm_struct *s, proc_state *state) {
|
418 |
|
|
/*DSP multiply*/
|
419 |
|
|
};
|
420 |
|
|
int func_insn_dp_r_s (struct _insn_dp_r_s_struct *s, proc_state *state) {
|
421 |
|
|
/*Data processing register shieft*/
|
422 |
|
|
};
|
423 |
|
|
int func_insn_mula (struct _insn_mula_struct *s, proc_state *state) {
|
424 |
|
|
/*Multiply and accumulate*/
|
425 |
|
|
};
|
426 |
|
|
int func_insn_mull (struct _insn_mull_struct *s, proc_state *state) {
|
427 |
|
|
/*Multiply long*/
|
428 |
|
|
};
|
429 |
|
|
int func_insn_swp (struct _insn_swp_struct *s, proc_state *state) {
|
430 |
|
|
/*Swap|swap byte*/
|
431 |
|
|
};
|
432 |
|
|
int func_insn_ld1 (struct _insn_ld1_struct *s, proc_state *state) {
|
433 |
|
|
/*Load|Store halfword*/
|
434 |
|
|
};
|
435 |
|
|
int func_insn_ld2 (struct _insn_ld2_struct *s, proc_state *state) {
|
436 |
|
|
/*Load|Store halfword immidiate offset*/
|
437 |
|
|
};
|
438 |
|
|
int func_insn_ld3 (struct _insn_ld3_struct *s, proc_state *state) {
|
439 |
|
|
/*Load|Store two words register offset*/
|
440 |
|
|
};
|
441 |
|
|
int func_insn_ld4 (struct _insn_ld4_struct *s, proc_state *state) {
|
442 |
|
|
/*Load|Store signed halfword/byte register offset*/
|
443 |
|
|
};
|
444 |
|
|
int func_insn_ld5 (struct _insn_ld5_struct *s, proc_state *state) {
|
445 |
|
|
/*Load|Store two words register offset*/
|
446 |
|
|
};
|
447 |
|
|
int func_insn_ld6 (struct _insn_ld6_struct *s, proc_state *state) {
|
448 |
|
|
/*Load|Store signed halfword/byte immidiate offset*/
|
449 |
|
|
};
|
450 |
|
|
int func_insn_dp_i (struct _insn_dp_i_struct *s, proc_state *state) {
|
451 |
|
|
/*Data processing immidiate*/
|
452 |
|
|
};
|
453 |
|
|
int func_insn_undef1 (struct _insn_undef1_struct *s, proc_state *state) {
|
454 |
|
|
/*Undefined instruction*/
|
455 |
|
|
};
|
456 |
|
|
int func_insn_misr (struct _insn_misr_struct *s, proc_state *state) {
|
457 |
|
|
/*Move immidiate to status register*/
|
458 |
|
|
};
|
459 |
|
|
int func_insn_lsio (struct _insn_lsio_struct *s, proc_state *state) {
|
460 |
|
|
/*Load|Store imidiate offset*/
|
461 |
|
|
};
|
462 |
|
|
int func_insn_lsro (struct _insn_lsro_struct *s, proc_state *state) {
|
463 |
|
|
/*Load|Store register offset*/
|
464 |
|
|
};
|
465 |
|
|
int func_insn_undef2 (struct _insn_undef2_struct *s, proc_state *state) {
|
466 |
|
|
/*Undefined instruction2*/
|
467 |
|
|
};
|
468 |
|
|
int func_insn_undef3 (struct _insn_undef3_struct *s, proc_state *state) {
|
469 |
|
|
/*Undefined instruction3*/
|
470 |
|
|
};
|
471 |
|
|
int func_insn_lsm (struct _insn_lsm_struct *s, proc_state *state) {
|
472 |
|
|
/*Load|Store multiple*/
|
473 |
|
|
};
|
474 |
|
|
int func_insn_undef4 (struct _insn_undef4_struct *s, proc_state *state) {
|
475 |
|
|
/*Undefined instruction4*/
|
476 |
|
|
};
|
477 |
|
|
int func_insn_bwl (struct _insn_bwl_struct *s, proc_state *state) {
|
478 |
|
|
/*Branch with link*/
|
479 |
|
|
};
|
480 |
|
|
int func_insn_bwlth (struct _insn_bwlth_struct *s, proc_state *state) {
|
481 |
|
|
/*Branch with link and change to thumb*/
|
482 |
|
|
};
|
483 |
|
|
int func_insn_cpldst (struct _insn_cpldst_struct *s, proc_state *state) {
|
484 |
|
|
/*Coprocessor Load Store*/
|
485 |
|
|
};
|
486 |
|
|
int func_insn_cpdp (struct _insn_cpdp_struct *s, proc_state *state) {
|
487 |
|
|
/*Coprocessor data processing*/
|
488 |
|
|
};
|
489 |
|
|
int func_insn_cpr (struct _insn_cpr_struct *s, proc_state *state) {
|
490 |
|
|
/*Coprocessor register transfer*/
|
491 |
|
|
};
|
492 |
|
|
int func_insn_swi (struct _insn_swi_struct *s, proc_state *state) {
|
493 |
|
|
/*Software interrupt*/
|
494 |
|
|
};
|
495 |
|
|
int func_insn_undef (struct _insn_undef_struct *s, proc_state *state) {
|
496 |
|
|
/*Undef*/
|
497 |
|
|
};
|
498 |
|
|
unsigned int init_insn_dp_i_s(unsigned int insn, insn_union *s) {
|
499 |
|
|
s->insn_dp_i_s.func=func_insn_dp_i_s;
|
500 |
|
|
s->insn_dp_i_s.c=((insn>>28)&0xf);
|
501 |
|
|
s->insn_dp_i_s.op1=((insn>>21)&0xf);
|
502 |
|
|
s->insn_dp_i_s.dps=((insn>>20)&0x1);
|
503 |
|
|
s->insn_dp_i_s.rn=((insn>>16)&0xf);
|
504 |
|
|
s->insn_dp_i_s.rd=((insn>>12)&0xf);
|
505 |
|
|
s->insn_dp_i_s.sha=((insn>>7)&0x1f);
|
506 |
|
|
s->insn_dp_i_s.sh=((insn>>5)&0x3);
|
507 |
|
|
s->insn_dp_i_s.rm=((insn>>0)&0xf);
|
508 |
|
|
return 1;};
|
509 |
|
|
unsigned int init_insn_msr(unsigned int insn, insn_union *s) {
|
510 |
|
|
s->insn_msr.func=func_insn_msr;
|
511 |
|
|
s->insn_msr.c=((insn>>28)&0xf);
|
512 |
|
|
s->insn_msr.R=((insn>>22)&0x1);
|
513 |
|
|
s->insn_msr.SBO=((insn>>16)&0xf);
|
514 |
|
|
s->insn_msr.rd=((insn>>12)&0xf);
|
515 |
|
|
s->insn_msr.SBZ=((insn>>8)&0xf);
|
516 |
|
|
s->insn_msr.SBZ2=((insn>>0)&0xf);
|
517 |
|
|
return 1;};
|
518 |
|
|
unsigned int init_insn_mrs(unsigned int insn, insn_union *s) {
|
519 |
|
|
s->insn_mrs.func=func_insn_mrs;
|
520 |
|
|
s->insn_mrs.c=((insn>>28)&0xf);
|
521 |
|
|
s->insn_mrs.R=((insn>>22)&0x1);
|
522 |
|
|
s->insn_mrs.msk=((insn>>16)&0xf);
|
523 |
|
|
s->insn_mrs.SBO=((insn>>12)&0xf);
|
524 |
|
|
s->insn_mrs.SBZ=((insn>>8)&0xf);
|
525 |
|
|
s->insn_mrs.rm=((insn>>0)&0xf);
|
526 |
|
|
return 1;};
|
527 |
|
|
unsigned int init_insn_bex(unsigned int insn, insn_union *s) {
|
528 |
|
|
s->insn_bex.func=func_insn_bex;
|
529 |
|
|
s->insn_bex.c=((insn>>28)&0xf);
|
530 |
|
|
s->insn_bex.SBO=((insn>>8)&0xfff);
|
531 |
|
|
s->insn_bex.rm=((insn>>0)&0xf);
|
532 |
|
|
return 1;};
|
533 |
|
|
unsigned int init_insn_clz(unsigned int insn, insn_union *s) {
|
534 |
|
|
s->insn_clz.func=func_insn_clz;
|
535 |
|
|
s->insn_clz.c=((insn>>28)&0xf);
|
536 |
|
|
s->insn_clz.SBO=((insn>>16)&0xf);
|
537 |
|
|
s->insn_clz.rd=((insn>>12)&0xf);
|
538 |
|
|
s->insn_clz.SBO2=((insn>>8)&0xf);
|
539 |
|
|
s->insn_clz.rm=((insn>>0)&0xf);
|
540 |
|
|
return 1;};
|
541 |
|
|
unsigned int init_insn_blx(unsigned int insn, insn_union *s) {
|
542 |
|
|
s->insn_blx.func=func_insn_blx;
|
543 |
|
|
s->insn_blx.c=((insn>>28)&0xf);
|
544 |
|
|
s->insn_blx.SBO=((insn>>8)&0xfff);
|
545 |
|
|
s->insn_blx.rm=((insn>>0)&0xf);
|
546 |
|
|
return 1;};
|
547 |
|
|
unsigned int init_insn_dsa(unsigned int insn, insn_union *s) {
|
548 |
|
|
s->insn_dsa.func=func_insn_dsa;
|
549 |
|
|
s->insn_dsa.c=((insn>>28)&0xf);
|
550 |
|
|
s->insn_dsa.dsop=((insn>>21)&0x3);
|
551 |
|
|
s->insn_dsa.rn=((insn>>16)&0xf);
|
552 |
|
|
s->insn_dsa.rd=((insn>>12)&0xf);
|
553 |
|
|
s->insn_dsa.SBZ=((insn>>8)&0xf);
|
554 |
|
|
s->insn_dsa.rm=((insn>>0)&0xf);
|
555 |
|
|
return 1;};
|
556 |
|
|
unsigned int init_insn_brk(unsigned int insn, insn_union *s) {
|
557 |
|
|
s->insn_brk.func=func_insn_brk;
|
558 |
|
|
s->insn_brk.c=((insn>>28)&0xf);
|
559 |
|
|
s->insn_brk.imm=((insn>>8)&0xfff);
|
560 |
|
|
s->insn_brk.imm2=((insn>>0)&0xf);
|
561 |
|
|
return 1;};
|
562 |
|
|
unsigned int init_insn_dsm(unsigned int insn, insn_union *s) {
|
563 |
|
|
s->insn_dsm.func=func_insn_dsm;
|
564 |
|
|
s->insn_dsm.c=((insn>>28)&0xf);
|
565 |
|
|
s->insn_dsm.dsop=((insn>>21)&0x3);
|
566 |
|
|
s->insn_dsm.RD=((insn>>16)&0xf);
|
567 |
|
|
s->insn_dsm.rn=((insn>>12)&0xf);
|
568 |
|
|
s->insn_dsm.rs=((insn>>8)&0xf);
|
569 |
|
|
s->insn_dsm.y=((insn>>6)&0x1);
|
570 |
|
|
s->insn_dsm.x=((insn>>5)&0x1);
|
571 |
|
|
s->insn_dsm.rm=((insn>>0)&0xf);
|
572 |
|
|
return 1;};
|
573 |
|
|
unsigned int init_insn_dp_r_s(unsigned int insn, insn_union *s) {
|
574 |
|
|
s->insn_dp_r_s.func=func_insn_dp_r_s;
|
575 |
|
|
s->insn_dp_r_s.c=((insn>>28)&0xf);
|
576 |
|
|
s->insn_dp_r_s.op1=((insn>>21)&0xf);
|
577 |
|
|
s->insn_dp_r_s.dps=((insn>>20)&0x1);
|
578 |
|
|
s->insn_dp_r_s.rn=((insn>>16)&0xf);
|
579 |
|
|
s->insn_dp_r_s.rd=((insn>>12)&0xf);
|
580 |
|
|
s->insn_dp_r_s.rs=((insn>>8)&0xf);
|
581 |
|
|
s->insn_dp_r_s.sh=((insn>>5)&0x3);
|
582 |
|
|
s->insn_dp_r_s.rm=((insn>>0)&0xf);
|
583 |
|
|
return 1;};
|
584 |
|
|
unsigned int init_insn_mula(unsigned int insn, insn_union *s) {
|
585 |
|
|
s->insn_mula.func=func_insn_mula;
|
586 |
|
|
s->insn_mula.c=((insn>>28)&0xf);
|
587 |
|
|
s->insn_mula.MA=((insn>>21)&0x1);
|
588 |
|
|
s->insn_mula.MS=((insn>>20)&0x1);
|
589 |
|
|
s->insn_mula.rd=((insn>>16)&0xf);
|
590 |
|
|
s->insn_mula.rn=((insn>>12)&0xf);
|
591 |
|
|
s->insn_mula.rs=((insn>>8)&0xf);
|
592 |
|
|
s->insn_mula.rm=((insn>>0)&0xf);
|
593 |
|
|
return 1;};
|
594 |
|
|
unsigned int init_insn_mull(unsigned int insn, insn_union *s) {
|
595 |
|
|
s->insn_mull.func=func_insn_mull;
|
596 |
|
|
s->insn_mull.c=((insn>>28)&0xf);
|
597 |
|
|
s->insn_mull.MU=((insn>>22)&0x1);
|
598 |
|
|
s->insn_mull.MA=((insn>>21)&0x1);
|
599 |
|
|
s->insn_mull.MS=((insn>>20)&0x1);
|
600 |
|
|
s->insn_mull.rd=((insn>>16)&0xf);
|
601 |
|
|
s->insn_mull.rdl=((insn>>12)&0xf);
|
602 |
|
|
s->insn_mull.rs=((insn>>8)&0xf);
|
603 |
|
|
s->insn_mull.rm=((insn>>0)&0xf);
|
604 |
|
|
return 1;};
|
605 |
|
|
unsigned int init_insn_swp(unsigned int insn, insn_union *s) {
|
606 |
|
|
s->insn_swp.func=func_insn_swp;
|
607 |
|
|
s->insn_swp.c=((insn>>28)&0xf);
|
608 |
|
|
s->insn_swp.SB=((insn>>22)&0x1);
|
609 |
|
|
s->insn_swp.rn=((insn>>16)&0xf);
|
610 |
|
|
s->insn_swp.rd=((insn>>12)&0xf);
|
611 |
|
|
s->insn_swp.sbz=((insn>>8)&0xf);
|
612 |
|
|
s->insn_swp.rm=((insn>>0)&0xf);
|
613 |
|
|
return 1;};
|
614 |
|
|
unsigned int init_insn_ld1(unsigned int insn, insn_union *s) {
|
615 |
|
|
s->insn_ld1.func=func_insn_ld1;
|
616 |
|
|
s->insn_ld1.c=((insn>>28)&0xf);
|
617 |
|
|
s->insn_ld1.LSP=((insn>>24)&0x1);
|
618 |
|
|
s->insn_ld1.LSU=((insn>>23)&0x1);
|
619 |
|
|
s->insn_ld1.LSW=((insn>>21)&0x1);
|
620 |
|
|
s->insn_ld1.LSL=((insn>>20)&0x1);
|
621 |
|
|
s->insn_ld1.rn=((insn>>16)&0xf);
|
622 |
|
|
s->insn_ld1.rd=((insn>>12)&0xf);
|
623 |
|
|
s->insn_ld1.sbz=((insn>>8)&0xf);
|
624 |
|
|
s->insn_ld1.rm=((insn>>0)&0xf);
|
625 |
|
|
return 1;};
|
626 |
|
|
unsigned int init_insn_ld2(unsigned int insn, insn_union *s) {
|
627 |
|
|
s->insn_ld2.func=func_insn_ld2;
|
628 |
|
|
s->insn_ld2.c=((insn>>28)&0xf);
|
629 |
|
|
s->insn_ld2.LSP=((insn>>24)&0x1);
|
630 |
|
|
s->insn_ld2.LSU=((insn>>23)&0x1);
|
631 |
|
|
s->insn_ld2.LSW=((insn>>21)&0x1);
|
632 |
|
|
s->insn_ld2.LSL=((insn>>20)&0x1);
|
633 |
|
|
s->insn_ld2.rn=((insn>>16)&0xf);
|
634 |
|
|
s->insn_ld2.rd=((insn>>12)&0xf);
|
635 |
|
|
s->insn_ld2.i81=((insn>>8)&0xf);
|
636 |
|
|
s->insn_ld2.i82=((insn>>0)&0xf);
|
637 |
|
|
return 1;};
|
638 |
|
|
unsigned int init_insn_ld3(unsigned int insn, insn_union *s) {
|
639 |
|
|
s->insn_ld3.func=func_insn_ld3;
|
640 |
|
|
s->insn_ld3.c=((insn>>28)&0xf);
|
641 |
|
|
s->insn_ld3.LSP=((insn>>24)&0x1);
|
642 |
|
|
s->insn_ld3.LSU=((insn>>23)&0x1);
|
643 |
|
|
s->insn_ld3.LSW=((insn>>21)&0x1);
|
644 |
|
|
s->insn_ld3.rn=((insn>>16)&0xf);
|
645 |
|
|
s->insn_ld3.rd=((insn>>12)&0xf);
|
646 |
|
|
s->insn_ld3.i81=((insn>>8)&0xf);
|
647 |
|
|
s->insn_ld3.S=((insn>>5)&0x1);
|
648 |
|
|
s->insn_ld3.i82=((insn>>0)&0xf);
|
649 |
|
|
return 1;};
|
650 |
|
|
unsigned int init_insn_ld4(unsigned int insn, insn_union *s) {
|
651 |
|
|
s->insn_ld4.func=func_insn_ld4;
|
652 |
|
|
s->insn_ld4.c=((insn>>28)&0xf);
|
653 |
|
|
s->insn_ld4.LSP=((insn>>24)&0x1);
|
654 |
|
|
s->insn_ld4.LSU=((insn>>23)&0x1);
|
655 |
|
|
s->insn_ld4.LSW=((insn>>21)&0x1);
|
656 |
|
|
s->insn_ld4.rn=((insn>>16)&0xf);
|
657 |
|
|
s->insn_ld4.rd=((insn>>12)&0xf);
|
658 |
|
|
s->insn_ld4.i81=((insn>>8)&0xf);
|
659 |
|
|
s->insn_ld4.H=((insn>>5)&0x1);
|
660 |
|
|
s->insn_ld4.i82=((insn>>0)&0xf);
|
661 |
|
|
return 1;};
|
662 |
|
|
unsigned int init_insn_ld5(unsigned int insn, insn_union *s) {
|
663 |
|
|
s->insn_ld5.func=func_insn_ld5;
|
664 |
|
|
s->insn_ld5.c=((insn>>28)&0xf);
|
665 |
|
|
s->insn_ld5.LSP=((insn>>24)&0x1);
|
666 |
|
|
s->insn_ld5.LSU=((insn>>23)&0x1);
|
667 |
|
|
s->insn_ld5.LSW=((insn>>21)&0x1);
|
668 |
|
|
s->insn_ld5.rn=((insn>>16)&0xf);
|
669 |
|
|
s->insn_ld5.rd=((insn>>12)&0xf);
|
670 |
|
|
s->insn_ld5.i81=((insn>>8)&0xf);
|
671 |
|
|
s->insn_ld5.S=((insn>>5)&0x1);
|
672 |
|
|
s->insn_ld5.i82=((insn>>0)&0xf);
|
673 |
|
|
return 1;};
|
674 |
|
|
unsigned int init_insn_ld6(unsigned int insn, insn_union *s) {
|
675 |
|
|
s->insn_ld6.func=func_insn_ld6;
|
676 |
|
|
s->insn_ld6.c=((insn>>28)&0xf);
|
677 |
|
|
s->insn_ld6.LSP=((insn>>24)&0x1);
|
678 |
|
|
s->insn_ld6.LSU=((insn>>23)&0x1);
|
679 |
|
|
s->insn_ld6.LSW=((insn>>21)&0x1);
|
680 |
|
|
s->insn_ld6.rn=((insn>>16)&0xf);
|
681 |
|
|
s->insn_ld6.rd=((insn>>12)&0xf);
|
682 |
|
|
s->insn_ld6.i81=((insn>>8)&0xf);
|
683 |
|
|
s->insn_ld6.H=((insn>>5)&0x1);
|
684 |
|
|
s->insn_ld6.i82=((insn>>0)&0xf);
|
685 |
|
|
return 1;};
|
686 |
|
|
unsigned int init_insn_dp_i(unsigned int insn, insn_union *s) {
|
687 |
|
|
s->insn_dp_i.func=func_insn_dp_i;
|
688 |
|
|
s->insn_dp_i.c=((insn>>28)&0xf);
|
689 |
|
|
s->insn_dp_i.op1=((insn>>21)&0xf);
|
690 |
|
|
s->insn_dp_i.dps=((insn>>20)&0x1);
|
691 |
|
|
s->insn_dp_i.rn=((insn>>16)&0xf);
|
692 |
|
|
s->insn_dp_i.rd=((insn>>12)&0xf);
|
693 |
|
|
s->insn_dp_i.rot=((insn>>8)&0xf);
|
694 |
|
|
s->insn_dp_i.dpi=((insn>>0)&0xff);
|
695 |
|
|
return 1;};
|
696 |
|
|
unsigned int init_insn_undef1(unsigned int insn, insn_union *s) {
|
697 |
|
|
s->insn_undef1.func=func_insn_undef1;
|
698 |
|
|
s->insn_undef1.c=((insn>>28)&0xf);
|
699 |
|
|
s->insn_undef1.X2=((insn>>22)&0x1);
|
700 |
|
|
s->insn_undef1.X=((insn>>0)&0xfffff);
|
701 |
|
|
return 1;};
|
702 |
|
|
unsigned int init_insn_misr(unsigned int insn, insn_union *s) {
|
703 |
|
|
s->insn_misr.func=func_insn_misr;
|
704 |
|
|
s->insn_misr.c=((insn>>28)&0xf);
|
705 |
|
|
s->insn_misr.R=((insn>>22)&0x1);
|
706 |
|
|
s->insn_misr.MSK=((insn>>16)&0xf);
|
707 |
|
|
s->insn_misr.SBQ=((insn>>12)&0xf);
|
708 |
|
|
s->insn_misr.rot=((insn>>8)&0xf);
|
709 |
|
|
s->insn_misr.dpi=((insn>>0)&0xff);
|
710 |
|
|
return 1;};
|
711 |
|
|
unsigned int init_insn_lsio(unsigned int insn, insn_union *s) {
|
712 |
|
|
s->insn_lsio.func=func_insn_lsio;
|
713 |
|
|
s->insn_lsio.c=((insn>>28)&0xf);
|
714 |
|
|
s->insn_lsio.LSP=((insn>>24)&0x1);
|
715 |
|
|
s->insn_lsio.LSU=((insn>>23)&0x1);
|
716 |
|
|
s->insn_lsio.LSB=((insn>>22)&0x1);
|
717 |
|
|
s->insn_lsio.LSW=((insn>>21)&0x1);
|
718 |
|
|
s->insn_lsio.LSL=((insn>>20)&0x1);
|
719 |
|
|
s->insn_lsio.rn=((insn>>16)&0xf);
|
720 |
|
|
s->insn_lsio.rd=((insn>>12)&0xf);
|
721 |
|
|
s->insn_lsio.LSI=((insn>>0)&0xfff);
|
722 |
|
|
return 1;};
|
723 |
|
|
unsigned int init_insn_lsro(unsigned int insn, insn_union *s) {
|
724 |
|
|
s->insn_lsro.func=func_insn_lsro;
|
725 |
|
|
s->insn_lsro.c=((insn>>28)&0xf);
|
726 |
|
|
s->insn_lsro.LSP=((insn>>24)&0x1);
|
727 |
|
|
s->insn_lsro.LSU=((insn>>23)&0x1);
|
728 |
|
|
s->insn_lsro.LSB=((insn>>22)&0x1);
|
729 |
|
|
s->insn_lsro.LSW=((insn>>21)&0x1);
|
730 |
|
|
s->insn_lsro.LSL=((insn>>20)&0x1);
|
731 |
|
|
s->insn_lsro.rn=((insn>>16)&0xf);
|
732 |
|
|
s->insn_lsro.rd=((insn>>12)&0xf);
|
733 |
|
|
s->insn_lsro.sha=((insn>>7)&0x1f);
|
734 |
|
|
s->insn_lsro.sh=((insn>>5)&0x3);
|
735 |
|
|
s->insn_lsro.rm=((insn>>0)&0xf);
|
736 |
|
|
return 1;};
|
737 |
|
|
unsigned int init_insn_undef2(unsigned int insn, insn_union *s) {
|
738 |
|
|
s->insn_undef2.func=func_insn_undef2;
|
739 |
|
|
s->insn_undef2.c=((insn>>28)&0xf);
|
740 |
|
|
s->insn_undef2.X=((insn>>5)&0xfffff);
|
741 |
|
|
s->insn_undef2.X2=((insn>>0)&0xf);
|
742 |
|
|
return 1;};
|
743 |
|
|
unsigned int init_insn_undef3(unsigned int insn, insn_union *s) {
|
744 |
|
|
s->insn_undef3.func=func_insn_undef3;
|
745 |
|
|
s->insn_undef3.X=((insn>>0)&0x7ffffff);
|
746 |
|
|
return 1;};
|
747 |
|
|
unsigned int init_insn_lsm(unsigned int insn, insn_union *s) {
|
748 |
|
|
s->insn_lsm.func=func_insn_lsm;
|
749 |
|
|
s->insn_lsm.c=((insn>>28)&0xf);
|
750 |
|
|
s->insn_lsm.LSP=((insn>>24)&0x1);
|
751 |
|
|
s->insn_lsm.LSU=((insn>>23)&0x1);
|
752 |
|
|
s->insn_lsm.LMS=((insn>>22)&0x1);
|
753 |
|
|
s->insn_lsm.LSW=((insn>>21)&0x1);
|
754 |
|
|
s->insn_lsm.LSL=((insn>>20)&0x1);
|
755 |
|
|
s->insn_lsm.rn=((insn>>16)&0xf);
|
756 |
|
|
s->insn_lsm.rgl=((insn>>0)&0xffff);
|
757 |
|
|
return 1;};
|
758 |
|
|
unsigned int init_insn_undef4(unsigned int insn, insn_union *s) {
|
759 |
|
|
s->insn_undef4.func=func_insn_undef4;
|
760 |
|
|
s->insn_undef4.X=((insn>>0)&0x1ffffff);
|
761 |
|
|
return 1;};
|
762 |
|
|
unsigned int init_insn_bwl(unsigned int insn, insn_union *s) {
|
763 |
|
|
s->insn_bwl.func=func_insn_bwl;
|
764 |
|
|
s->insn_bwl.c=((insn>>28)&0xf);
|
765 |
|
|
s->insn_bwl.BLL=((insn>>24)&0x1);
|
766 |
|
|
s->insn_bwl.blo=((insn>>0)&0xffffff);
|
767 |
|
|
return 1;};
|
768 |
|
|
unsigned int init_insn_bwlth(unsigned int insn, insn_union *s) {
|
769 |
|
|
s->insn_bwlth.func=func_insn_bwlth;
|
770 |
|
|
s->insn_bwlth.BLH=((insn>>24)&0x1);
|
771 |
|
|
s->insn_bwlth.blo=((insn>>0)&0xffffff);
|
772 |
|
|
return 1;};
|
773 |
|
|
unsigned int init_insn_cpldst(unsigned int insn, insn_union *s) {
|
774 |
|
|
s->insn_cpldst.func=func_insn_cpldst;
|
775 |
|
|
s->insn_cpldst.c=((insn>>28)&0xf);
|
776 |
|
|
s->insn_cpldst.LSP=((insn>>24)&0x1);
|
777 |
|
|
s->insn_cpldst.LSU=((insn>>23)&0x1);
|
778 |
|
|
s->insn_cpldst.Cp_N=((insn>>22)&0x1);
|
779 |
|
|
s->insn_cpldst.LSW=((insn>>21)&0x1);
|
780 |
|
|
s->insn_cpldst.LSL=((insn>>20)&0x1);
|
781 |
|
|
s->insn_cpldst.rn=((insn>>16)&0xf);
|
782 |
|
|
s->insn_cpldst.crd=((insn>>12)&0xf);
|
783 |
|
|
s->insn_cpldst.cpn=((insn>>8)&0xf);
|
784 |
|
|
s->insn_cpldst.of8=((insn>>0)&0xff);
|
785 |
|
|
return 1;};
|
786 |
|
|
unsigned int init_insn_cpdp(unsigned int insn, insn_union *s) {
|
787 |
|
|
s->insn_cpdp.func=func_insn_cpdp;
|
788 |
|
|
s->insn_cpdp.c=((insn>>28)&0xf);
|
789 |
|
|
s->insn_cpdp.co1=((insn>>20)&0xf);
|
790 |
|
|
s->insn_cpdp.crn=((insn>>16)&0xf);
|
791 |
|
|
s->insn_cpdp.rd=((insn>>12)&0xf);
|
792 |
|
|
s->insn_cpdp.cpn=((insn>>8)&0xf);
|
793 |
|
|
s->insn_cpdp.cp1=((insn>>5)&0x7);
|
794 |
|
|
s->insn_cpdp.crm=((insn>>0)&0xf);
|
795 |
|
|
return 1;};
|
796 |
|
|
unsigned int init_insn_cpr(unsigned int insn, insn_union *s) {
|
797 |
|
|
s->insn_cpr.func=func_insn_cpr;
|
798 |
|
|
s->insn_cpr.c=((insn>>28)&0xf);
|
799 |
|
|
s->insn_cpr.co1=((insn>>21)&0x7);
|
800 |
|
|
s->insn_cpr.LSL=((insn>>20)&0x1);
|
801 |
|
|
s->insn_cpr.crn=((insn>>16)&0xf);
|
802 |
|
|
s->insn_cpr.rd=((insn>>12)&0xf);
|
803 |
|
|
s->insn_cpr.cpn=((insn>>8)&0xf);
|
804 |
|
|
s->insn_cpr.cp1=((insn>>5)&0x7);
|
805 |
|
|
s->insn_cpr.crm=((insn>>0)&0xf);
|
806 |
|
|
return 1;};
|
807 |
|
|
unsigned int init_insn_swi(unsigned int insn, insn_union *s) {
|
808 |
|
|
s->insn_swi.func=func_insn_swi;
|
809 |
|
|
s->insn_swi.c=((insn>>28)&0xf);
|
810 |
|
|
s->insn_swi.X=((insn>>0)&0xffffff);
|
811 |
|
|
return 1;};
|
812 |
|
|
unsigned int init_insn_undef(unsigned int insn, insn_union *s) {
|
813 |
|
|
s->insn_undef.func=func_insn_undef;
|
814 |
|
|
s->insn_undef.X=((insn>>0)&0xffffff);
|
815 |
|
|
return 1;};
|
816 |
|
|
|
817 |
|
|
|
818 |
|
|
|
819 |
|
|
|
820 |
|
|
|
821 |
|
|
|
822 |
|
|
|
823 |
|
|
|
824 |
|
|
unsigned int decode(unsigned int insn, insn_union *s) {
|
825 |
|
|
{
|
826 |
|
|
switch (((insn>>27)&0x1)) {
|
827 |
|
|
case 0x1:
|
828 |
|
|
{
|
829 |
|
|
{
|
830 |
|
|
switch (((insn>>25)&0x3)) {
|
831 |
|
|
case 0x3:
|
832 |
|
|
{
|
833 |
|
|
{
|
834 |
|
|
switch (((insn>>24)&0x1)) {
|
835 |
|
|
case 0x1:
|
836 |
|
|
{
|
837 |
|
|
{
|
838 |
|
|
switch (((insn>>28)&0xf)) {
|
839 |
|
|
case 0xf:
|
840 |
|
|
{return init_insn_undef(insn,s);
|
841 |
|
|
};break;
|
842 |
|
|
}}
|
843 |
|
|
/*default:*/ return init_insn_swi(insn,s);
|
844 |
|
|
};break;
|
845 |
|
|
}}
|
846 |
|
|
};break;
|
847 |
|
|
case 0x1:
|
848 |
|
|
{
|
849 |
|
|
{
|
850 |
|
|
switch (((insn>>24)&0x1)) {
|
851 |
|
|
case 0x0:
|
852 |
|
|
{
|
853 |
|
|
{
|
854 |
|
|
switch (((insn>>4)&0x1)) {
|
855 |
|
|
case 0x1:
|
856 |
|
|
{return init_insn_cpr(insn,s);
|
857 |
|
|
};break;
|
858 |
|
|
case 0x0:
|
859 |
|
|
{return init_insn_cpdp(insn,s);
|
860 |
|
|
};break;
|
861 |
|
|
}}
|
862 |
|
|
};break;
|
863 |
|
|
}}
|
864 |
|
|
/*default:*/ return init_insn_cpldst(insn,s);
|
865 |
|
|
};break;
|
866 |
|
|
case 0x2:
|
867 |
|
|
{
|
868 |
|
|
{
|
869 |
|
|
switch (((insn>>28)&0xf)) {
|
870 |
|
|
case 0xf:
|
871 |
|
|
{return init_insn_bwlth(insn,s);
|
872 |
|
|
};break;
|
873 |
|
|
}}
|
874 |
|
|
/*default:*/ return init_insn_bwl(insn,s);
|
875 |
|
|
};break;
|
876 |
|
|
case 0x0:
|
877 |
|
|
{
|
878 |
|
|
{
|
879 |
|
|
switch (((insn>>28)&0xf)) {
|
880 |
|
|
case 0xf:
|
881 |
|
|
{return init_insn_undef4(insn,s);
|
882 |
|
|
};break;
|
883 |
|
|
}}
|
884 |
|
|
};break;
|
885 |
|
|
}}
|
886 |
|
|
};break;
|
887 |
|
|
case 0x0:
|
888 |
|
|
{
|
889 |
|
|
{
|
890 |
|
|
switch (((insn>>25)&0x3)) {
|
891 |
|
|
case 0x3:
|
892 |
|
|
{
|
893 |
|
|
{
|
894 |
|
|
switch (((insn>>4)&0x1)) {
|
895 |
|
|
case 0x1:
|
896 |
|
|
{return init_insn_undef2(insn,s);
|
897 |
|
|
};break;
|
898 |
|
|
case 0x0:
|
899 |
|
|
{return init_insn_lsro(insn,s);
|
900 |
|
|
};break;
|
901 |
|
|
}}
|
902 |
|
|
/*default:*/ return init_insn_lsm(insn,s);
|
903 |
|
|
};break;
|
904 |
|
|
case 0x1:
|
905 |
|
|
{return init_insn_lsio(insn,s);
|
906 |
|
|
};break;
|
907 |
|
|
case 0x2:
|
908 |
|
|
{
|
909 |
|
|
{
|
910 |
|
|
switch (((insn>>24)&0x1)) {
|
911 |
|
|
case 0x1:
|
912 |
|
|
{
|
913 |
|
|
{
|
914 |
|
|
switch (((insn>>23)&0x1)) {
|
915 |
|
|
case 0x0:
|
916 |
|
|
{
|
917 |
|
|
{
|
918 |
|
|
switch (((insn>>21)&0x1)) {
|
919 |
|
|
case 0x1:
|
920 |
|
|
{
|
921 |
|
|
{
|
922 |
|
|
switch (((insn>>20)&0x1)) {
|
923 |
|
|
case 0x0:
|
924 |
|
|
{return init_insn_misr(insn,s);
|
925 |
|
|
};break;
|
926 |
|
|
}}
|
927 |
|
|
};break;
|
928 |
|
|
case 0x0:
|
929 |
|
|
{
|
930 |
|
|
{
|
931 |
|
|
switch (((insn>>20)&0x1)) {
|
932 |
|
|
case 0x0:
|
933 |
|
|
{return init_insn_undef1(insn,s);
|
934 |
|
|
};break;
|
935 |
|
|
}}
|
936 |
|
|
};break;
|
937 |
|
|
}}
|
938 |
|
|
};break;
|
939 |
|
|
}}
|
940 |
|
|
};break;
|
941 |
|
|
}}
|
942 |
|
|
/*default:*/ return init_insn_dp_i(insn,s);
|
943 |
|
|
};break;
|
944 |
|
|
case 0x0:
|
945 |
|
|
{
|
946 |
|
|
{
|
947 |
|
|
switch (((insn>>4)&0x1)) {
|
948 |
|
|
case 0x1:
|
949 |
|
|
{
|
950 |
|
|
{
|
951 |
|
|
switch (((insn>>7)&0x1)) {
|
952 |
|
|
case 0x1:
|
953 |
|
|
{
|
954 |
|
|
{
|
955 |
|
|
switch (((insn>>6)&0x1)) {
|
956 |
|
|
case 0x1:
|
957 |
|
|
{
|
958 |
|
|
{
|
959 |
|
|
switch (((insn>>22)&0x1)) {
|
960 |
|
|
case 0x1:
|
961 |
|
|
{
|
962 |
|
|
{
|
963 |
|
|
switch (((insn>>20)&0x1)) {
|
964 |
|
|
case 0x1:
|
965 |
|
|
{return init_insn_ld6(insn,s);
|
966 |
|
|
};break;
|
967 |
|
|
case 0x0:
|
968 |
|
|
{return init_insn_ld5(insn,s);
|
969 |
|
|
};break;
|
970 |
|
|
}}
|
971 |
|
|
};break;
|
972 |
|
|
case 0x0:
|
973 |
|
|
{
|
974 |
|
|
{
|
975 |
|
|
switch (((insn>>20)&0x1)) {
|
976 |
|
|
case 0x1:
|
977 |
|
|
{return init_insn_ld4(insn,s);
|
978 |
|
|
};break;
|
979 |
|
|
case 0x0:
|
980 |
|
|
{return init_insn_ld3(insn,s);
|
981 |
|
|
};break;
|
982 |
|
|
}}
|
983 |
|
|
};break;
|
984 |
|
|
}}
|
985 |
|
|
};break;
|
986 |
|
|
case 0x0:
|
987 |
|
|
{
|
988 |
|
|
{
|
989 |
|
|
switch (((insn>>5)&0x1)) {
|
990 |
|
|
case 0x1:
|
991 |
|
|
{
|
992 |
|
|
{
|
993 |
|
|
switch (((insn>>22)&0x1)) {
|
994 |
|
|
case 0x1:
|
995 |
|
|
{return init_insn_ld2(insn,s);
|
996 |
|
|
};break;
|
997 |
|
|
case 0x0:
|
998 |
|
|
{return init_insn_ld1(insn,s);
|
999 |
|
|
};break;
|
1000 |
|
|
}}
|
1001 |
|
|
};break;
|
1002 |
|
|
case 0x0:
|
1003 |
|
|
{
|
1004 |
|
|
{
|
1005 |
|
|
switch (((insn>>24)&0x1)) {
|
1006 |
|
|
case 0x1:
|
1007 |
|
|
{
|
1008 |
|
|
{
|
1009 |
|
|
switch (((insn>>23)&0x1)) {
|
1010 |
|
|
case 0x0:
|
1011 |
|
|
{
|
1012 |
|
|
{
|
1013 |
|
|
switch (((insn>>21)&0x1)) {
|
1014 |
|
|
case 0x0:
|
1015 |
|
|
{
|
1016 |
|
|
{
|
1017 |
|
|
switch (((insn>>20)&0x1)) {
|
1018 |
|
|
case 0x0:
|
1019 |
|
|
{return init_insn_swp(insn,s);
|
1020 |
|
|
};break;
|
1021 |
|
|
}}
|
1022 |
|
|
};break;
|
1023 |
|
|
}}
|
1024 |
|
|
};break;
|
1025 |
|
|
}}
|
1026 |
|
|
};break;
|
1027 |
|
|
case 0x0:
|
1028 |
|
|
{
|
1029 |
|
|
{
|
1030 |
|
|
switch (((insn>>23)&0x1)) {
|
1031 |
|
|
case 0x1:
|
1032 |
|
|
{return init_insn_mull(insn,s);
|
1033 |
|
|
};break;
|
1034 |
|
|
case 0x0:
|
1035 |
|
|
{
|
1036 |
|
|
{
|
1037 |
|
|
switch (((insn>>22)&0x1)) {
|
1038 |
|
|
case 0x0:
|
1039 |
|
|
{return init_insn_mula(insn,s);
|
1040 |
|
|
};break;
|
1041 |
|
|
}}
|
1042 |
|
|
};break;
|
1043 |
|
|
}}
|
1044 |
|
|
};break;
|
1045 |
|
|
}}
|
1046 |
|
|
};break;
|
1047 |
|
|
}}
|
1048 |
|
|
};break;
|
1049 |
|
|
}}
|
1050 |
|
|
};break;
|
1051 |
|
|
case 0x0:
|
1052 |
|
|
{
|
1053 |
|
|
{
|
1054 |
|
|
switch (((insn>>24)&0x1)) {
|
1055 |
|
|
case 0x1:
|
1056 |
|
|
{
|
1057 |
|
|
{
|
1058 |
|
|
switch (((insn>>23)&0x1)) {
|
1059 |
|
|
case 0x0:
|
1060 |
|
|
{
|
1061 |
|
|
{
|
1062 |
|
|
switch (((insn>>20)&0x1)) {
|
1063 |
|
|
case 0x0:
|
1064 |
|
|
{
|
1065 |
|
|
{
|
1066 |
|
|
switch (((insn>>6)&0x1)) {
|
1067 |
|
|
case 0x1:
|
1068 |
|
|
{
|
1069 |
|
|
{
|
1070 |
|
|
switch (((insn>>5)&0x1)) {
|
1071 |
|
|
case 0x1:
|
1072 |
|
|
{
|
1073 |
|
|
{
|
1074 |
|
|
switch (((insn>>22)&0x1)) {
|
1075 |
|
|
case 0x0:
|
1076 |
|
|
{
|
1077 |
|
|
{
|
1078 |
|
|
switch (((insn>>21)&0x1)) {
|
1079 |
|
|
case 0x1:
|
1080 |
|
|
{return init_insn_brk(insn,s);
|
1081 |
|
|
};break;
|
1082 |
|
|
}}
|
1083 |
|
|
};break;
|
1084 |
|
|
}}
|
1085 |
|
|
};break;
|
1086 |
|
|
case 0x0:
|
1087 |
|
|
{return init_insn_dsa(insn,s);
|
1088 |
|
|
};break;
|
1089 |
|
|
}}
|
1090 |
|
|
};break;
|
1091 |
|
|
case 0x0:
|
1092 |
|
|
{
|
1093 |
|
|
{
|
1094 |
|
|
switch (((insn>>22)&0x1)) {
|
1095 |
|
|
case 0x0:
|
1096 |
|
|
{
|
1097 |
|
|
{
|
1098 |
|
|
switch (((insn>>21)&0x1)) {
|
1099 |
|
|
case 0x1:
|
1100 |
|
|
{
|
1101 |
|
|
{
|
1102 |
|
|
switch (((insn>>5)&0x1)) {
|
1103 |
|
|
case 0x1:
|
1104 |
|
|
{return init_insn_blx(insn,s);
|
1105 |
|
|
};break;
|
1106 |
|
|
case 0x0:
|
1107 |
|
|
{return init_insn_bex(insn,s);
|
1108 |
|
|
};break;
|
1109 |
|
|
}}
|
1110 |
|
|
};break;
|
1111 |
|
|
}}
|
1112 |
|
|
};break;
|
1113 |
|
|
case 0x1:
|
1114 |
|
|
{
|
1115 |
|
|
{
|
1116 |
|
|
switch (((insn>>21)&0x1)) {
|
1117 |
|
|
case 0x1:
|
1118 |
|
|
{
|
1119 |
|
|
{
|
1120 |
|
|
switch (((insn>>5)&0x1)) {
|
1121 |
|
|
case 0x0:
|
1122 |
|
|
{return init_insn_clz(insn,s);
|
1123 |
|
|
};break;
|
1124 |
|
|
}}
|
1125 |
|
|
};break;
|
1126 |
|
|
}}
|
1127 |
|
|
};break;
|
1128 |
|
|
}}
|
1129 |
|
|
};break;
|
1130 |
|
|
}}
|
1131 |
|
|
};break;
|
1132 |
|
|
}}
|
1133 |
|
|
};break;
|
1134 |
|
|
}}
|
1135 |
|
|
};break;
|
1136 |
|
|
}}
|
1137 |
|
|
/*default:*/ return init_insn_dp_r_s(insn,s);
|
1138 |
|
|
};break;
|
1139 |
|
|
}}
|
1140 |
|
|
};break;
|
1141 |
|
|
case 0x0:
|
1142 |
|
|
{
|
1143 |
|
|
{
|
1144 |
|
|
switch (((insn>>24)&0x1)) {
|
1145 |
|
|
case 0x1:
|
1146 |
|
|
{
|
1147 |
|
|
{
|
1148 |
|
|
switch (((insn>>23)&0x1)) {
|
1149 |
|
|
case 0x0:
|
1150 |
|
|
{
|
1151 |
|
|
{
|
1152 |
|
|
switch (((insn>>20)&0x1)) {
|
1153 |
|
|
case 0x0:
|
1154 |
|
|
{
|
1155 |
|
|
{
|
1156 |
|
|
switch (((insn>>7)&0x1)) {
|
1157 |
|
|
case 0x1:
|
1158 |
|
|
{return init_insn_dsm(insn,s);
|
1159 |
|
|
};break;
|
1160 |
|
|
case 0x0:
|
1161 |
|
|
{
|
1162 |
|
|
{
|
1163 |
|
|
switch (((insn>>21)&0x1)) {
|
1164 |
|
|
case 0x1:
|
1165 |
|
|
{
|
1166 |
|
|
{
|
1167 |
|
|
switch (((insn>>6)&0x1)) {
|
1168 |
|
|
case 0x0:
|
1169 |
|
|
{
|
1170 |
|
|
{
|
1171 |
|
|
switch (((insn>>5)&0x1)) {
|
1172 |
|
|
case 0x0:
|
1173 |
|
|
{return init_insn_mrs(insn,s);
|
1174 |
|
|
};break;
|
1175 |
|
|
}}
|
1176 |
|
|
};break;
|
1177 |
|
|
}}
|
1178 |
|
|
};break;
|
1179 |
|
|
case 0x0:
|
1180 |
|
|
{
|
1181 |
|
|
{
|
1182 |
|
|
switch (((insn>>6)&0x1)) {
|
1183 |
|
|
case 0x0:
|
1184 |
|
|
{
|
1185 |
|
|
{
|
1186 |
|
|
switch (((insn>>5)&0x1)) {
|
1187 |
|
|
case 0x0:
|
1188 |
|
|
{return init_insn_msr(insn,s);
|
1189 |
|
|
};break;
|
1190 |
|
|
}}
|
1191 |
|
|
};break;
|
1192 |
|
|
}}
|
1193 |
|
|
};break;
|
1194 |
|
|
}}
|
1195 |
|
|
};break;
|
1196 |
|
|
}}
|
1197 |
|
|
};break;
|
1198 |
|
|
}}
|
1199 |
|
|
};break;
|
1200 |
|
|
}}
|
1201 |
|
|
};break;
|
1202 |
|
|
}}
|
1203 |
|
|
/*default:*/ return init_insn_dp_i_s(insn,s);
|
1204 |
|
|
};break;
|
1205 |
|
|
}}
|
1206 |
|
|
};break;
|
1207 |
|
|
}}
|
1208 |
|
|
/*default:*/
|
1209 |
|
|
{
|
1210 |
|
|
switch (((insn>>28)&0xf)) {
|
1211 |
|
|
case 0xf:
|
1212 |
|
|
{return init_insn_undef3(insn,s);
|
1213 |
|
|
};break;
|
1214 |
|
|
}}
|
1215 |
|
|
};break;
|
1216 |
|
|
}}
|
1217 |
|
|
|
1218 |
|
|
};
|