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[/] [core_arm/] [trunk/] [vhdl/] [arm/] [libs/] [armpctrl.vhd] - Blame information for rev 5

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library ieee;
use ieee.std_logic_1164.all;
use work.corelib.all;
use work.armpmodel.all;
use work.armshiefter.all;
use work.armdecode.all;
use work.gendc_lib.all;
 
-- PREFIX: apc_xxx
package armpctrl is
 
--   pctrl.
-- data1 data2
--  +---+---+-----------------------------------------------+
--  |   |   | ######## Register Read Stage (rrstg) ######## |
--  |   |   | record apc_micro:                             |
--  |   |   | r1       : src register 1                     |
--  |   |   | r1_valid : src register 1 enable              |
--  |   |   | r2       : src register 2                     |
--  |   |   | r2_valid : src register 2 enable              |
--  +---+---+-----------------------------------------------+
--  |   |   |          pstate                               |
--  |   |   | r1+--------V---------+    +---------+         |
--  | +-+---+---+ Forwarding Logic +----+ regfile +<--------+< wrstg
--  | | | +-+---+                  |    +---------+         |
--  | V | V | r2+------------------+                        |
--  |   |   |                                               | 
--  |   |   |  Note: if (rsop_op1_src,rsop_op2_src) == none | 
--  |   |   |        then pctrl.data(1,2) are imidiate and  | 
--  |   |   |        pctrl.data(1,2) are not written        |
--  +---+---+-----------------------------------------------+ 
--    VVVVV    lock on register/coprocessor stall           
--  +---+---+-----------------------------------------------+
--  |   |   | ####### Register Shieft Stage (rsstg) ####### |
--  |   |   | record apc_rsstg:                             |
--  |   |   | rsop_op1_src : pctrl.data1 src                |
--  |   |   | rsop_op2_src : pctrl.data2 src                |
--  |   |   | rsop_buf1_src: rsstg.buf1 src                 |
--  |   |   | rsop_buf2_src: rsstg.buf2 src                 |
--  |   |   | rsop_styp    : shieft type                    |
--  |   |   | rsop_sdir    : shieft dir                     |
--  +---+---+-----------------------------------------------+
--  |   |   |                                               | 
--  |   |   |  rsop_buf2_src:                  +----+      <+-exstg.<aluresult>
--  |   |   |       "trough": pctrl.data1 -+-> |buf1|       |    
--  |   |   |       "alures": <aluresult> -+   +----+       |    
--  |   |   |       "none"  : ~~                            |    
--  |   |   |                                               |
--  |   |   |  rsop_buf2_src:                  +----+       |    
--  |   |   |       "trough": pctrl.data2 -+-> |buf2|       |    
--  |   |   |       "alures": <aluresult> -+   +----+       |    
--  |   |   |       "none"  : ~~                            |    
--  |   |   |                                               |
--  |   |   |  rsop_op1_src :                               |    
--  | +-^---^---+-  "trough": pctrl.data1                   |    
--  | V |   |   +-  "none"  : ~~                            |    
--  |   |   |   +-  "alures": <aluresult>                   |    
--  |   |   |   +-  "buf"   : buf1                          |    
--  |   |   |                        pctrl.data1 pctrl.data2|
--  |   |   |                                V    V         |
--  |   |   |  rsop_op2_src :              +-+----+-+       |    
--  |   | +-^---+-  "trough": <------------|shiefter|       |    
--  |   | V |   +-  "none"  : ~~           +----+---+       |    
--  |   |   |   +-  "alures": <aluresult>       |           |    
--  |   |   |   +-  "buf"   : buf2              V           |    
--  |   |   |                          rs_shieftcarryout    |     
--  +---+---+-----------------------------------------------+
--  +---+---+-----------------------------------------------+
--  |   |   | ########### Execute Stage (exstg) ########### |
--  +---+---+-----------------------------------------------+
--  |   |   | record apc_exstg:                             |
--  |   |   | exop_aluop    : alu operation type            |
--  |   |   | exop_data_src : pctrl.data1 source            | 
--  |   |   | exop_buf_src  : exstg.buf source              |
--  |   |   | exop_setcpsr  : update cpsr                   |
--  +---+---+-----------------------------------------------+
--  |   |   |                                               |
--  | o-+-o=+======+------+                                 |
--  |   |   |   +--+------+--+                              |
--  |   |   |   | exop_aluop |                              |
--  |   |   |   +-----+------+                              |
--  |   |   |         |                                     |
--  |   |   |     <aluresult>                               |
--  |   |   |                                               |
--  |   |   |  exop_buf_src:                  +----+       <+--
--  |   |   |       "aluout": <aluresult> -+->|buf1|        |
--  |   |   |       "op1"   : pctrl.data1 -+  +----+        |
--  |   |   |       "none"  : ~~                            |
--  |   |   |                                               |
--  |   |   |  exop_op1_src :                 exop_setcpsr  |
--  | +-^---^---+-  "aluout": <aluresult>      +-------+    |
--  | V |   |   +-  "buf"   : buf1             |  cpsr |    |
--  |   |   |                                  +---+---+    |
--  |   |   |                                      V        |
--  |   |   |                                   ex_cpsr     |
--  +---+---+-----------------------------------------------+
--  +---+---+-----------------------------------------------+
--  |   |   | ############ DMMU Stage (dmstg) ############# |
--  +---+---+-----------------------------------------------+
--  |   |   |                                               |
--  |   | o-+-+                                             |
--  +---+---+-)---------------------------------------------+
--  +---+---+-)---------------------------------------------+
--  |   |   | |########## Memory Stage (dmstg) ############ |
--  |   |   | |record apc_mestg:                            |
--  |   |   | | meop_param  : dcache params                 |
--  |   |   | | meop_enable : load/store                    |
--  +---+---+-)---------------------------------------------+
--  |   |   | |       Store :                               |
--  |   |   | +> dmstg.pctrl.data2 : store data             +
--  | o-+---+-->pctrl.data1 : memory address                |
--  |   |   |                                              -+-> dcache in
--  |   |   |          Load :                               |
--  | o-+---+-> pctrl.data1 : memory address                |
--  |   |   |                                               |
--  |   |   |                                               |
--  |   |   |                                               |
--  |   |   |                                               |
--  +---+---+-----------------------------------------------+
--  +---+---+-----------------------------------------------+
--  |   |   | ############ Write Stage (dmstg) ############ |
--  |   |   | record apc_mestg:                             |
--  |   |   |  wrop_rd      : write register                |
--  |   |   |  wrop_rdvalid : write enable                  |
--  |   |   |  wrop_trap    : trap ctrl                     | 
--  |   |   |  wrop_setspsr : set spsr                      |
--  +---+---+-----------------------------------------------+
--  |   |   |                                               |
--  |   |   |                                          <-+-<+- dcache out
--  |   |   |                                            |  |
--  |   |   |                                            +->+- rrstg write
--  |   |   |                                               |
--  +---+---+-----------------------------------------------+
 
 
-- RSSTG operation: EXSTG operand source
type apc_rsop_opsrc is (
  apc_opsrc_through,
  apc_opsrc_buf,
  apc_opsrc_alures,
  apc_opsrc_none
);
 
-- RSSTG operation: RSSTG buffer source
type apc_rsop_bufsrc is (
  apc_bufsrc_none,
  apc_bufsrc_through,
  apc_bufsrc_alures
);
 
-- EXSTG operation: pctrl.data source
type apc_exop_datasrc is (
  apc_datasrc_aluout,
  apc_datasrc_buf,
  apc_datasrc_none
);
 
-- EXSTG operation: exstg.buf source
type apc_exop_bufsrc is (
  apc_exbufsrc_none,
  apc_exbufsrc_aluout,
  apc_exbufsrc_op1
);
 
type apc_rrstg is record
  -- operations
  dummy : std_logic;
end record;
 
type apc_rsstg is record
  -- operations
  rsop_op1_src  : apc_rsop_opsrc;  -- EXSTG operand1 source
  rsop_op2_src  : apc_rsop_opsrc;  -- EXSTG operand1 source
  rsop_buf1_src : apc_rsop_bufsrc; -- RSSTG buffer1 source
  rsop_buf2_src : apc_rsop_bufsrc; -- RSSTG buffer2 source
  rsop_styp     : ash_styp;        -- RSSTG shieft op
  rsop_sdir     : ash_sdir;        -- RSSTG shieft dir
  -- data
  rs_shieftcarryout : std_logic;   -- RSSTG shiefter carry out
end record;
 
type apc_exstg is record
  -- operations
  exop_aluop    : std_logic_vector(3 downto 0);  -- EXSTG alu operation
  exop_data_src : apc_exop_datasrc;  -- EXSTG pctrl.data1 source
  exop_buf_src  : apc_exop_bufsrc;   -- ESSTG buffer source
  exop_setcpsr  : std_logic;         -- EXSTG set cpsr
  -- data                                   
  ex_cpsr : apm_cpsr;           -- EXSTG store old cpsr
end record;
 
type apc_dmstg is record
  dummy : std_logic;
end record;
 
type apc_mestg is record
  -- operation
  meop_enable : std_logic;
  meop_param  : gdcl_param;
  -- data
  mexc   : std_logic;
end record;
 
type apc_wrstg is record
  -- operation
  wrop_rd      : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  wrop_rdvalid : std_logic;
  wrop_setspsr : std_logic;
  wrop_trap    : apm_trapctrl;
end record;
 
type apc_pctrl is record
  insn : ade_insn;
  valid : std_logic;
  rr : apc_rrstg;
  rs : apc_rsstg;
  ex : apc_exstg;
  dm : apc_dmstg;
  me : apc_mestg;
  wr : apc_wrstg;
  data1 : std_logic_vector(31 downto 0);
  data2 : std_logic_vector(31 downto 0);
end record;
 
type apc_pstate is record
  hold_r    : cli_hold;
  nextinsn_v : std_logic;
  dabort_v : std_logic;
  -- active cpsr
  fromEX_cpsr_r : apm_cpsr;
  -- pctrls of all stages from rrstg on 
  fromRR_pctrl_r : apc_pctrl;
  fromRS_pctrl_r : apc_pctrl;
  fromEX_pctrl_r : apc_pctrl;
  fromDM_pctrl_r : apc_pctrl;
  fromME_pctrl_r : apc_pctrl;
  fromWR_pctrl_r : apc_pctrl;
end record;
 
type apc_micro is record
  pctrl : apc_pctrl;
  valid : std_logic;
  r1, r2 : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  r1_valid, r2_valid : std_logic;
end record;
 
-------------------------------------------------------------------------------
-- pctrl predicate: ctrl
 
-- check weather pctrl is valid
function apc_is_valid (
  pctrl : apc_pctrl
) return boolean;
 
-- check weather branch (reg/mem)
function apc_is_branch(
  pctrl   : apc_pctrl
) return boolean;
 
-------------------------------------------------------------------------------
-- pctrl predicate: mem op 
 
-- check weather mestg active
function apc_is_mem(
  pctrl   : apc_pctrl
) return boolean;
 
-- check weather mestg load
function apc_is_memload(
  pctrl   : apc_pctrl
) return boolean;
 
-- check weather str addr (next pctrl will be store data) 
function apc_is_straddr(
  pctrl   : apc_pctrl
) return boolean;
 
-- check weather str data (prev pctrl was be store addr) 
function apc_is_strdata(
  pctrl   : apc_pctrl
) return boolean;
 
-------------------------------------------------------------------------------
-- pctrl predicate: register locking 
 
-- check weather it is a mem ldr
function apc_is_rdlocked(
  pctrl   : apc_pctrl
) return boolean;
 
-- check weather app_is_rdlocked() + rd compare
function apc_is_rdlocked_by (
  rd    : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  pctrl : apc_pctrl
) return boolean;
 
-- check weather wrstg rd data come from alu
function apc_is_rdfromalu(
  pctrl   : apc_pctrl
) return boolean;
 
-------------------------------------------------------------------------------
-- pctrl predicate: cpsr locking 
 
-- check weather rsstg is used
function apc_is_rswillshieft(
  pctrl   : apc_pctrl
) return boolean;
 
-- check weather cpsr will be modified 
function apc_is_exwillsetcpsr(
  pctrl   : apc_pctrl
) return boolean;
 
-- check weather cpsr is used 
function apc_is_usecpsr(
  pctrl   : apc_pctrl
) return boolean;
 
-------------------------------------------------------------------------------
 
-- check weather stg should flush
function apc_is_flush(
  stgid : std_logic_vector(2 downto 0);
  flushid : std_logic_vector(2 downto 0)
) return boolean;
 
end armpctrl;
 
package body armpctrl is
 
function apc_is_valid (
  pctrl : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if pctrl.valid = '1' then
    tmp := true;
  end if;
  return tmp;
end;
 
function apc_is_branch(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if (pctrl.wr.wrop_rdvalid = '1') and
       (pctrl.wr.wrop_rd = APM_RREAL_PC) then
      tmp := true;
    end if;
  end if;
  return tmp;
end;
 
function apc_is_rdlocked(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) and
     (pctrl.me.meop_enable = '1') and
     (pctrl.me.meop_param.read = '1') and
     (pctrl.wr.wrop_rdvalid = '1') then
    tmp := true;
  end if;
  return tmp;
end;
 
function apc_is_rdlocked_by (
  rd    : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);
  pctrl : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if (pctrl.wr.wrop_rd = rd) and apc_is_rdlocked(pctrl) then
    tmp := true;
  end if;
  return tmp;
end;
 
function apc_is_rdfromalu(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if  apc_is_valid(pctrl) and
     (not apc_is_memload(pctrl)) and
     (pctrl.wr.wrop_rdvalid = '1') then
    tmp := true;
  end if;
  return tmp;
end;
 
function apc_is_mem(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if pctrl.me.meop_enable = '1' then
      tmp := true;
    end if;
  end if;
  return tmp;
end;
 
function apc_is_memload(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_mem(pctrl) then
    if pctrl.me.meop_param.read = '1' then
      tmp := true;
    end if;
  end if;
  return tmp;
end;
 
function apc_is_straddr(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if (pctrl.me.meop_enable = '1') and
       (pctrl.me.meop_param.read = '0') and
       (pctrl.me.meop_param.addrin = '1') then
      tmp := true;
    end if;
  end if;
  return tmp;
end;
 
function apc_is_strdata(
  pctrl   : apc_pctrl
) return boolean  is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if (pctrl.me.meop_enable = '1') and
       (pctrl.me.meop_param.read = '0') and
       (pctrl.me.meop_param.writedata = '1') then
      tmp := true;
    end if;
  end if;
  return tmp;
end;
 
function apc_is_rswillshieft(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    -- shiefter output used
    if pctrl.rs.rsop_op2_src = apc_opsrc_through or
       pctrl.rs.rsop_buf2_src = apc_bufsrc_through then
      -- shiefter does something
      if (pctrl.rs.rsop_styp = ash_styp_simm) or
         (pctrl.rs.rsop_styp = ash_styp_sreg) then
        if not (pctrl.rs.rsop_sdir = ash_sdir_snone) then
          tmp := true;
        end if;
      end if;
    end if;
  end if;
  return tmp;
end;
 
function apc_is_exwillsetcpsr(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := apc_is_valid(pctrl) and
        (pctrl.ex.exop_setcpsr = '1') ;
  return tmp;
end;
 
function apc_is_usecpsr(
  pctrl   : apc_pctrl
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if apc_is_valid(pctrl) then
    if apc_is_rswillshieft(pctrl) then
      tmp := true;
    end if;
  end if;
  return tmp;
end;
 
function apc_is_flush(
  stgid : std_logic_vector(2 downto 0);
  flushid : std_logic_vector(2 downto 0)
) return boolean is
  variable tmp : boolean;
begin
  tmp := false;
  if not (stgid = flushid) then
    tmp := true;
  end if;
  return tmp;
end;
 
end armpctrl;

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Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [vhdl/] [arm/] [libs/] [armpctrl.vhd] - Blame information for rev 5

Line No.	Rev	Author	Line
1	2	tarookumic	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use work.corelib.all;`
4			`use work.armpmodel.all;`
5			`use work.armshiefter.all;`
6			`use work.armdecode.all;`
7			`use work.gendc_lib.all;`
8
9			`-- PREFIX: apc_xxx`
10			`package armpctrl is`
11
12			`-- pctrl.`
13			`-- data1 data2`
14			`-- +---+---+-----------------------------------------------+`
15			`-- \| \| \| ######## Register Read Stage (rrstg) ######## \|`
16			`-- \| \| \| record apc_micro: \|`
17			`-- \| \| \| r1 : src register 1 \|`
18			`-- \| \| \| r1_valid : src register 1 enable \|`
19			`-- \| \| \| r2 : src register 2 \|`
20			`-- \| \| \| r2_valid : src register 2 enable \|`
21			`-- +---+---+-----------------------------------------------+`
22			`-- \| \| \| pstate \|`
23			`-- \| \| \| r1+--------V---------+ +---------+ \|`
24			`-- \| +-+---+---+ Forwarding Logic +----+ regfile +<--------+< wrstg`
25			`-- \| \| \| +-+---+ \| +---------+ \|`
26			`-- \| V \| V \| r2+------------------+ \|`
27			`-- \| \| \| \|`
28			`-- \| \| \| Note: if (rsop_op1_src,rsop_op2_src) == none \|`
29			`-- \| \| \| then pctrl.data(1,2) are imidiate and \|`
30			`-- \| \| \| pctrl.data(1,2) are not written \|`
31			`-- +---+---+-----------------------------------------------+`
32			`-- VVVVV lock on register/coprocessor stall`
33			`-- +---+---+-----------------------------------------------+`
34			`-- \| \| \| ####### Register Shieft Stage (rsstg) ####### \|`
35			`-- \| \| \| record apc_rsstg: \|`
36			`-- \| \| \| rsop_op1_src : pctrl.data1 src \|`
37			`-- \| \| \| rsop_op2_src : pctrl.data2 src \|`
38			`-- \| \| \| rsop_buf1_src: rsstg.buf1 src \|`
39			`-- \| \| \| rsop_buf2_src: rsstg.buf2 src \|`
40			`-- \| \| \| rsop_styp : shieft type \|`
41			`-- \| \| \| rsop_sdir : shieft dir \|`
42			`-- +---+---+-----------------------------------------------+`
43			`-- \| \| \| \|`
44			`-- \| \| \| rsop_buf2_src: +----+ <+-exstg.<aluresult>`
45			`-- \| \| \| "trough": pctrl.data1 -+-> \|buf1\| \|`
46			`-- \| \| \| "alures": <aluresult> -+ +----+ \|`
47			`-- \| \| \| "none" : ~~ \|`
48			`-- \| \| \| \|`
49			`-- \| \| \| rsop_buf2_src: +----+ \|`
50			`-- \| \| \| "trough": pctrl.data2 -+-> \|buf2\| \|`
51			`-- \| \| \| "alures": <aluresult> -+ +----+ \|`
52			`-- \| \| \| "none" : ~~ \|`
53			`-- \| \| \| \|`
54			`-- \| \| \| rsop_op1_src : \|`
55			`-- \| +-^---^---+- "trough": pctrl.data1 \|`
56			`-- \| V \| \| +- "none" : ~~ \|`
57			`-- \| \| \| +- "alures": <aluresult> \|`
58			`-- \| \| \| +- "buf" : buf1 \|`
59			`-- \| \| \| pctrl.data1 pctrl.data2\|`
60			`-- \| \| \| V V \|`
61			`-- \| \| \| rsop_op2_src : +-+----+-+ \|`
62			`-- \| \| +-^---+- "trough": <------------\|shiefter\| \|`
63			`-- \| \| V \| +- "none" : ~~ +----+---+ \|`
64			`-- \| \| \| +- "alures": <aluresult> \| \|`
65			`-- \| \| \| +- "buf" : buf2 V \|`
66			`-- \| \| \| rs_shieftcarryout \|`
67			`-- +---+---+-----------------------------------------------+`
68			`-- +---+---+-----------------------------------------------+`
69			`-- \| \| \| ########### Execute Stage (exstg) ########### \|`
70			`-- +---+---+-----------------------------------------------+`
71			`-- \| \| \| record apc_exstg: \|`
72			`-- \| \| \| exop_aluop : alu operation type \|`
73			`-- \| \| \| exop_data_src : pctrl.data1 source \|`
74			`-- \| \| \| exop_buf_src : exstg.buf source \|`
75			`-- \| \| \| exop_setcpsr : update cpsr \|`
76			`-- +---+---+-----------------------------------------------+`
77			`-- \| \| \| \|`
78			`-- \| o-+-o=+======+------+ \|`
79			`-- \| \| \| +--+------+--+ \|`
80			`-- \| \| \| \| exop_aluop \| \|`
81			`-- \| \| \| +-----+------+ \|`
82			`-- \| \| \| \| \|`
83			`-- \| \| \| <aluresult> \|`
84			`-- \| \| \| \|`
85			`-- \| \| \| exop_buf_src: +----+ <+--`
86			`-- \| \| \| "aluout": <aluresult> -+->\|buf1\| \|`
87			`-- \| \| \| "op1" : pctrl.data1 -+ +----+ \|`
88			`-- \| \| \| "none" : ~~ \|`
89			`-- \| \| \| \|`
90			`-- \| \| \| exop_op1_src : exop_setcpsr \|`
91			`-- \| +-^---^---+- "aluout": <aluresult> +-------+ \|`
92			`-- \| V \| \| +- "buf" : buf1 \| cpsr \| \|`
93			`-- \| \| \| +---+---+ \|`
94			`-- \| \| \| V \|`
95			`-- \| \| \| ex_cpsr \|`
96			`-- +---+---+-----------------------------------------------+`
97			`-- +---+---+-----------------------------------------------+`
98			`-- \| \| \| ############ DMMU Stage (dmstg) ############# \|`
99			`-- +---+---+-----------------------------------------------+`
100			`-- \| \| \| \|`
101			`-- \| \| o-+-+ \|`
102			`-- +---+---+-)---------------------------------------------+`
103			`-- +---+---+-)---------------------------------------------+`
104			`-- \| \| \| \|########## Memory Stage (dmstg) ############ \|`
105			`-- \| \| \| \|record apc_mestg: \|`
106			`-- \| \| \| \| meop_param : dcache params \|`
107			`-- \| \| \| \| meop_enable : load/store \|`
108			`-- +---+---+-)---------------------------------------------+`
109			`-- \| \| \| \| Store : \|`
110			`-- \| \| \| +> dmstg.pctrl.data2 : store data +`
111			`-- \| o-+---+-->pctrl.data1 : memory address \|`
112			`-- \| \| \| -+-> dcache in`
113			`-- \| \| \| Load : \|`
114			`-- \| o-+---+-> pctrl.data1 : memory address \|`
115			`-- \| \| \| \|`
116			`-- \| \| \| \|`
117			`-- \| \| \| \|`
118			`-- \| \| \| \|`
119			`-- +---+---+-----------------------------------------------+`
120			`-- +---+---+-----------------------------------------------+`
121			`-- \| \| \| ############ Write Stage (dmstg) ############ \|`
122			`-- \| \| \| record apc_mestg: \|`
123			`-- \| \| \| wrop_rd : write register \|`
124			`-- \| \| \| wrop_rdvalid : write enable \|`
125			`-- \| \| \| wrop_trap : trap ctrl \|`
126			`-- \| \| \| wrop_setspsr : set spsr \|`
127			`-- +---+---+-----------------------------------------------+`
128			`-- \| \| \| \|`
129			`-- \| \| \| <-+-<+- dcache out`
130			`-- \| \| \| \| \|`
131			`-- \| \| \| +->+- rrstg write`
132			`-- \| \| \| \|`
133			`-- +---+---+-----------------------------------------------+`
134
135
136			`-- RSSTG operation: EXSTG operand source`
137			`type apc_rsop_opsrc is (`
138			`apc_opsrc_through,`
139			`apc_opsrc_buf,`
140			`apc_opsrc_alures,`
141			`apc_opsrc_none`
142			`);`
143
144			`-- RSSTG operation: RSSTG buffer source`
145			`type apc_rsop_bufsrc is (`
146			`apc_bufsrc_none,`
147			`apc_bufsrc_through,`
148			`apc_bufsrc_alures`
149			`);`
150
151			`-- EXSTG operation: pctrl.data source`
152			`type apc_exop_datasrc is (`
153			`apc_datasrc_aluout,`
154			`apc_datasrc_buf,`
155			`apc_datasrc_none`
156			`);`
157
158			`-- EXSTG operation: exstg.buf source`
159			`type apc_exop_bufsrc is (`
160			`apc_exbufsrc_none,`
161			`apc_exbufsrc_aluout,`
162			`apc_exbufsrc_op1`
163			`);`
164
165			`type apc_rrstg is record`
166			`-- operations`
167			`dummy : std_logic;`
168			`end record;`
169
170			`type apc_rsstg is record`
171			`-- operations`
172			`rsop_op1_src : apc_rsop_opsrc; -- EXSTG operand1 source`
173			`rsop_op2_src : apc_rsop_opsrc; -- EXSTG operand1 source`
174			`rsop_buf1_src : apc_rsop_bufsrc; -- RSSTG buffer1 source`
175			`rsop_buf2_src : apc_rsop_bufsrc; -- RSSTG buffer2 source`
176			`rsop_styp : ash_styp; -- RSSTG shieft op`
177			`rsop_sdir : ash_sdir; -- RSSTG shieft dir`
178			`-- data`
179			`rs_shieftcarryout : std_logic; -- RSSTG shiefter carry out`
180			`end record;`
181
182			`type apc_exstg is record`
183			`-- operations`
184			`exop_aluop : std_logic_vector(3 downto 0); -- EXSTG alu operation`
185			`exop_data_src : apc_exop_datasrc; -- EXSTG pctrl.data1 source`
186			`exop_buf_src : apc_exop_bufsrc; -- ESSTG buffer source`
187			`exop_setcpsr : std_logic; -- EXSTG set cpsr`
188			`-- data`
189			`ex_cpsr : apm_cpsr; -- EXSTG store old cpsr`
190			`end record;`
191
192			`type apc_dmstg is record`
193			`dummy : std_logic;`
194			`end record;`
195
196			`type apc_mestg is record`
197			`-- operation`
198			`meop_enable : std_logic;`
199			`meop_param : gdcl_param;`
200			`-- data`
201			`mexc : std_logic;`
202			`end record;`
203
204			`type apc_wrstg is record`
205			`-- operation`
206			`wrop_rd : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);`
207			`wrop_rdvalid : std_logic;`
208			`wrop_setspsr : std_logic;`
209			`wrop_trap : apm_trapctrl;`
210			`end record;`
211
212			`type apc_pctrl is record`
213			`insn : ade_insn;`
214			`valid : std_logic;`
215			`rr : apc_rrstg;`
216			`rs : apc_rsstg;`
217			`ex : apc_exstg;`
218			`dm : apc_dmstg;`
219			`me : apc_mestg;`
220			`wr : apc_wrstg;`
221			`data1 : std_logic_vector(31 downto 0);`
222			`data2 : std_logic_vector(31 downto 0);`
223			`end record;`
224
225			`type apc_pstate is record`
226			`hold_r : cli_hold;`
227			`nextinsn_v : std_logic;`
228			`dabort_v : std_logic;`
229			`-- active cpsr`
230			`fromEX_cpsr_r : apm_cpsr;`
231			`-- pctrls of all stages from rrstg on`
232			`fromRR_pctrl_r : apc_pctrl;`
233			`fromRS_pctrl_r : apc_pctrl;`
234			`fromEX_pctrl_r : apc_pctrl;`
235			`fromDM_pctrl_r : apc_pctrl;`
236			`fromME_pctrl_r : apc_pctrl;`
237			`fromWR_pctrl_r : apc_pctrl;`
238			`end record;`
239
240			`type apc_micro is record`
241			`pctrl : apc_pctrl;`
242			`valid : std_logic;`
243			`r1, r2 : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);`
244			`r1_valid, r2_valid : std_logic;`
245			`end record;`
246
247			`-------------------------------------------------------------------------------`
248			`-- pctrl predicate: ctrl`
249
250			`-- check weather pctrl is valid`
251			`function apc_is_valid (`
252			`pctrl : apc_pctrl`
253			`) return boolean;`
254
255			`-- check weather branch (reg/mem)`
256			`function apc_is_branch(`
257			`pctrl : apc_pctrl`
258			`) return boolean;`
259
260			`-------------------------------------------------------------------------------`
261			`-- pctrl predicate: mem op`
262
263			`-- check weather mestg active`
264			`function apc_is_mem(`
265			`pctrl : apc_pctrl`
266			`) return boolean;`
267
268			`-- check weather mestg load`
269			`function apc_is_memload(`
270			`pctrl : apc_pctrl`
271			`) return boolean;`
272
273			`-- check weather str addr (next pctrl will be store data)`
274			`function apc_is_straddr(`
275			`pctrl : apc_pctrl`
276			`) return boolean;`
277
278			`-- check weather str data (prev pctrl was be store addr)`
279			`function apc_is_strdata(`
280			`pctrl : apc_pctrl`
281			`) return boolean;`
282
283			`-------------------------------------------------------------------------------`
284			`-- pctrl predicate: register locking`
285
286			`-- check weather it is a mem ldr`
287			`function apc_is_rdlocked(`
288			`pctrl : apc_pctrl`
289			`) return boolean;`
290
291			`-- check weather app_is_rdlocked() + rd compare`
292			`function apc_is_rdlocked_by (`
293			`rd : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);`
294			`pctrl : apc_pctrl`
295			`) return boolean;`
296
297			`-- check weather wrstg rd data come from alu`
298			`function apc_is_rdfromalu(`
299			`pctrl : apc_pctrl`
300			`) return boolean;`
301
302			`-------------------------------------------------------------------------------`
303			`-- pctrl predicate: cpsr locking`
304
305			`-- check weather rsstg is used`
306			`function apc_is_rswillshieft(`
307			`pctrl : apc_pctrl`
308			`) return boolean;`
309
310			`-- check weather cpsr will be modified`
311			`function apc_is_exwillsetcpsr(`
312			`pctrl : apc_pctrl`
313			`) return boolean;`
314
315			`-- check weather cpsr is used`
316			`function apc_is_usecpsr(`
317			`pctrl : apc_pctrl`
318			`) return boolean;`
319
320			`-------------------------------------------------------------------------------`
321
322			`-- check weather stg should flush`
323			`function apc_is_flush(`
324			`stgid : std_logic_vector(2 downto 0);`
325			`flushid : std_logic_vector(2 downto 0)`
326			`) return boolean;`
327
328			`end armpctrl;`
329
330			`package body armpctrl is`
331
332			`function apc_is_valid (`
333			`pctrl : apc_pctrl`
334			`) return boolean is`
335			`variable tmp : boolean;`
336			`begin`
337			`tmp := false;`
338			`if pctrl.valid = '1' then`
339			`tmp := true;`
340			`end if;`
341			`return tmp;`
342			`end;`
343
344			`function apc_is_branch(`
345			`pctrl : apc_pctrl`
346			`) return boolean is`
347			`variable tmp : boolean;`
348			`begin`
349			`tmp := false;`
350			`if apc_is_valid(pctrl) then`
351			`if (pctrl.wr.wrop_rdvalid = '1') and`
352			`(pctrl.wr.wrop_rd = APM_RREAL_PC) then`
353			`tmp := true;`
354			`end if;`
355			`end if;`
356			`return tmp;`
357			`end;`
358
359			`function apc_is_rdlocked(`
360			`pctrl : apc_pctrl`
361			`) return boolean is`
362			`variable tmp : boolean;`
363			`begin`
364			`tmp := false;`
365			`if apc_is_valid(pctrl) and`
366			`(pctrl.me.meop_enable = '1') and`
367			`(pctrl.me.meop_param.read = '1') and`
368			`(pctrl.wr.wrop_rdvalid = '1') then`
369			`tmp := true;`
370			`end if;`
371			`return tmp;`
372			`end;`
373
374			`function apc_is_rdlocked_by (`
375			`rd : std_logic_vector(APM_RREAL_U downto APM_RREAL_D);`
376			`pctrl : apc_pctrl`
377			`) return boolean is`
378			`variable tmp : boolean;`
379			`begin`
380			`tmp := false;`
381			`if (pctrl.wr.wrop_rd = rd) and apc_is_rdlocked(pctrl) then`
382			`tmp := true;`
383			`end if;`
384			`return tmp;`
385			`end;`
386
387			`function apc_is_rdfromalu(`
388			`pctrl : apc_pctrl`
389			`) return boolean is`
390			`variable tmp : boolean;`
391			`begin`
392			`tmp := false;`
393			`if apc_is_valid(pctrl) and`
394			`(not apc_is_memload(pctrl)) and`
395			`(pctrl.wr.wrop_rdvalid = '1') then`
396			`tmp := true;`
397			`end if;`
398			`return tmp;`
399			`end;`
400
401			`function apc_is_mem(`
402			`pctrl : apc_pctrl`
403			`) return boolean is`
404			`variable tmp : boolean;`
405			`begin`
406			`tmp := false;`
407			`if apc_is_valid(pctrl) then`
408			`if pctrl.me.meop_enable = '1' then`
409			`tmp := true;`
410			`end if;`
411			`end if;`
412			`return tmp;`
413			`end;`
414
415			`function apc_is_memload(`
416			`pctrl : apc_pctrl`
417			`) return boolean is`
418			`variable tmp : boolean;`
419			`begin`
420			`tmp := false;`
421			`if apc_is_mem(pctrl) then`
422			`if pctrl.me.meop_param.read = '1' then`
423			`tmp := true;`
424			`end if;`
425			`end if;`
426			`return tmp;`
427			`end;`
428
429			`function apc_is_straddr(`
430			`pctrl : apc_pctrl`
431			`) return boolean is`
432			`variable tmp : boolean;`
433			`begin`
434			`tmp := false;`
435			`if apc_is_valid(pctrl) then`
436			`if (pctrl.me.meop_enable = '1') and`
437			`(pctrl.me.meop_param.read = '0') and`
438			`(pctrl.me.meop_param.addrin = '1') then`
439			`tmp := true;`
440			`end if;`
441			`end if;`
442			`return tmp;`
443			`end;`
444
445			`function apc_is_strdata(`
446			`pctrl : apc_pctrl`
447			`) return boolean is`
448			`variable tmp : boolean;`
449			`begin`
450			`tmp := false;`
451			`if apc_is_valid(pctrl) then`
452			`if (pctrl.me.meop_enable = '1') and`
453			`(pctrl.me.meop_param.read = '0') and`
454			`(pctrl.me.meop_param.writedata = '1') then`
455			`tmp := true;`
456			`end if;`
457			`end if;`
458			`return tmp;`
459			`end;`
460
461			`function apc_is_rswillshieft(`
462			`pctrl : apc_pctrl`
463			`) return boolean is`
464			`variable tmp : boolean;`
465			`begin`
466			`tmp := false;`
467			`if apc_is_valid(pctrl) then`
468			`-- shiefter output used`
469			`if pctrl.rs.rsop_op2_src = apc_opsrc_through or`
470			`pctrl.rs.rsop_buf2_src = apc_bufsrc_through then`
471			`-- shiefter does something`
472			`if (pctrl.rs.rsop_styp = ash_styp_simm) or`
473			`(pctrl.rs.rsop_styp = ash_styp_sreg) then`
474			`if not (pctrl.rs.rsop_sdir = ash_sdir_snone) then`
475			`tmp := true;`
476			`end if;`
477			`end if;`
478			`end if;`
479			`end if;`
480			`return tmp;`
481			`end;`
482
483			`function apc_is_exwillsetcpsr(`
484			`pctrl : apc_pctrl`
485			`) return boolean is`
486			`variable tmp : boolean;`
487			`begin`
488			`tmp := apc_is_valid(pctrl) and`
489			`(pctrl.ex.exop_setcpsr = '1') ;`
490			`return tmp;`
491			`end;`
492
493			`function apc_is_usecpsr(`
494			`pctrl : apc_pctrl`
495			`) return boolean is`
496			`variable tmp : boolean;`
497			`begin`
498			`tmp := false;`
499			`if apc_is_valid(pctrl) then`
500			`if apc_is_rswillshieft(pctrl) then`
501			`tmp := true;`
502			`end if;`
503			`end if;`
504			`return tmp;`
505			`end;`
506
507			`function apc_is_flush(`
508			`stgid : std_logic_vector(2 downto 0);`
509			`flushid : std_logic_vector(2 downto 0)`
510			`) return boolean is`
511			`variable tmp : boolean;`
512			`begin`
513			`tmp := false;`
514			`if not (stgid = flushid) then`
515			`tmp := true;`
516			`end if;`
517			`return tmp;`
518			`end;`
519
520			`end armpctrl;`