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[/] [core_arm/] [trunk/] [vhdl/] [mem/] [cache/] [libs/] [genwb_lib.vhd] - Blame information for rev 4

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Line No. Rev Author Line
1 2 tarookumic
-- $(lic)
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-- $(help_generic)
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-- $(help_local)
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library ieee;
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use ieee.std_logic_1164.all;
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use work.config.all;
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use work.memdef.all;
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use work.cache_config.all;
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-- PREFIX: gwbl_xxx
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package genwb_lib is
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--        dcache                wb 
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-- +-------+ +-------+  +-------+ +-------+
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-- |       | |       |->|       | |       |
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-- +-------+ +-------+  +-------+ +-------+
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-- .       . .       .  .       . .       .              
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--                      .         .       .              
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--                      +-------+ +-------+          
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--                      |       | |       |          
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--                      +-------+ +-------+
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--                          V         V
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--                      +-------+ +-------+          
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--                      |       | |       |          
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--                      +-------+ +-------+           
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--                                
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-- .         .       .            
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-- +-------+ +-------+             
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-- |       | |       |            
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-- +-------+ +-------+             
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--                      +---------------------+-----------+-----------+----+
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-- addr as tag-access : |        TTAG         |   TADDR   | TLINE     | 00 |   
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--                      +---------------------+-----------+-----------+----+
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type gwbl_entry is record
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  addr : std_logic_vector(31 downto 0);
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  data : std_logic_vector(31 downto 0);
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  burst : std_logic;
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  size : lmd_memsize;
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  read : std_logic;
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  lock : std_logic;                     -- lock until next req
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end record;
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type gwbl_entry_a is array (natural range <>) of gwbl_entry;
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end genwb_lib;
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