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[/] [core_arm/] [trunk/] [vhdl/] [peripherals/] [mem/] [c_model/] [mctrl.c] - Blame information for rev 2

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#include <tmki.h>
#include "mctrl.h"
 
/* mctrl.vhd c model:
 * Currently supports:
 * - mcfg2[12:9] sram banksz
 * - mcfg2[25:23] sdram banksz
 * - mcfg2[13] sram disable
 * - mcfg2[14] sdram enable
 */
 
static int fsramsize(mctrl_struct *c) {
  unsigned int i = c ->mcfg2;
  unsigned int sz = 0x2000;
  i = (i >> 9) & 0xf;
  sz = sz << i;
  return sz;
}
 
static int fsdramsize(mctrl_struct *c) {
  unsigned int i = c ->mcfg2;
  unsigned int sz = 0x400000;
  i = (i >> 23) & 0x7;
  sz = sz << i;
  if (c ->mcfg2 & (1 << 14))
    sz = 0;;
  return sz;
}
 
mctrl_struct *mctrl_create() {
 
  mctrl_struct *m;
 
  m = (mctrl_struct *) ti_alloc(sizeof(mctrl_struct));
  if (!m) { return 0; }
 
  m ->sram_sz = fsramsize(m);
  m ->sram_m = ti_alloc(m ->sram_sz);
  m ->rom_sz = 0x100000;
  m ->rom_m = ti_alloc(m ->rom_sz);
 
    ti_print_err("\
Create mctrl model (0x%x):\n\
init sramsize : %x\n\
init sdramsize: %x\n\
init romsize  : %x\n\n",
m,m ->sram_sz,m ->sdram_sz,m ->rom_sz);
 
  return m;
}
 
static unsigned int *decode(mctrl_struct *c,unsigned int addr) {
 
  int sramsize = fsramsize(c);
  int sdramsize = fsdramsize(c);
  addr &= ~0x3;
 
  if (addr >= 0x00000000 && addr < 0x40000000 ) {
    if (addr >= c->rom_sz) {
      return 0;
    }
    return (unsigned int *)&(c->sdram_m[addr]);
  }
  else if (addr >= 0x40000000 && addr < 0x60000000 ) {
    addr = addr - 0x40000000;
    if (c ->mcfg2 & (1 << 13)) {
      if (addr >= sdramsize) {
        return 0;
      }
      return (unsigned int *)&(c->sdram_m[addr]);
    } else {
      if (addr >= sramsize) {
        return 0;
      }
      return (unsigned int *)&(c->sram_m[addr]);
    }
  }
  else if (addr >= 0x60000000 && addr < 0x80000000 ) {
    addr = addr - 0x60000000;
    if (c ->mcfg2 & (1 << 13)) {
      return 0;
    }
    if (addr >= sdramsize) {
      return 0;
    }
    return (unsigned int *)&(c->sdram_m[addr]);
  }
  return 0;
}
 
int mctrl_pwrite(mctrl_struct *c,unsigned int addr,unsigned int data) {
 
  int sramsize,sdramsize;
 
  switch (addr) {
  case 0:
    c ->mcfg1 = data; break;
  case 4:
    c ->mcfg2 = data;
    sramsize = fsramsize(c);
    if (sramsize > c ->sram_sz) {
      c->sram_m = ti_realloc(c->sram_m,c ->sram_sz,sramsize);
    }
    c ->sram_sz = sramsize;
    if (c ->mcfg2 & (1 << 14)) {
      sdramsize = fsdramsize(c);
      if (sdramsize > c ->sdram_sz) {
        c->sdram_m = ti_realloc(c->sdram_m,c ->sdram_sz,sdramsize);
      }
      c ->sdram_sz = sdramsize;
    }
    break;
  case 8:
    c ->mcfg3 = data; break;
  }
}
 
int mctrl_pread(mctrl_struct *c,unsigned int addr,unsigned int *data) {
 
  switch (addr) {
  case 0:
    *data = c ->mcfg1;
    return 1;
  case 4:
    *data = c ->mcfg2;
    return 1;
  case 8:
    *data = c ->mcfg3;
    return 1;
  }
  return 0;
}
 
int mctrl_read(mctrl_struct *c,unsigned int addr,unsigned int *data) {
 
  unsigned int *a = decode(c, addr);
  *data = *(a);
  return 1;
}
 
int mctrl_write(mctrl_struct *c,unsigned int addr,unsigned int data) {
 
  unsigned int *a = decode(c, addr);
  *(a) = data;
  return 1;
}
 
 
 

Line No.	Rev	Author	Line
1	2	tarookumic	`#include <tmki.h>`
2			`#include "mctrl.h"`
3
4			`/* mctrl.vhd c model:`
5			`* Currently supports:`
6			`* - mcfg2[12:9] sram banksz`
7			`* - mcfg2[25:23] sdram banksz`
8			`* - mcfg2[13] sram disable`
9			`* - mcfg2[14] sdram enable`
10			`*/`
11
12			`static int fsramsize(mctrl_struct *c) {`
13			`unsigned int i = c ->mcfg2;`
14			`unsigned int sz = 0x2000;`
15			`i = (i >> 9) & 0xf;`
16			`sz = sz << i;`
17			`return sz;`
18			`}`
19
20			`static int fsdramsize(mctrl_struct *c) {`
21			`unsigned int i = c ->mcfg2;`
22			`unsigned int sz = 0x400000;`
23			`i = (i >> 23) & 0x7;`
24			`sz = sz << i;`
25			`if (c ->mcfg2 & (1 << 14))`
26			`sz = 0;;`
27			`return sz;`
28			`}`
29
30			`mctrl_struct *mctrl_create() {`
31
32			`mctrl_struct *m;`
33
34			`m = (mctrl_struct *) ti_alloc(sizeof(mctrl_struct));`
35			`if (!m) { return 0; }`
36
37			`m ->sram_sz = fsramsize(m);`
38			`m ->sram_m = ti_alloc(m ->sram_sz);`
39			`m ->rom_sz = 0x100000;`
40			`m ->rom_m = ti_alloc(m ->rom_sz);`
41
42			`ti_print_err("\`
43			`Create mctrl model (0x%x):\n\`
44			`init sramsize : %x\n\`
45			`init sdramsize: %x\n\`
46			`init romsize : %x\n\n",`
47			`m,m ->sram_sz,m ->sdram_sz,m ->rom_sz);`
48
49			`return m;`
50			`}`
51
52			`static unsigned int decode(mctrl_struct c,unsigned int addr) {`
53
54			`int sramsize = fsramsize(c);`
55			`int sdramsize = fsdramsize(c);`
56			`addr &= ~0x3;`
57
58			`if (addr >= 0x00000000 && addr < 0x40000000 ) {`
59			`if (addr >= c->rom_sz) {`
60			`return 0;`
61			`}`
62			`return (unsigned int *)&(c->sdram_m[addr]);`
63			`}`
64			`else if (addr >= 0x40000000 && addr < 0x60000000 ) {`
65			`addr = addr - 0x40000000;`
66			`if (c ->mcfg2 & (1 << 13)) {`
67			`if (addr >= sdramsize) {`
68			`return 0;`
69			`}`
70			`return (unsigned int *)&(c->sdram_m[addr]);`
71			`} else {`
72			`if (addr >= sramsize) {`
73			`return 0;`
74			`}`
75			`return (unsigned int *)&(c->sram_m[addr]);`
76			`}`
77			`}`
78			`else if (addr >= 0x60000000 && addr < 0x80000000 ) {`
79			`addr = addr - 0x60000000;`
80			`if (c ->mcfg2 & (1 << 13)) {`
81			`return 0;`
82			`}`
83			`if (addr >= sdramsize) {`
84			`return 0;`
85			`}`
86			`return (unsigned int *)&(c->sdram_m[addr]);`
87			`}`
88			`return 0;`
89			`}`
90
91			`int mctrl_pwrite(mctrl_struct *c,unsigned int addr,unsigned int data) {`
92
93			`int sramsize,sdramsize;`
94
95			`switch (addr) {`
96			`case 0:`
97			`c ->mcfg1 = data; break;`
98			`case 4:`
99			`c ->mcfg2 = data;`
100			`sramsize = fsramsize(c);`
101			`if (sramsize > c ->sram_sz) {`
102			`c->sram_m = ti_realloc(c->sram_m,c ->sram_sz,sramsize);`
103			`}`
104			`c ->sram_sz = sramsize;`
105			`if (c ->mcfg2 & (1 << 14)) {`
106			`sdramsize = fsdramsize(c);`
107			`if (sdramsize > c ->sdram_sz) {`
108			`c->sdram_m = ti_realloc(c->sdram_m,c ->sdram_sz,sdramsize);`
109			`}`
110			`c ->sdram_sz = sdramsize;`
111			`}`
112			`break;`
113			`case 8:`
114			`c ->mcfg3 = data; break;`
115			`}`
116			`}`
117
118			`int mctrl_pread(mctrl_struct c,unsigned int addr,unsigned int data) {`
119
120			`switch (addr) {`
121			`case 0:`
122			`*data = c ->mcfg1;`
123			`return 1;`
124			`case 4:`
125			`*data = c ->mcfg2;`
126			`return 1;`
127			`case 8:`
128			`*data = c ->mcfg3;`
129			`return 1;`
130			`}`
131			`return 0;`
132			`}`
133
134			`int mctrl_read(mctrl_struct c,unsigned int addr,unsigned int data) {`
135
136			`unsigned int *a = decode(c, addr);`
137			`data = (a);`
138			`return 1;`
139			`}`
140
141			`int mctrl_write(mctrl_struct *c,unsigned int addr,unsigned int data) {`
142
143			`unsigned int *a = decode(c, addr);`
144			`*(a) = data;`
145			`return 1;`
146			`}`
147
148
149

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[/] [core_arm/] [trunk/] [vhdl/] [peripherals/] [mem/] [c_model/] [mctrl.c] - Blame information for rev 2