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[/] [core_arm/] [trunk/] [vhdl/] [sparc/] [debug.vhd] - Blame information for rev 4

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1 2 tarookumic 
 
2 
 
3 
 
4 
 
5 
----------------------------------------------------------------------------
6 
--  This file is a part of the LEON VHDL model
7 
--  Copyright (C) 1999  European Space Agency (ESA)
8 
--
9 
--  This library is free software; you can redistribute it and/or
10 
--  modify it under the terms of the GNU Lesser General Public
11 
--  License as published by the Free Software Foundation; either
12 
--  version 2 of the License, or (at your option) any later version.
13 
--
14 
--  See the file COPYING.LGPL for the full details of the license.
15 
 
16 
 
17 
-----------------------------------------------------------------------------
18 
-- Package:     debug
19 
-- File:        debug.vhd
20 
-- Author:      Jiri Gaisler - ESA/ESTEC
21 
-- Description: This package implements a SPARC disassembler and LEON
22 
--              trace function.
23 
------------------------------------------------------------------------------
24 
-- Version control:
25 
-- 17-12-1998:  : First implemetation
26 
-- 27-08-1999:  : Moved trace function from iu
27 
-- 26-09-1999:  : Release 1.0
28 
------------------------------------------------------------------------------
29 
 
30 
library IEEE;
31 
use IEEE.Std_Logic_1164.all;
32 
use IEEE.Std_Logic_unsigned."+";
33 
use IEEE.Std_Logic_arith.all;
34 
use IEEE.std_logic_unsigned.conv_integer;
35 
use work.leon_target.all;
36 
use work.leon_config.all;
37 
use work.sparcv8.all;
38 
use work.leon_iface.all;
39 
use STD.TEXTIO.all;
40 
 
41 
package debug is
42 
 
43 
type debug_info is record
44 
  op    : std_logic_vector(31 downto 0);
45 
  pc    : std_logic_vector(31 downto 0);
46 
end record;
47 
 
48 
type base_type is (hex, dec);
49 
 
50 
subtype nibble is std_logic_vector(3 downto 0);
51 
 
52 
function disas(insn : debug_info) return string;
53 
 
54 
procedure trace(signal debug : in iu_debug_out_type; DISASS : boolean);
55 
 
56 
function tost(v:std_logic_vector) return string;
57 
function tostd(v:std_logic_vector) return string;
58 
function tosth(v:std_logic_vector) return string;
59 
function tostf(v:std_logic_vector) return string;
60 
--function tostring(n:integer) return string;
61 
function tostrd(n:integer) return string;
62 
procedure print(s : string);
63 
 
64 
end debug;
65 
 
66 
package body debug is
67 
 
68 
function tohex(n:nibble) return character is
69 
begin
70 
  case n is
71 
  when "0000" => return('0');
72 
  when "0001" => return('1');
73 
  when "0010" => return('2');
74 
  when "0011" => return('3');
75 
  when "0100" => return('4');
76 
  when "0101" => return('5');
77 
  when "0110" => return('6');
78 
  when "0111" => return('7');
79 
  when "1000" => return('8');
80 
  when "1001" => return('9');
81 
  when "1010" => return('a');
82 
  when "1011" => return('b');
83 
  when "1100" => return('c');
84 
  when "1101" => return('d');
85 
  when "1110" => return('e');
86 
  when "1111" => return('f');
87 
  when others => return('X');
88 
  end case;
89 
end;
90 
 
91 
type carr is array (0 to 9) of character;
92 
constant darr : carr := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9');
93 
function tostd(v:std_logic_vector) return string is
94 
variable s : string(1 to 2);
95 
variable val : integer;
96 
begin
97 
  val := conv_integer(v); s(1) := darr(val / 10); s(2) := darr(val mod 10);
98 
  return(s);
99 
end;
100 
 
101 
function tosth(v:std_logic_vector) return string is
102 
constant vlen : natural := v'length; --'
103 
constant slen : natural := (vlen+3)/4;
104 
variable vv : std_logic_vector(vlen-1 downto 0);
105 
variable s : string(1 to slen);
106 
begin
107 
  vv := v;
108 
  for i in slen downto 1 loop
109 
    s(i) := tohex(vv(3 downto 0));
110 
    vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
111 
  end loop;
112 
  return(s);
113 
end;
114 
 
115 
function tostf(v:std_logic_vector) return string is
116 
constant vlen : natural := v'length; --'
117 
constant slen : natural := (vlen+3)/4;
118 
variable vv : std_logic_vector(vlen-1 downto 0);
119 
variable s : string(1 to slen);
120 
begin
121 
  vv := v;
122 
  for i in slen downto 1 loop
123 
    s(i) := tohex(vv(3 downto 0));
124 
    vv(vlen-5 downto 0) := vv(vlen-1 downto 4);
125 
  end loop;
126 
  return("0x" & s);
127 
end;
128 
 
129 
function tost(v:std_logic_vector) return string is
130 
constant vlen : natural := v'length; --'
131 
constant slen : natural := (vlen+3)/4;
132 
variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
133 
variable s : string(1 to slen);
134 
variable nz : boolean := true;
135 
variable index : integer := -1;
136 
begin
137 
  vv(slen*4-vlen to slen*4-1) := v;
138 
  for i in 0 to slen-1 loop
139 
    if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
140 
      index := i;
141 
    else
142 
      nz := false;
143 
      s(i+1) := tohex(vv(i*4 to i*4+3));
144 
    end if;
145 
  end loop;
146 
  if ((index +2) = slen) then return(s(slen to slen));
147 
  else return(string'("0x") & s(index+2 to slen)); end if; --'
148 
end;
149 
 
150 
--function tostring(n:integer) return string is
151 
--variable len : natural := 1;
152 
--variable tmp : string(1 to 32);
153 
--variable v : integer := n;
154 
--begin
155 
--  for i in 31 downto 0 loop
156 
--    if v>(2**i) then
157 
--      tmp(i) := '1'; v := v - (2**i);
158 
--      if i>len then len := i; end if;
159 
--    else
160 
--      tmp(i) := '0';
161 
--    end if;
162 
--  end loop;
163 
--  return(tmp(32-len to 32));
164 
--end;
165 
 
166 
function tostrd(n:integer) return string is
167 
variable len : integer := 0;
168 
variable tmp : string(10 downto 1);
169 
variable v : integer := n;
170 
begin
171 
  for i in 0 to 9 loop
172 
     tmp(i+1) := darr(v mod 10);
173 
     if tmp(i+1) /= '0'  then
174 
        len := i;
175 
     end if;
176 
     v := v/10;
177 
  end loop;
178 
  return(tmp(len+1 downto 1));
179 
end;
180 
 
181 
function regdec(v : std_logic_vector) return string is
182 
  variable t : std_logic_vector(4 downto 0);
183 
  variable rt : character;
184 
  begin
185 
    t := v;
186 
    case t(4 downto 3) is
187 
    when "00" => rt := 'g';
188 
    when "01" => rt := 'o';
189 
    when "10" => rt := 'l';
190 
    when "11" => rt := 'i';
191 
    when others => rt := 'X';
192 
    end case;
193 
    if v(4 downto 0) = "11110" then
194 
      return("%fp");
195 
    elsif v(4 downto 0) = "01110" then
196 
      return("%sp");
197 
    else
198 
      return('%' & rt & tost('0' & t(2 downto 0)));
199 
    end if;
200 
end;
201 
 
202 
function simm13dec(insn : debug_info; base : base_type; merge : boolean) return string is
203 
  variable simm : std_logic_vector(12 downto 0) := insn.op(12 downto 0);
204 
  variable rs1 : std_logic_vector(4 downto 0)   := insn.op(18 downto 14);
205 
  variable i : std_logic := insn.op(13);
206 
  variable sig : character;
207 
  variable fill : std_logic_vector(31 downto 13) := (others => simm(12));
208 
begin
209 
  if i = '0' then
210 
    return("");
211 
  else
212 
    if (simm(12) = '1') and (base = dec) then
213 
      sig := '-'; simm := (not simm) + 1;
214 
    else
215 
      sig := '+';
216 
    end if;
217 
    if base = dec then
218 
      if merge then
219 
        if rs1 = "00000" then
220 
          return(tost(simm));
221 
        else
222 
          return(sig & tost(simm));
223 
        end if;
224 
      else
225 
        if rs1 = "00000" then
226 
          return(tost(simm));
227 
        else
228 
          if sig = '-' then
229 
            return(", " & sig & tost(simm));
230 
          else
231 
            return(", " & tost(simm));
232 
          end if;
233 
        end if;
234 
      end if;
235 
    else
236 
      if rs1 = "00000" then
237 
        if simm(12) = '1' then return(tost(fill & simm));
238 
        else return(tost(simm)); end if;
239 
      else
240 
        if simm(12) = '1' then return(", " & tost(fill & simm));
241 
        else return(", " & tost(simm)); end if;
242 
      end if;
243 
    end if;
244 
  end if;
245 
end;
246 
 
247 
function freg2(insn : debug_info) return string is
248 
  variable rs1, rs2, rd : std_logic_vector(4 downto 0);
249 
  variable i : std_logic;
250 
begin
251 
  rs2   := insn.op(4 downto 0);
252 
  rd    := insn.op(29 downto 25);
253 
  return("%f" & tostd(rs2) &
254 
         ", %f" & tostd(rd));
255 
end;
256 
 
257 
function creg3(insn : debug_info) return string is
258 
  variable rs1, rs2, rd : std_logic_vector(4 downto 0);
259 
  variable i : std_logic;
260 
begin
261 
  rs1   := insn.op(18 downto 14);
262 
  rs2   := insn.op(4 downto 0);
263 
  rd    := insn.op(29 downto 25);
264 
  return("%c" & tostd(rs1) & ", %c" & tostd(rs2) & ", %c" & tostd(rd));
265 
end;
266 
 
267 
function freg3(insn : debug_info) return string is
268 
  variable rs1, rs2, rd : std_logic_vector(4 downto 0);
269 
  variable i : std_logic;
270 
begin
271 
  rs1   := insn.op(18 downto 14);
272 
  rs2   := insn.op(4 downto 0);
273 
  rd    := insn.op(29 downto 25);
274 
  return("%f" & tostd(rs1) & ", %f" & tostd(rs2) & ", %f" & tostd(rd));
275 
end;
276 
 
277 
function fregc(insn : debug_info) return string is
278 
  variable rs1, rs2 : std_logic_vector(4 downto 0);
279 
  variable i : std_logic;
280 
begin
281 
  rs1   := insn.op(18 downto 14);
282 
  rs2   := insn.op(4 downto 0);
283 
  return("%f" & tostd(rs1) & ", %f" & tostd(rs2));
284 
end;
285 
 
286 
function regimm(insn : debug_info; base : base_type; merge : boolean) return string is
287 
  variable rs1, rs2 : std_logic_vector(4 downto 0);
288 
  variable i : std_logic;
289 
begin
290 
  rs1   := insn.op(18 downto 14);
291 
  rs2   := insn.op(4 downto 0);
292 
  i     := insn.op(13);
293 
  if i = '0' then
294 
    if (rs1 = "00000") then
295 
      if (rs2 = "00000") then
296 
        return("0");
297 
      else
298 
        return(regdec(rs2));
299 
      end if;
300 
    else
301 
      if (rs2 = "00000") then
302 
        return(regdec(rs1));
303 
      elsif merge then
304 
        return(regdec(rs1) & " + " & regdec(rs2));
305 
      else
306 
        return(regdec(rs1) & ", " & regdec(rs2));
307 
      end if;
308 
    end if;
309 
  else
310 
    if (rs1 = "00000") then
311 
      return(simm13dec(insn, base, merge));
312 
    elsif insn.op(12 downto 0) = "0000000000000" then
313 
      return(regdec(rs1));
314 
    else
315 
      return(regdec(rs1) & simm13dec(insn, base, merge));
316 
    end if;
317 
  end if;
318 
end;
319 
 
320 
function regres(insn : debug_info; base : base_type) return string is
321 
  variable rs1, rs2, rd : std_logic_vector(4 downto 0);
322 
  variable i : std_logic;
323 
begin
324 
  rd    := insn.op(29 downto 25);
325 
  return(regimm(insn, base,false) & ", " & regdec(rd ));
326 
end;
327 
 
328 
 
329 
function branchop(insn : debug_info) return string is
330 
  variable simm : std_logic_vector(31 downto 0);
331 
begin
332 
  case insn.op(28 downto 25) is
333 
  when "0000" => return("n");
334 
  when "0001" => return("e");
335 
  when "0010" => return("le");
336 
  when "0011" => return("l");
337 
  when "0100" => return("lue");
338 
  when "0101" => return("cs");
339 
  when "0110" => return("neg");
340 
  when "0111" => return("vs");
341 
  when "1000" => return("a");
342 
  when "1001" => return("ne");
343 
  when "1010" => return("g");
344 
  when "1011" => return("ge");
345 
  when "1100" => return("gu");
346 
  when "1101" => return("cc");
347 
  when "1110" => return("pos");
348 
  when "1111" => return("vc");
349 
  when others => return("XXX");
350 
  end case;
351 
end;
352 
 
353 
function fbranchop(insn : debug_info) return string is
354 
  variable simm : std_logic_vector(31 downto 0);
355 
begin
356 
  case insn.op(28 downto 25) is
357 
  when "0000" => return("n");
358 
  when "0001" => return("ne");
359 
  when "0010" => return("lg");
360 
  when "0011" => return("ul");
361 
  when "0100" => return("l");
362 
  when "0101" => return("ug");
363 
  when "0110" => return("g");
364 
  when "0111" => return("u");
365 
  when "1000" => return("a");
366 
  when "1001" => return("e");
367 
  when "1010" => return("ue");
368 
  when "1011" => return("ge");
369 
  when "1100" => return("uge");
370 
  when "1101" => return("le");
371 
  when "1110" => return("ule");
372 
  when "1111" => return("o");
373 
  when others => return("XXX");
374 
  end case;
375 
end;
376 
 
377 
function ldparcp(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
378 
begin
379 
  return("[" & regimm(insn,dec,true) & "]" & ", " & "%c" & tost(rd));
380 
end;
381 
 
382 
function ldparf(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
383 
begin
384 
  return("[" & regimm(insn,dec,true) & "]" & ", " & "%f" & tostd(rd));
385 
end;
386 
 
387 
function ldpar(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
388 
begin
389 
  return("[" & regimm(insn,dec,true) & "]" & ", " & regdec(rd));
390 
end;
391 
function ldpara(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
392 
begin
393 
  return("[" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)) & ", " & regdec(rd));
394 
end;
395 
function stparc(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
396 
begin
397 
  if rd = "00000" then
398 
    return("[" & regimm(insn,dec,true) & "]");
399 
  else
400 
    return(regdec(rd) & ", [" & regimm(insn,dec,true) & "]");
401 
  end if;
402 
end;
403 
function stparcp(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
404 
begin
405 
  return("%c" & tost(rd) & ", [" & regimm(insn,dec,true) & "]");
406 
end;
407 
function stparf(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
408 
begin
409 
  return("%f" & tostd(rd) & ", [" & regimm(insn,dec,true) & "]");
410 
end;
411 
function stpar(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
412 
begin
413 
  return(regdec(rd) & ", [" & regimm(insn,dec,true) & "]");
414 
end;
415 
function stpara(insn : debug_info; rd : std_logic_vector; base : base_type) return string is
416 
begin
417 
  return(regdec(rd) & ", [" & regimm(insn,dec,true) & "]" & " " & tost(insn.op(12 downto 5)));
418 
end;
419 
 
420 
function disas(insn : debug_info) return string is
421 
  constant STMAX  : natural := 9;
422 
  constant bl2    : string(1 to  2) := (others => ' ');
423 
  constant bb     : string(1 to (4)) := (others => ' ');
424 
  variable op     : std_logic_vector(1 downto 0);
425 
  variable op2    : std_logic_vector(2 downto 0);
426 
  variable op3    : std_logic_vector(5 downto 0);
427 
  variable opf    : std_logic_vector(8 downto 0);
428 
  variable cond   : std_logic_vector(3 downto 0);
429 
  variable rs1, rs2, rd : std_logic_vector(4 downto 0);
430 
  variable addr   : std_logic_vector(31 downto 0);
431 
  variable annul  : std_logic;
432 
  variable i      : std_logic;
433 
  variable simm : std_logic_vector(12 downto 0);
434 
 
435 
  variable disen      : boolean := true;
436 
 
437 
begin
438 
 
439 
  if disen then
440 
 
441 
    op    := insn.op(31 downto 30);
442 
    op2   := insn.op(24 downto 22);
443 
 
444 
    op3   := insn.op(24 downto 19);
445 
    opf   := insn.op(13 downto 5);
446 
    cond  := insn.op(28 downto 25);
447 
    annul := insn.op(29);
448 
    rs1   := insn.op(18 downto 14);
449 
    rs2   := insn.op(4 downto 0);
450 
    rd    := insn.op(29 downto 25);
451 
    i     := insn.op(13);
452 
    simm  := insn.op(12 downto 0);
453 
 
454 
    case op is
455 
    when CALL =>
456 
      addr := insn.pc + (insn.op(29 downto 0) & "00");
457 
      return(tostf(insn.pc) & bb & "call" & bl2 & tost(addr));
458 
    when FMT2 =>
459 
      case op2 is
460 
      when UNIMP => return(tostf(insn.pc) & bb & "unimp");
461 
      when SETHI =>
462 
        if rd = "00000" then
463 
          return(tostf(insn.pc) & bb & "nop");
464 
        else
465 
          return(tostf(insn.pc) & bb & "sethi" & bl2 & "%hi(" &
466 
                tost(insn.op(21 downto 0) & "0000000000") & "), " & regdec(rd));
467 
        end if;
468 
      when BICC | FBFCC =>
469 
        addr(31 downto 24) := (others => '0');
470 
        addr(1 downto 0) := (others => '0');
471 
        addr(23 downto 2) := insn.op(21 downto 0);
472 
        if addr(23) = '1' then
473 
          addr(31 downto 24) := (others => '1');
474 
        else
475 
          addr(31 downto 24) := (others => '0');
476 
        end if;
477 
        addr := addr + insn.pc;
478 
        if op2 = BICC then
479 
          if insn.op(29) = '1' then
480 
            return(tostf(insn.pc) & bb & 'b' & branchop(insn) & ",a" & bl2 &
481 
                tost(addr));
482 
          else
483 
            return(tostf(insn.pc) & bb & 'b' & branchop(insn) & bl2 &
484 
                tost(addr));
485 
          end if;
486 
        else
487 
          if insn.op(29) = '1' then
488 
            return(tostf(insn.pc) & bb & "fb" & fbranchop(insn) & ",a" & bl2 &
489 
                tost(addr));
490 
          else
491 
            return(tostf(insn.pc) & bb & "fb" & fbranchop(insn) & bl2 &
492 
                tost(addr));
493 
          end if;
494 
        end if;
495 
--      when CBCCC => cptrap := '1';
496 
      when others => return(tostf(insn.pc) & bb & "unknown opcode: " & tost(insn.op));
497 
      end case;
498 
    when FMT3 =>
499 
      case op3 is
500 
      when IAND => return(tostf(insn.pc) & bb & "and" & bl2 & regres(insn,hex));
501 
      when IADD => return(tostf(insn.pc) & bb & "add" & bl2 & regres(insn,dec));
502 
      when IOR  =>
503 
        if ((i = '0') and (rs1 = "00000") and (rs2 = "00000")) then
504 
          return(tostf(insn.pc) & bb & "clr" & bl2 & regdec(rd));
505 
        elsif ((i = '1') and (simm = "0000000000000")) or (rs1 = "00000") then
506 
          return(tostf(insn.pc) & bb & "mov" & bl2 & regres(insn,hex));
507 
        else
508 
          return(tostf(insn.pc) & bb & "or " & bl2 & regres(insn,hex));
509 
        end if;
510 
      when IXOR => return(tostf(insn.pc) & bb & "xor" & bl2 & regres(insn,hex));
511 
      when ISUB => return(tostf(insn.pc) & bb & "sub" & bl2 & regres(insn,dec));
512 
      when ANDN => return(tostf(insn.pc) & bb & "andn" & bl2 & regres(insn,hex));
513 
      when ORN  => return(tostf(insn.pc) & bb & "orn" & bl2 & regres(insn,hex));
514 
      when IXNOR =>
515 
        if ((i = '0') and ((rs1 = rd) or (rs2 = "00000"))) then
516 
          return(tostf(insn.pc) & bb & "not" & bl2 & regdec(rd));
517 
        else
518 
          return(tostf(insn.pc) & bb & "xnor" & bl2 & regdec(rd));
519 
        end if;
520 
      when ADDX => return(tostf(insn.pc) & bb & "addx" & bl2 & regres(insn,dec));
521 
      when SUBX => return(tostf(insn.pc) & bb & "subx" & bl2 & regres(insn,dec));
522 
      when ADDCC => return(tostf(insn.pc) & bb & "addcc" & bl2 & regres(insn,dec));
523 
      when ANDCC => return(tostf(insn.pc) & bb & "andcc" & bl2 & regres(insn,hex));
524 
      when ORCC => return(tostf(insn.pc) & bb & "orcc" & bl2 & regres(insn,hex));
525 
      when XORCC => return(tostf(insn.pc) & bb & "xorcc" & bl2 & regres(insn,hex));
526 
      when SUBCC => return(tostf(insn.pc) & bb & "subcc" & bl2 & regres(insn,dec));
527 
      when ANDNCC => return(tostf(insn.pc) & bb & "andncc" & bl2 & regres(insn,hex));
528 
      when ORNCC => return(tostf(insn.pc) & bb & "orncc" & bl2 & regres(insn,hex));
529 
      when XNORCC => return(tostf(insn.pc) & bb & "xnorcc" & bl2 & regres(insn,hex));
530 
      when ADDXCC => return(tostf(insn.pc) & bb & "addxcc" & bl2 & regres(insn,hex));
531 
      when UMAC   => return(tostf(insn.pc) & bb & "umac" & bl2 & regres(insn,dec));
532 
      when SMAC   => return(tostf(insn.pc) & bb & "smac" & bl2 & regres(insn,dec));
533 
      when UMUL   => return(tostf(insn.pc) & bb & "umul" & bl2 & regres(insn,dec));
534 
      when SMUL   => return(tostf(insn.pc) & bb & "smul" & bl2 & regres(insn,dec));
535 
      when UMULCC => return(tostf(insn.pc) & bb & "umulcc" & bl2 & regres(insn,dec));
536 
      when SMULCC => return(tostf(insn.pc) & bb & "smulcc" & bl2 & regres(insn,dec));
537 
      when SUBXCC => return(tostf(insn.pc) & bb & "subxcc" & bl2 & regres(insn,dec));
538 
      when UDIV   => return(tostf(insn.pc) & bb & "udiv" & bl2 & regres(insn,dec));
539 
      when SDIV   => return(tostf(insn.pc) & bb & "sdiv" & bl2 & regres(insn,dec));
540 
      when UDIVCC => return(tostf(insn.pc) & bb & "udivcc" & bl2 & regres(insn,dec));
541 
      when SDIVCC => return(tostf(insn.pc) & bb & "sdivcc" & bl2 & regres(insn,dec));
542 
      when TADDCC => return(tostf(insn.pc) & bb & "taddcc" & bl2 & regres(insn,dec));
543 
      when TSUBCC => return(tostf(insn.pc) & bb & "tsubcc" & bl2 & regres(insn,dec));
544 
      when TADDCCTV => return(tostf(insn.pc) & bb & "taddcctv" & bl2 & regres(insn,dec));
545 
      when TSUBCCTV => return(tostf(insn.pc) & bb & "tsubcctv" & bl2 & regres(insn,dec));
546 
      when MULSCC => return(tostf(insn.pc) & bb & "mulscc" & bl2 & regres(insn,dec));
547 
      when ISLL => return(tostf(insn.pc) & bb & "sll" & bl2 & regres(insn,dec));
548 
      when ISRL => return(tostf(insn.pc) & bb & "srl" & bl2 & regres(insn,dec));
549 
      when ISRA => return(tostf(insn.pc) & bb & "sra" & bl2 & regres(insn,dec));
550 
      when RDY  =>
551 
        if rs1 /= "00000" then
552 
          return(tostf(insn.pc) & bb & "mov" & bl2 & "%asr" &
553 
                 tost(rs1) & ", " & regdec(rd));
554 
        else
555 
          return(tostf(insn.pc) & bb & "mov" & bl2 & "%y, " & regdec(rd));
556 
        end if;
557 
      when RDPSR  => return(tostf(insn.pc) & bb & "mov" & bl2 & "%psr, " & regdec(rd));
558 
      when RDWIM  => return(tostf(insn.pc) & bb & "mov" & bl2 & "%wim, " & regdec(rd));
559 
      when RDTBR  => return(tostf(insn.pc) & bb & "mov" & bl2 & "%tbr, " & regdec(rd));
560 
      when WRY  =>
561 
        if (rs1 = "00000") or (rs2 = "00000") then
562 
          if rd /= "00000" then
563 
            return(tostf(insn.pc) & bb & "mov" & bl2
564 
                 & regimm(insn,hex,false) & ", %asr" & tost(rd));
565 
          else
566 
            return(tostf(insn.pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %y");
567 
          end if;
568 
        else
569 
          if rd /= "00000" then
570 
            return(tostf(insn.pc) & bb & "wr " & bl2 & "%asr"
571 
                 & regimm(insn,hex,false) & ", %asr" & tost(rd));
572 
          else
573 
            return(tostf(insn.pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %y");
574 
          end if;
575 
        end if;
576 
      when WRPSR  =>
577 
        if (rs1 = "00000") or (rs2 = "00000") then
578 
          return(tostf(insn.pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %psr");
579 
        else
580 
          return(tostf(insn.pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %psr");
581 
        end if;
582 
      when WRWIM  =>
583 
        if (rs1 = "00000") or (rs2 = "00000") then
584 
          return(tostf(insn.pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %wim");
585 
        else
586 
          return(tostf(insn.pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %wim");
587 
        end if;
588 
      when WRTBR  =>
589 
        if (rs1 = "00000") or (rs2 = "00000") then
590 
          return(tostf(insn.pc) & bb & "mov" & bl2 & regimm(insn,hex,false) & ", %tbr");
591 
        else
592 
          return(tostf(insn.pc) & bb & "wr " & bl2 & regimm(insn,hex,false) & ", %tbr");
593 
        end if;
594 
      when JMPL =>
595 
        if (rd = "00000") then
596 
          if (i = '1') and (simm = "0000000001000") then
597 
            if (rs1 = "11111") then
598 
              return(tostf(insn.pc) & bb & "ret");
599 
            elsif (rs1 = "01111") then
600 
              return(tostf(insn.pc) & bb & "retl");
601 
            else
602 
              return(tostf(insn.pc) & bb & "jmp" & bl2 & regimm(insn,dec,true));
603 
            end if;
604 
          else
605 
            return(tostf(insn.pc) & bb & "jmp" & bl2 & regimm(insn,dec,true));
606 
          end if;
607 
        else
608 
          return(tostf(insn.pc) & bb & "jmpl" & bl2 & regres(insn,dec));
609 
        end if;
610 
      when TICC =>
611 
        return(tostf(insn.pc) & bb & 't' & branchop(insn) & bl2 & regimm(insn,hex,false));
612 
      when FLUSH =>
613 
        return(tostf(insn.pc) & bb & "flush" & bl2 & regimm(insn,hex,false));
614 
      when RETT =>
615 
        return(tostf(insn.pc) & bb & "rett" & bl2 & regimm(insn,dec,false));
616 
      when RESTORE =>
617 
        if (rd = "00000") then
618 
          return(tostf(insn.pc) & bb & "restore");
619 
        else
620 
          return(tostf(insn.pc) & bb & "restore" & bl2 & regres(insn,hex));
621 
        end if;
622 
      when SAVE =>
623 
        if (rd = "00000") then
624 
          return(tostf(insn.pc) & bb & "save");
625 
        else
626 
          return(tostf(insn.pc) & bb & "save" & bl2 & regres(insn,dec));
627 
        end if;
628 
      when FPOP1 =>
629 
        case opf is
630 
        when FITOS => return(tostf(insn.pc) & bb & "fitos" & bl2 & freg2(insn));
631 
        when FITOD => return(tostf(insn.pc) & bb & "fitod" & bl2 & freg2(insn));
632 
        when FSTOI => return(tostf(insn.pc) & bb & "fstoi" & bl2 & freg2(insn));
633 
        when FDTOI => return(tostf(insn.pc) & bb & "fdtoi" & bl2 & freg2(insn));
634 
        when FSTOD => return(tostf(insn.pc) & bb & "fstod" & bl2 & freg2(insn));
635 
        when FDTOS => return(tostf(insn.pc) & bb & "fdtos" & bl2 & freg2(insn));
636 
        when FMOVS => return(tostf(insn.pc) & bb & "fmovs" & bl2 & freg2(insn));
637 
        when FNEGS => return(tostf(insn.pc) & bb & "fnegs" & bl2 & freg2(insn));
638 
        when FABSS => return(tostf(insn.pc) & bb & "fabss" & bl2 & freg2(insn));
639 
        when FSQRTS => return(tostf(insn.pc) & bb & "fsqrts" & bl2 & freg2(insn));
640 
        when FSQRTD => return(tostf(insn.pc) & bb & "fsqrtd" & bl2 & freg2(insn));
641 
        when FADDS => return(tostf(insn.pc) & bb & "fadds" & bl2 & freg3(insn));
642 
        when FADDD => return(tostf(insn.pc) & bb & "faddd" & bl2 & freg3(insn));
643 
        when FSUBS => return(tostf(insn.pc) & bb & "fsubs" & bl2 & freg3(insn));
644 
        when FSUBD => return(tostf(insn.pc) & bb & "fsubd" & bl2 & freg3(insn));
645 
        when FMULS => return(tostf(insn.pc) & bb & "fmuls" & bl2 & freg3(insn));
646 
        when FMULD => return(tostf(insn.pc) & bb & "fmuld" & bl2 & freg3(insn));
647 
        when FSMULD => return(tostf(insn.pc) & bb & "fsmuld" & bl2 & freg3(insn));
648 
        when FDIVS => return(tostf(insn.pc) & bb & "fdivs" & bl2 & freg3(insn));
649 
        when FDIVD => return(tostf(insn.pc) & bb & "fdivd" & bl2 & freg3(insn));
650 
        when others => return(tostf(insn.pc) & bb & "unknown Fopcode: " & tost(insn.op));
651 
        end case;
652 
      when FPOP2 =>
653 
        case opf is
654 
        when FCMPS => return(tostf(insn.pc) & bb & "fcmps" & bl2 & fregc(insn));
655 
        when FCMPD => return(tostf(insn.pc) & bb & "fcmpd" & bl2 & fregc(insn));
656 
        when FCMPES => return(tostf(insn.pc) & bb & "fcmpes" & bl2 & fregc(insn));
657 
        when FCMPED => return(tostf(insn.pc) & bb & "fcmped" & bl2 & fregc(insn));
658 
        when others => return(tostf(insn.pc) & bb & "unknown Fopcode: " & tost(insn.op));
659 
        end case;
660 
      when CPOP1 =>
661 
        return(tostf(insn.pc) & bb & "cpop1" & bl2 & tost("000"&opf) & ", " &creg3(insn));
662 
      when CPOP2 =>
663 
        return(tostf(insn.pc) & bb & "cpop2" & bl2 & tost("000"&opf) & ", " &creg3(insn));
664 
      when others => return(tostf(insn.pc) & bb & "unknown opcode: " & tost(insn.op));
665 
      end case;
666 
    when LDST =>
667 
      case op3 is
668 
      when STC =>
669 
        return(tostf(insn.pc) & bb & "st" & bl2 & stparcp(insn, rd, dec));
670 
      when STF =>
671 
        return(tostf(insn.pc) & bb & "st" & bl2 & stparf(insn, rd, dec));
672 
      when ST =>
673 
        if rd = "00000" then
674 
          return(tostf(insn.pc) & bb & "clr" & bl2 & stparc(insn, rd, dec));
675 
        else
676 
          return(tostf(insn.pc) & bb & "st" & bl2 & stpar(insn, rd, dec));
677 
        end if;
678 
      when STB =>
679 
        if rd = "00000" then
680 
          return(tostf(insn.pc) & bb & "clrb" & bl2 & stparc(insn, rd, dec));
681 
        else
682 
          return(tostf(insn.pc) & bb & "stb" & bl2 & stpar(insn, rd, dec));
683 
        end if;
684 
      when STH =>
685 
        if rd = "00000" then
686 
          return(tostf(insn.pc) & bb & "clrh" & bl2 & stparc(insn, rd, dec));
687 
        else
688 
          return(tostf(insn.pc) & bb & "sth" & bl2 & stpar(insn, rd, dec));
689 
        end if;
690 
      when STDC =>
691 
        return(tostf(insn.pc) & bb & "std" & bl2 & stparcp(insn, rd, dec));
692 
      when STDF =>
693 
        return(tostf(insn.pc) & bb & "std" & bl2 & stparf(insn, rd, dec));
694 
      when STCSR =>
695 
        return(tostf(insn.pc) & bb & "st" & bl2 & "%csr, [" & regimm(insn,dec,true) & "]");
696 
      when STFSR =>
697 
        return(tostf(insn.pc) & bb & "st" & bl2 & "%fsr, [" & regimm(insn,dec,true) & "]");
698 
      when STDCQ =>
699 
        return(tostf(insn.pc) & bb & "std" & bl2 & "%cq, [" & regimm(insn,dec,true) & "]");
700 
      when STDFQ =>
701 
        return(tostf(insn.pc) & bb & "std" & bl2 & "%fq, [" & regimm(insn,dec,true) & "]");
702 
      when ISTD =>
703 
        return(tostf(insn.pc) & bb & "std" & bl2 & stpar(insn, rd, dec));
704 
      when STA =>
705 
        return(tostf(insn.pc) & bb & "sta" & bl2 & stpara(insn, rd, dec));
706 
      when STBA =>
707 
        return(tostf(insn.pc) & bb & "stba" & bl2 & stpara(insn, rd, dec));
708 
      when STHA =>
709 
        return(tostf(insn.pc) & bb & "stha" & bl2 & stpara(insn, rd, dec));
710 
      when STDA =>
711 
        return(tostf(insn.pc) & bb & "stda" & bl2 & stpara(insn, rd, dec));
712 
      when LDC =>
713 
        return(tostf(insn.pc) & bb & "ld" & bl2 & ldparcp(insn, rd, dec));
714 
      when LDF =>
715 
        return(tostf(insn.pc) & bb & "ld" & bl2 & ldparf(insn, rd, dec));
716 
      when LDCSR =>
717 
        return(tostf(insn.pc) & bb & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %csr");
718 
      when LDFSR =>
719 
        return(tostf(insn.pc) & bb & "ld" & bl2 & "[" & regimm(insn,dec,true) & "]" & ", %fsr");
720 
      when LD =>
721 
        return(tostf(insn.pc) & bb & "ld" & bl2 & ldpar(insn, rd, dec));
722 
      when LDUB =>
723 
        return(tostf(insn.pc) & bb & "ldub" & bl2 & ldpar(insn, rd, dec));
724 
      when LDUH =>
725 
        return(tostf(insn.pc) & bb & "lduh" & bl2 & ldpar(insn, rd, dec));
726 
      when LDDC =>
727 
        return(tostf(insn.pc) & bb & "ldd" & bl2 & ldparcp(insn, rd, dec));
728 
      when LDDF =>
729 
        return(tostf(insn.pc) & bb & "ldd" & bl2 & ldparf(insn, rd, dec));
730 
      when LDD =>
731 
        return(tostf(insn.pc) & bb & "ldd" & bl2 & ldpar(insn, rd, dec));
732 
      when LDSB =>
733 
        return(tostf(insn.pc) & bb & "ldsb" & bl2 & ldpar(insn, rd, dec));
734 
      when LDSH =>
735 
        return(tostf(insn.pc) & bb & "ldsh" & bl2 & ldpar(insn, rd, dec));
736 
      when LDSTUB =>
737 
        return(tostf(insn.pc) & bb & "ldstub" & bl2 & ldpar(insn, rd, dec));
738 
      when SWAP   =>
739 
        return(tostf(insn.pc) & bb & "swap" & bl2 & ldpar(insn, rd, dec));
740 
      when LDA =>
741 
        return(tostf(insn.pc) & bb & "lda" & bl2 & ldpara(insn, rd, dec));
742 
      when LDUBA =>
743 
        return(tostf(insn.pc) & bb & "lduba" & bl2 & ldpara(insn, rd, dec));
744 
      when LDUHA =>
745 
        return(tostf(insn.pc) & bb & "lduha" & bl2 & ldpara(insn, rd, dec));
746 
      when LDDA =>
747 
        return(tostf(insn.pc) & bb & "ldda" & bl2 & ldpara(insn, rd, dec));
748 
      when LDSBA =>
749 
        return(tostf(insn.pc) & bb & "ldsba" & bl2 & ldpara(insn, rd, dec));
750 
      when LDSHA =>
751 
        return(tostf(insn.pc) & bb & "ldsha" & bl2 & ldpara(insn, rd, dec));
752 
      when LDSTUBA =>
753 
        return(tostf(insn.pc) & bb & "ldstuba" & bl2 & ldpara(insn, rd, dec));
754 
      when SWAPA   =>
755 
        return(tostf(insn.pc) & bb & "swapa" & bl2 & ldpara(insn, rd, dec));
756 
 
757 
      when others => return(tostf(insn.pc) & bb & "unknown opcode: " & tost(insn.op));
758 
      end case;
759 
    when others => return(tostf(insn.pc) & bb & "unknown opcode: " & tost(insn.op));
760 
    end case;
761 
 
762 
  end if;
763 
end;
764 
 
765 
procedure print(s : string) is
766 
    variable L1 : line;
767 
begin
768 
  L1:= new string'(s);  --'
769 
--  write(L1, s);
770 
  writeline(output,L1);
771 
end;
772 
 
773 
procedure trace(signal debug : in iu_debug_out_type; DISASS : boolean) is
774 
  variable insn    : debug_info;
775 
  variable wr_annul : std_logic;
776 
begin
777 
  if DEBUGFPU and (FPIFTYPE = parallel) and (FPCORE = grfpu) then
778 
    wr_annul := debug.wr.annul or debug.fpdbg.wr_fp;
779 
  else
780 
    wr_annul := debug.wr.annul;
781 
  end if;
782 
  if DISASS or DEBUGFPU then
783 
    if (debug.rst = '1') and debug.clk'event and (debug.clk = '1') and ((debug.holdn = '1')) then --'
784 
      insn.op := debug.wr.inst;
785 
      insn.pc := debug.wr.pc(31 downto 2) & "00";
786 
      if (((not wr_annul) and debug.wr.pv) = '1') and
787 
        not (DEBUG_UNIT and (debug.vdmode = '1'))
788 
      then
789 
        if DISASS then
790 
          if debug.trap = '1' then
791 
            print (disas(insn) & "  (trapped, tt = " & tostf(debug.tt) & ")");
792 
 
793 
          else
794 
            print (disas(insn));
795 
          end if;
796 
        end if;
797 
      end if;
798 
      if wr_annul = '0' then
799 
        if DEBUGIURF then
800 
          if (debug.write_reg = '1') then
801 
            print(tostf(insn.pc) & ": %r" & tost(debug.wr.rd) & " = " & tost(debug.result));
802 
          end if;
803 
        end if;
804 
        if DEBUGFPU and (FPIFTYPE = serial) then
805 
          if (debug.write_reg = '1') and (debug.wr.rd(7 downto 5) = "100") then
806 
            print(tosth(insn.pc) & ": %f" & tostd(debug.wr.rd(4 downto 0)) &
807 
                " = " & tosth(debug.result));
808 
          end if;
809 
        end if;
810 
      end if;
811 
      if (DEBUGFPU or DISASS) and (FPIFTYPE = parallel) and (FPCORE = grfpu) then
812 
        insn.op := debug.fpdbg.op;
813 
        insn.pc := debug.fpdbg.pc(31 downto 2) & "00";
814 
        if debug.fpdbg.wr2_fp = '1' then
815 
          if DISASS then
816 
            print(disas(insn));
817 
          end if;
818 
          if DEBUGFPU then
819 
            if debug.fpdbg.write_fpreg(0) = '1' then
820 
              print(tostf(insn.pc) & ": %f" & tostd(debug.fpdbg.fpreg & '0') & " = " & tostf(debug.fpdbg.ddata(63 downto 32)));
821 
            end if;
822 
            if debug.fpdbg.write_fpreg(1) = '1' then
823 
              print(tostf(insn.pc) & ": %f" & tostd(debug.fpdbg.fpreg & '1') & " = " & tostf(debug.fpdbg.ddata(31 downto 0)));
824 
            end if;
825 
            if debug.fpdbg.write_fsr = '1' then
826 
              print(tostf(insn.pc) & ": %fsr" & " = " & tostf(debug.fpdbg.ddata(63 downto 32)));
827 
            end if;
828 
          end if;
829 
        end if;
830 
      end if;
831 
    end if;
832 
  end if;
833 
end;
834 
 
835 
end debug;

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