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----------------------------------------------------------------------------
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-- This file is a part of the LEON VHDL model
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-- Copyright (C) 1999 European Space Agency (ESA)
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--
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2 of the License, or (at your option) any later version.
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--
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-- See the file COPYING.LGPL for the full details of the license.
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-----------------------------------------------------------------------------
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-- Entity: dsu_mem
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-- File: dsu_mem.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: DSU trace buffer memory
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use work.leon_target.all;
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use work.leon_config.all;
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use work.leon_iface.all;
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use work.tech_map.all;
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entity dsu_mem is
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port (
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clk : in clk_type;
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dmi : in dsumem_in_type;
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dmo : out dsumem_out_type
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);
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end;
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architecture rtl of dsu_mem is
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begin
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nomix : if DSUTRACE and not DSUMIXED generate
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spram0 : if not DSUDPRAM generate
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mem0 : for i in 0 to 3 generate
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ram0 : syncram generic map ( dbits => 32, abits => TBUFABITS)
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port map ( dmi.pbufi.addr(TBUFABITS-1 downto 0), clk,
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dmi.pbufi.data(((i*32)+31) downto (i*32)),
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dmo.pbufo.data(((i*32)+31) downto (i*32)), dmi.pbufi.enable, dmi.pbufi.write(i));
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end generate;
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end generate;
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dpram0 : if DSUDPRAM generate
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mem0 : for i in 0 to 1 generate
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ram0 : dpsyncram generic map ( dbits => 32, abits => TBUFABITS+1)
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port map ( dmi.pbufi.addr(TBUFABITS downto 0), clk,
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dmi.pbufi.data(((i*32)+31) downto (i*32)),
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dmo.pbufo.data(((i*32)+31) downto (i*32)), dmi.pbufi.enable, dmi.pbufi.write(i),
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dmi.abufi.addr(TBUFABITS downto 0),
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dmi.pbufi.data(((i*32)+31+64) downto (i*32+64)),
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dmo.pbufo.data(((i*32)+31+64) downto (i*32+64)), dmi.pbufi.enable,
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dmi.pbufi.write(i+2));
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end generate;
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end generate;
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end generate;
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tbmix : if DSUTRACE and DSUMIXED generate
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spram0 : if not DSUDPRAM generate
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mem0 : for i in 0 to 3 generate
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ram0 : syncram generic map ( dbits => 32, abits => TBUFABITS-1)
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port map ( dmi.pbufi.addr(TBUFABITS-2 downto 0), clk,
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dmi.pbufi.data(((i*32)+31) downto (i*32)),
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dmo.pbufo.data(((i*32)+31) downto (i*32)),
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dmi.pbufi.enable, dmi.pbufi.write(i));
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end generate;
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mem1 : for i in 0 to 3 generate
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ram0 : syncram generic map ( dbits => 32, abits => TBUFABITS-1)
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port map ( dmi.abufi.addr(TBUFABITS-2 downto 0), clk,
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dmi.abufi.data(((i*32)+31) downto (i*32)),
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dmo.abufo.data(((i*32)+31) downto (i*32)),
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dmi.abufi.enable, dmi.abufi.write(i));
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end generate;
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end generate;
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dpram0 : if DSUDPRAM generate
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mem0 : for i in 0 to 3 generate
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ram0 : dpsyncram generic map ( dbits => 32, abits => TBUFABITS)
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port map ( dmi.pbufi.addr(TBUFABITS-1 downto 0), clk,
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dmi.pbufi.data(((i*32)+31) downto (i*32)),
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dmo.pbufo.data(((i*32)+31) downto (i*32)),
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dmi.pbufi.enable, dmi.pbufi.write(i),
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dmi.abufi.addr(TBUFABITS-1 downto 0),
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dmi.abufi.data(((i*32)+31) downto (i*32)),
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dmo.abufo.data(((i*32)+31) downto (i*32)),
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dmi.abufi.enable, dmi.abufi.write(i));
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end generate;
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end generate;
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end generate;
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end;
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