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[/] [core_arm/] [trunk/] [vhdl/] [sparc/] [leon_device.v] - Blame information for rev 4

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`define HEADER_VENDOR_ID    16'h0000
`define HEADER_DEVICE_ID    16'h0000
`define HEADER_REVISION_ID  8'h00
 
`define ETH_WISHBONE_B3
 
`define ETH_TX_FIFO_CNT_WIDTH  8_log2%
`define ETH_TX_FIFO_DEPTH      8
 
`define ETH_RX_FIFO_CNT_WIDTH  4
`define ETH_RX_FIFO_DEPTH      8
 
`define ETH_BURST_CNT_WIDTH    3
`define ETH_BURST_LENGTH       4
 
 
`define FPGA
`define XILINX
`define WBW_ADDR_LENGTH 7
`define WBR_ADDR_LENGTH 7
`define PCIW_ADDR_LENGTH 7
`define PCIR_ADDR_LENGTH 7
`define PCI_FIFO_RAM_ADDR_LENGTH 8
`define WB_FIFO_RAM_ADDR_LENGTH 8
 
 

Line No.	Rev	Author	Line
1	2	tarookumic
2			`define HEADER_VENDOR_ID 16'h0000
3			`define HEADER_DEVICE_ID 16'h0000
4			`define HEADER_REVISION_ID 8'h00
5
6			`define ETH_WISHBONE_B3
7
8			`define ETH_TX_FIFO_CNT_WIDTH 8_log2%
9			`define ETH_TX_FIFO_DEPTH 8
10
11			`define ETH_RX_FIFO_CNT_WIDTH 4
12			`define ETH_RX_FIFO_DEPTH 8
13
14			`define ETH_BURST_CNT_WIDTH 3
15			`define ETH_BURST_LENGTH 4
16
17
18			`define FPGA
19			`define XILINX
20			`define WBW_ADDR_LENGTH 7
21			`define WBR_ADDR_LENGTH 7
22			`define PCIW_ADDR_LENGTH 7
23			`define PCIR_ADDR_LENGTH 7
24			`define PCI_FIFO_RAM_ADDR_LENGTH 8
25			`define WB_FIFO_RAM_ADDR_LENGTH 8
26
27

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[/] [core_arm/] [trunk/] [vhdl/] [sparc/] [leon_device.v] - Blame information for rev 4