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[/] [core_arm/] [trunk/] [vhdl/] [sparc/] [macro.vhd] - Blame information for rev 4

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----------------------------------------------------------------------------
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--  This file is a part of the LEON VHDL model
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--  Copyright (C) 1999  European Space Agency (ESA)
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--
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--  This library is free software; you can redistribute it and/or
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--  modify it under the terms of the GNU Lesser General Public
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--  License as published by the Free Software Foundation; either
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--  version 2 of the License, or (at your option) any later version.
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--
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--  See the file COPYING.LGPL for the full details of the license.
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-----------------------------------------------------------------------------
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-- Entity:      macro
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-- File:        macro.vhd
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-- Author:      Jiri Gaisler - ESA/ESTEC
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-- Description: some common macro functions
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------------------------------------------------------------------------------
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-- Version control:
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-- 29-11-1997:  First implemetation
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-- 26-09-1999:  Release 1.0
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------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use work.leon_target.all;
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use work.leon_config.all;
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use work.leon_iface.all;
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package macro is
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constant zero32 : std_Logic_vector(31 downto 0) := (others => '0');
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function decode(v : std_logic_vector) return std_logic_vector;
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function genmux(s,v : std_logic_vector) return std_logic;
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function xorv(d : std_logic_vector) return std_logic;
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function orv(d : std_logic_vector) return std_logic;
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-- 3-way set permutations
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-- s012 => set 0 - least recently used
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--         set 2 - most recently used
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constant s012 : std_logic_vector(2 downto 0) := "000";
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constant s021 : std_logic_vector(2 downto 0) := "001";
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constant s102 : std_logic_vector(2 downto 0) := "010";
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constant s120 : std_logic_vector(2 downto 0) := "011";
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constant s201 : std_logic_vector(2 downto 0) := "100";
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constant s210 : std_logic_vector(2 downto 0) := "101";
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-- 4-way set permutations
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-- s0123 => set 0 - least recently used
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--          set 3 - most recently used
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constant s0123 : std_logic_vector(4 downto 0) := "00000";
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constant s0132 : std_logic_vector(4 downto 0) := "00001";
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constant s0213 : std_logic_vector(4 downto 0) := "00010";
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constant s0231 : std_logic_vector(4 downto 0) := "00011";
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constant s0312 : std_logic_vector(4 downto 0) := "00100";
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constant s0321 : std_logic_vector(4 downto 0) := "00101";
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constant s1023 : std_logic_vector(4 downto 0) := "00110";
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constant s1032 : std_logic_vector(4 downto 0) := "00111";
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constant s1203 : std_logic_vector(4 downto 0) := "01000";
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constant s1230 : std_logic_vector(4 downto 0) := "01001";
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constant s1302 : std_logic_vector(4 downto 0) := "01010";
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constant s1320 : std_logic_vector(4 downto 0) := "01011";
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constant s2013 : std_logic_vector(4 downto 0) := "01100";
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constant s2031 : std_logic_vector(4 downto 0) := "01101";
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constant s2103 : std_logic_vector(4 downto 0) := "01110";
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constant s2130 : std_logic_vector(4 downto 0) := "01111";
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constant s2301 : std_logic_vector(4 downto 0) := "10000";
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constant s2310 : std_logic_vector(4 downto 0) := "10001";
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constant s3012 : std_logic_vector(4 downto 0) := "10010";
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constant s3021 : std_logic_vector(4 downto 0) := "10011";
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constant s3102 : std_logic_vector(4 downto 0) := "10100";
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constant s3120 : std_logic_vector(4 downto 0) := "10101";
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constant s3201 : std_logic_vector(4 downto 0) := "10110";
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constant s3210 : std_logic_vector(4 downto 0) := "10111";
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type lru_3set_table_vector_type is array(0 to 2) of std_logic_vector(2 downto 0);
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type lru_3set_table_type is array (0 to 7) of lru_3set_table_vector_type;
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constant lru_3set_table : lru_3set_table_type :=
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  ( (s120, s021, s012),                   -- s012
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    (s210, s021, s012),                   -- s021
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    (s120, s021, s102),                   -- s102
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    (s120, s201, s102),                   -- s120
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    (s210, s201, s012),                   -- s201
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    (s210, s201, s102),                   -- s210
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    (s210, s201, s102),                   -- dummy
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    (s210, s201, s102)                    -- dummy
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  );
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type lru_4set_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0);
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type lru_4set_table_type is array(0 to 31) of lru_4set_table_vector_type;
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constant lru_4set_table : lru_4set_table_type :=
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  ( (s1230, s0231, s0132, s0123),       -- s0123
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    (s1320, s0321, s0132, s0123),       -- s0132
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    (s2130, s0231, s0132, s0213),       -- s0213
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    (s2310, s0231, s0312, s0213),       -- s0231
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    (s3120, s0321, s0312, s0123),       -- s0312    
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    (s3210, s0321, s0312, s0213),       -- s0321
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    (s1230, s0231, s1032, s1023),       -- s1023
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    (s1320, s0321, s1032, s1023),       -- s1032
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    (s1230, s2031, s1032, s1203),       -- s1203
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    (s1230, s2301, s1302, s1203),       -- s1230
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    (s1320, s3021, s1302, s1023),       -- s1302
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    (s1320, s3201, s1302, s1203),       -- s1320
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    (s2130, s2031, s0132, s2013),       -- s2013
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    (s2310, s2031, s0312, s2013),       -- s2031
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    (s2130, s2031, s1032, s2103),       -- s2103
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    (s2130, s2301, s1302, s2103),       -- s2130      
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    (s2310, s2301, s3012, s2013),       -- s2301
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    (s2310, s2301, s3102, s2103),       -- s2310
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    (s3120, s3021, s3012, s0123),       -- s3012
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    (s3210, s3021, s3012, s0213),       -- s3021
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    (s3120, s3021, s3102, s1023),       -- s3102
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    (s3120, s3201, s3102, s1203),       -- s3120
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    (s3210, s3201, s3012, s2013),       -- s3201
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    (s3210, s3201, s3102, s2103),       -- s3210
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    (s3210, s3201, s3102, s2103),        -- dummy
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    (s3210, s3201, s3102, s2103),        -- dummy
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    (s3210, s3201, s3102, s2103),        -- dummy
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    (s3210, s3201, s3102, s2103),        -- dummy
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    (s3210, s3201, s3102, s2103),        -- dummy
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    (s3210, s3201, s3102, s2103),        -- dummy
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    (s3210, s3201, s3102, s2103),        -- dummy
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    (s3210, s3201, s3102, s2103)         -- dummy
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  );
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type lru3_repl_table_single_type is array(0 to 2) of integer range 0 to 2;
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type lru3_repl_table_type is array(0 to 7) of lru3_repl_table_single_type;
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constant lru3_repl_table : lru3_repl_table_type :=
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  ( (0, 1, 2),      -- s012
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    (0, 2, 2),      -- s021
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    (1, 1, 2),      -- s102
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    (1, 1, 2),      -- s120
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    (2, 2, 2),      -- s201
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    (2, 2, 2),      -- s210
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    (2, 2, 2),      -- dummy
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    (2, 2, 2)       -- dummy
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  );
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type lru4_repl_table_single_type is array(0 to 3) of integer range 0 to 3;
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type lru4_repl_table_type is array(0 to 31) of lru4_repl_table_single_type;
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constant lru4_repl_table : lru4_repl_table_type :=
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  ( (0, 1, 2, 3), -- s0123
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    (0, 1, 3, 3), -- s0132
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    (0, 2, 2, 3), -- s0213
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    (0, 2, 2, 3), -- s0231
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    (0, 3, 3, 3), -- s0312
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    (0, 3, 3, 3), -- s0321
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    (1, 1, 2, 3), -- s1023
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    (1, 1, 3, 3), -- s1032
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    (1, 1, 2, 3), -- s1203
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    (1, 1, 2, 3), -- s1230
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    (1, 1, 3, 3), -- s1302
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    (1, 1, 3, 3), -- s1320
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    (2, 2, 2, 3), -- s2013
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    (2, 2, 2, 3), -- s2031
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    (2, 2, 2, 3), -- s2103
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    (2, 2, 2, 3), -- s2130
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    (2, 2, 2, 3), -- s2301
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    (2, 2, 2, 3), -- s2310
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    (3, 3, 3, 3), -- s3012
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    (3, 3, 3, 3), -- s3021
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    (3, 3, 3, 3), -- s3102
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    (3, 3, 3, 3), -- s3120
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    (3, 3, 3, 3), -- s3201
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    (3, 3, 3, 3), -- s3210
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    (0, 0, 0, 0), -- dummy
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    (0, 0, 0, 0), -- dummy
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    (0, 0, 0, 0), -- dummy
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    (0, 0, 0, 0), -- dummy
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    (0, 0, 0, 0), -- dummy
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    (0, 0, 0, 0), -- dummy
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    (0, 0, 0, 0), -- dummy
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    (0, 0, 0, 0)  -- dummy
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  );
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function is_cacheable(haddr : std_logic_vector(31 downto 24)) return std_logic;
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end;
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package body macro is
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-- generic decoder
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function decode(v : std_logic_vector) return std_logic_vector is
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variable res : std_logic_vector((2**v'length)-1 downto 0); --'
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variable i : natural;
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begin
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  res := (others => '0');
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-- pragma translate_off
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  i := 0;
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  if not is_x(v) then
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-- pragma translate_on
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    i := conv_integer(unsigned(v));
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    res(i) := '1';
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-- pragma translate_off
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  else
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    res := (others => 'X');
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  end if;
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-- pragma translate_on
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  return(res);
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end;
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-- generic multiplexer
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function genmux(s,v : std_logic_vector) return std_logic is
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variable res : std_logic_vector(v'length-1 downto 0); --'
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variable i : integer;
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begin
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  res := v;
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-- pragma translate_off
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  i := 0;
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  if not is_x(s) then
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-- pragma translate_on
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    i := conv_integer(unsigned(s));
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-- pragma translate_off
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  else
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    res := (others => 'X');
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  end if;
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-- pragma translate_on
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  return(res(i));
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end;
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-- vector XOR
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function xorv(d : std_logic_vector) return std_logic is
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variable tmp : std_logic;
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begin
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  tmp := '0';
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  for i in d'range loop tmp := tmp xor d(i); end loop; --'
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  return(tmp);
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end;
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-- vector OR
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function orv(d : std_logic_vector) return std_logic is
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variable tmp : std_logic;
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begin
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  tmp := '0';
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  for i in d'range loop tmp := tmp or d(i); end loop; --'
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  return(tmp);
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end;
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function is_cacheable(haddr : std_logic_vector(31 downto 24)) return std_logic is
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variable hcache : std_logic;
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begin
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--  hcache := '0';
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--  for i in PROC_CACHETABLE'range loop --'
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--    if (haddr(31 downto 32-PROC_CACHE_ADDR_MSB) >= PROC_CACHETABLE(i).firstaddr) and
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--      (haddr(31 downto 32-PROC_CACHE_ADDR_MSB) < PROC_CACHETABLE(i).lastaddr) 
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--    then hcache := '1';  end if;
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--  end loop;
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--  return(hcache);
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  if (haddr(31) = '0') and (haddr(30 downto 29) /= "01") then hcache := '1';
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  else hcache := '0'; end if;
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  return(hcache);
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end;
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end;
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