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-------------------------------------------------------------------------------
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-- Title : PCI interface for LEON processor
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-- Project : pci4leon
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-------------------------------------------------------------------------------
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-- File : pci.vhd
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-- Author : Roland Weigand <weigand@ws.estec.esa.nl>
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-- Created : 2000/02/29
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-- Last modified : 2000/02/29
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-------------------------------------------------------------------------------
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-- Description :
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-- This Unit is the top level of the PCI interface. It is connected
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-- to the peripheral bus of LEON and the DMA port.
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-- PCI ports must be connected to the top level pads.
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-- It includes the Phoenix/In-Silicon PCI core
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-------------------------------------------------------------------------------
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-- THIS IS JUST A DUMMY VERSION TO TEST THE LEON/AHB INTERFACE
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use work.amba.all;
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use work.leon_iface.all;
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entity pci_is is
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port (
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rst_n : in std_logic;
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pciresetn : in std_logic;
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app_clk : in clk_type;
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pci_clk : in clk_type;
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-- peripheral bus
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pbi : in APB_Slv_In_Type; -- peripheral bus in
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pbo : out APB_Slv_Out_Type; -- peripheral bus out
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irq : out std_logic; -- interrupt request
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-- PCI-Target DMA-Port = AHB master
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TargetMasterOut : out ahb_mst_out_type; -- dma port out
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TargetMasterIn : in ahb_mst_in_type; -- dma port in
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-- TargetAsi : out std_logic_vector(3 downto 0); -- sparc ASI
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-- PCI PORTS for top level
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pci_in : in pci_in_type; -- PCI bus inputs
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pci_out : out pci_out_type; -- PCI bus outputs
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-- PCI-Initiator Word-Interface = AHB slave
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InitSlaveOut : out ahb_slv_out_type; -- Direct initiator I/F
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InitSlaveIn : in ahb_slv_in_type; -- Direct initiator I/F
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-- PCI-Intitiator DMA-Port = AHB master
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InitMasterOut : out ahb_mst_out_type; -- dma port out
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InitMasterIn : in ahb_mst_in_type -- dma port in
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-- InitAsi : out std_logic_vector(3 downto 0); -- sparc ASI
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);
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end;
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architecture struct of pci_is is
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begin
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InitMasterOut.haddr <= (others => '0') ;
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InitMasterOut.htrans <= HTRANS_IDLE;
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InitMasterOut.hbusreq <= '0';
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InitMasterOut.hwdata <= (others => '0');
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InitMasterOut.hlock <= '0';
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InitMasterOut.hwrite <= '0';
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InitMasterOut.hsize <= HSIZE_WORD;
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InitMasterOut.hburst <= HBURST_SINGLE;
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InitMasterOut.hprot <= (others => '0');
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TargetMasterOut.haddr <= (others => '0') ;
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TargetMasterOut.htrans <= HTRANS_IDLE;
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TargetMasterOut.hbusreq <= '0';
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TargetMasterOut.hwdata <= (others => '0');
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TargetMasterOut.hlock <= '0';
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TargetMasterOut.hwrite <= '0';
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TargetMasterOut.hsize <= HSIZE_WORD;
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TargetMasterOut.hburst <= HBURST_SINGLE;
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TargetMasterOut.hprot <= (others => '0');
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InitSlaveOut.hrdata <= (others => '0');
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InitSlaveOut.hready <= '1';
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InitSlaveOut.hresp <= HRESP_OKAY;
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irq <= '0';
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end;
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