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[/] [core_arm/] [trunk/] [vhdl/] [tbench/] [tbench_config.vhd] - Blame information for rev 6

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library ieee;
use ieee.std_logic_1164.all;
use work.tbench_comp.all;
 
entity tbench_config is
end tbench_config;
 
architecture behav of tbench_config is
    signal i       : tbench_gen_typ_in;
    signal o       : tbench_gen_typ_out;
begin
  tb0: tbench_gen port map (i,o);
end behav;
 
 
 

Line No.	Rev	Author	Line
1	2	tarookumic	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use work.tbench_comp.all;`
4
5			`entity tbench_config is`
6			`end tbench_config;`
7
8			`architecture behav of tbench_config is`
9			`signal i : tbench_gen_typ_in;`
10			`signal o : tbench_gen_typ_out;`
11			`begin`
12			`tb0: tbench_gen port map (i,o);`
13			`end behav;`
14
15
16

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[/] [core_arm/] [trunk/] [vhdl/] [tbench/] [tbench_config.vhd] - Blame information for rev 6