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[/] [core_arm/] [trunk/] [vhdl/] [tech/] [tech_atc18.vhd] - Blame information for rev 5

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----------------------------------------------------------------------------
6 
--  This file is a part of the LEON VHDL model
7 
--  Copyright (C) 1999  European Space Agency (ESA)
8 
--
9 
--  This library is free software; you can redistribute it and/or
10 
--  modify it under the terms of the GNU Lesser General Public
11 
--  License as published by the Free Software Foundation; either
12 
--  version 2 of the License, or (at your option) any later version.
13 
--
14 
--  See the file COPYING.LGPL for the full details of the license.
15 
 
16 
 
17 
-----------------------------------------------------------------------------
18 
-- Entity:      tech_atc18
19 
-- File:        tech_atc18.vhd
20 
-- Author:      Jiri Gaisler - Gaisler Research
21 
-- Description: Contains Atmel ATC18 specific pads and ram generators
22 
------------------------------------------------------------------------------
23 
 
24 
 
25 
 
26 
 
27 
LIBRARY ieee;
28 
use IEEE.std_logic_1164.all;
29 
use work.leon_iface.all;
30 
package tech_atc18 is
31 
 
32 
-- sync ram generator
33 
 
34 
  component atc18_syncram
35 
  generic ( abits : integer := 10; dbits : integer := 8 );
36 
  port (
37 
    address  : in std_logic_vector(abits -1 downto 0);
38 
    clk      : in clk_type;
39 
    datain   : in std_logic_vector(dbits -1 downto 0);
40 
    dataout  : out std_logic_vector(dbits -1 downto 0);
41 
    enable   : in std_logic;
42 
    write    : in std_logic);
43 
  end component;
44 
 
45 
-- IU regfile generator
46 
 
47 
component atc18_regfile_iu
48 
  generic (rftype : integer := 1; abits : integer := 8; dbits : integer := 32; words : integer := 136);
49 
  port (
50 
    rst      : in std_logic;
51 
    clk      : in clk_type;
52 
    clkn     : in clk_type;
53 
    rfi      : in rf_in_type;
54 
    rfo      : out rf_out_type);
55 
  end component;
56 
 
57 
component atc18_regfile_cp
58 
  generic (
59 
    abits : integer := 4;
60 
    dbits : integer := 32;
61 
    words : integer := 16
62 
  );
63 
  port (
64 
    rst      : in std_logic;
65 
    clk      : in clk_type;
66 
    rfi      : in rf_cp_in_type;
67 
    rfo      : out rf_cp_out_type);
68 
end component;
69 
 
70 
component atc18_dpram
71 
  generic ( abits : integer := 10; dbits : integer := 8 );
72 
  port (
73 
    address1 : in std_logic_vector((abits -1) downto 0);
74 
    clk      : in clk_type;
75 
    datain1  : in std_logic_vector((dbits -1) downto 0);
76 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
77 
    enable1  : in std_logic;
78 
    write1   : in std_logic;
79 
    address2 : in std_logic_vector((abits -1) downto 0);
80 
    datain2  : in std_logic_vector((dbits -1) downto 0);
81 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
82 
    enable2  : in std_logic;
83 
    write2   : in std_logic
84 
   );
85 
end component;
86 
 
87 
-- input pads, all others pads are taken from the atc25 package
88 
 
89 
  component atc18_inpad
90 
    port (pad : in std_logic; q : out std_logic);
91 
  end component;
92 
  component atc18_smpad
93 
    port (pad : in std_logic; q : out std_logic);
94 
  end component;
95 
 
96 
end;
97 
 
98 
------------------------------------------------------------------
99 
-- behavioural pad models --------------------------------------------
100 
------------------------------------------------------------------
101 
-- Only needed for simulation, not synthesis.
102 
-- pragma translate_off
103 
 
104 
-- input pad
105 
library IEEE;
106 
use IEEE.std_logic_1164.all;
107 
entity pc33d00 is port (pad : in std_logic; cin : out std_logic); end;
108 
architecture rtl of pc33d00 is begin cin <= to_x01(pad) after 1 ns; end;
109 
 
110 
-- input schmitt pad
111 
library IEEE;
112 
use IEEE.std_logic_1164.all;
113 
entity pc33d20 is port (pad : in std_logic; cin : out std_logic); end;
114 
architecture rtl of pc33d20 is begin cin <= to_x01(pad) after 1 ns; end;
115 
 
116 
------------------------------------------------------------------
117 
-- behavioural ram models ----------------------------------------
118 
------------------------------------------------------------------
119 
 
120 
-- synchronous 1-port ram
121 
 
122 
library ieee;
123 
use ieee.std_logic_1164.all;
124 
use ieee.std_logic_arith.all;
125 
 
126 
entity atc18_syncram_sim is
127 
  generic (
128 
    abits : integer := 10;
129 
    dbits : integer := 8
130 
  );
131 
  port (
132 
    addr  : in std_logic_vector((abits -1) downto 0);
133 
    clk   : in std_logic;
134 
    di    : in std_logic_vector((dbits -1) downto 0);
135 
    do    : out std_logic_vector((dbits -1) downto 0);
136 
    me    : in std_logic;
137 
    oe    : in std_logic;
138 
    we    : in std_logic
139 
  );
140 
end;
141 
 
142 
architecture behavioral of atc18_syncram_sim is
143 
  subtype word is std_logic_vector((dbits -1) downto 0);
144 
  type mem is array(0 to (2**abits -1)) of word;
145 
begin
146 
  main : process(clk, oe, me)
147 
  variable memarr : mem;
148 
  variable doint  : std_logic_vector((dbits -1) downto 0);
149 
  begin
150 
    if rising_edge(clk) and (me = '1') and not is_x(addr) then
151 
      if (we = '1') then memarr(conv_integer(unsigned(addr))) := di; end if;
152 
      doint := memarr(conv_integer(unsigned(addr)));
153 
    end if;
154 
    if (me and oe) = '1' then do <= doint;
155 
    else do <= (others => 'Z'); end if;
156 
  end process;
157 
end behavioral;
158 
 
159 
--  synchronous 2-port ram
160 
 
161 
LIBRARY ieee;
162 
use IEEE.std_logic_1164.all;
163 
use IEEE.std_logic_arith.all;
164 
 
165 
entity atc18_2pram_sim is
166 
  generic (
167 
    abits : integer := 10;
168 
    dbits : integer := 8;
169 
    words : integer := 1024
170 
  );
171 
  port (
172 
    addra, addrb  : in std_logic_vector((abits -1) downto 0);
173 
    clka, clkb   : in std_logic;
174 
    dia    : in std_logic_vector((dbits -1) downto 0);
175 
    dob    : out std_logic_vector((dbits -1) downto 0);
176 
    mea, wea, meb, oeb    : in std_logic
177 
  );
178 
end;
179 
 
180 
architecture behavioral of atc18_2pram_sim is
181 
  subtype word is std_logic_vector((dbits -1) downto 0);
182 
  type mem is array(0 to (words-1)) of word;
183 
begin
184 
  main : process(clka, clkb, oeb, mea, meb, wea)
185 
  variable memarr : mem;
186 
  variable doint  : std_logic_vector((dbits -1) downto 0);
187 
  begin
188 
    if rising_edge(clka) and (mea = '1') and not is_x(addra) then
189 
      if (wea = '1') then memarr(conv_integer(unsigned(addra)) mod words) := dia; end if;
190 
    end if;
191 
    if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
192 
      doint := memarr(conv_integer(unsigned(addrb)) mod words);
193 
    end if;
194 
    if (meb and oeb) = '1' then dob <= doint;
195 
    else dob <= (others => 'Z'); end if;
196 
  end process;
197 
end behavioral;
198 
 
199 
 
200 
--  synchronous dual-port ram
201 
 
202 
LIBRARY ieee;
203 
use IEEE.std_logic_1164.all;
204 
use IEEE.std_logic_arith.all;
205 
 
206 
entity atc18_dpram_sim is
207 
  generic (
208 
    abits : integer := 10;
209 
    dbits : integer := 8
210 
  );
211 
  port (
212 
    addra  : in std_logic_vector((abits -1) downto 0);
213 
    clka   : in std_logic;
214 
    dia    : in std_logic_vector((dbits -1) downto 0);
215 
    doa    : out std_logic_vector((dbits -1) downto 0);
216 
    mea, oea, wea : in std_logic;
217 
    addrb  : in std_logic_vector((abits -1) downto 0);
218 
    clkb   : in std_logic;
219 
    dib    : in std_logic_vector((dbits -1) downto 0);
220 
    dob    : out std_logic_vector((dbits -1) downto 0);
221 
    meb, oeb, web : in std_logic
222 
  );
223 
end;
224 
 
225 
architecture behavioral of atc18_dpram_sim is
226 
  subtype word is std_logic_vector((dbits -1) downto 0);
227 
  type mem is array(0 to (2**abits -1)) of word;
228 
begin
229 
  main : process(clka, oea, mea, clkb, oeb, meb)
230 
  variable memarr : mem;
231 
  variable dointa, dointb  : std_logic_vector((dbits -1) downto 0);
232 
  begin
233 
    if rising_edge(clka) and (mea = '1') and not is_x(addra) then
234 
      if (wea = '1') then memarr(conv_integer(unsigned(addra))) := dia; end if;
235 
      dointa := memarr(conv_integer(unsigned(addra)));
236 
    end if;
237 
    if (mea and oea) = '1' then doa <= dointa;
238 
    else doa <= (others => 'Z'); end if;
239 
    if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
240 
      if (web = '1') then memarr(conv_integer(unsigned(addrb))) := dib; end if;
241 
      dointb := memarr(conv_integer(unsigned(addrb)));
242 
    end if;
243 
    if (meb and oeb) = '1' then dob <= dointb;
244 
    else dob <= (others => 'Z'); end if;
245 
  end process;
246 
end behavioral;
247 
 
248 
-- package with common ram simulation models
249 
LIBRARY ieee;
250 
use IEEE.std_logic_1164.all;
251 
use work.leon_iface.all;
252 
package tech_atc18_sim is
253 
component atc18_syncram_sim
254 
  generic ( abits : integer := 10; dbits : integer := 8 );
255 
  port (
256 
    addr  : in std_logic_vector((abits -1) downto 0);
257 
    clk   : in std_logic;
258 
    di    : in std_logic_vector((dbits -1) downto 0);
259 
    do    : out std_logic_vector((dbits -1) downto 0);
260 
    me    : in std_logic;
261 
    oe    : in std_logic;
262 
    we    : in std_logic
263 
   );
264 
end component;
265 
 
266 
--  synchronous 2-port ram
267 
component atc18_2pram_sim
268 
  generic (
269 
    abits : integer := 8;
270 
    dbits : integer := 32;
271 
    words : integer := 256
272 
  );
273 
  port (
274 
    addra, addrb  : in std_logic_vector((abits -1) downto 0);
275 
    clka, clkb   : in std_logic;
276 
    dia    : in std_logic_vector((dbits -1) downto 0);
277 
    dob    : out std_logic_vector((dbits -1) downto 0);
278 
    mea, wea, meb, oeb    : in std_logic
279 
  );
280 
end component;
281 
 
282 
component atc18_dpram_sim
283 
  generic (
284 
    abits : integer := 8;
285 
    dbits : integer := 32
286 
  );
287 
  port (
288 
    addra  : in std_logic_vector((abits -1) downto 0);
289 
    clka   : in std_logic;
290 
    dia    : in std_logic_vector((dbits -1) downto 0);
291 
    doa    : out std_logic_vector((dbits -1) downto 0);
292 
    mea, oea, wea : in std_logic;
293 
    addrb  : in std_logic_vector((abits -1) downto 0);
294 
    clkb   : in std_logic;
295 
    dib    : in std_logic_vector((dbits -1) downto 0);
296 
    dob    : out std_logic_vector((dbits -1) downto 0);
297 
    meb, oeb, web : in std_logic
298 
  );
299 
end component;
300 
 
301 
end;
302 
 
303 
-- 1-port syncronous ram
304 
 
305 
library ieee;
306 
use IEEE.std_logic_1164.all;
307 
use work.tech_atc18_sim.all;
308 
entity hdss1_128x32cm4sw0 is
309 
  port (
310 
    addr, taddr : in std_logic_vector(6 downto 0);
311 
    clk         : in std_logic;
312 
    di, tdi     : in std_logic_vector(31 downto 0);
313 
    do          : out std_logic_vector(31 downto 0);
314 
    me, oe, we, tme, twe, awt, biste, toe : in std_logic
315 
  );
316 
end;
317 
architecture behavioral of hdss1_128x32cm4sw0 is
318 
begin
319 
  syncram0 : atc18_syncram_sim
320 
    generic map ( abits => 7, dbits => 32)
321 
    port map ( addr, clk, di, do, me, oe, we);
322 
end behavioral;
323 
 
324 
library ieee;
325 
use IEEE.std_logic_1164.all;
326 
use work.tech_atc18_sim.all;
327 
entity hdss1_256x32cm4sw0 is
328 
  port (
329 
    addr, taddr : in std_logic_vector(7 downto 0);
330 
    clk         : in std_logic;
331 
    di, tdi     : in std_logic_vector(31 downto 0);
332 
    do          : out std_logic_vector(31 downto 0);
333 
    me, oe, we, tme, twe, awt, biste, toe : in std_logic
334 
  );
335 
end;
336 
architecture behavioral of hdss1_256x32cm4sw0 is
337 
begin
338 
  syncram0 : atc18_syncram_sim
339 
    generic map ( abits => 8, dbits => 32)
340 
    port map ( addr, clk, di, do, me, oe, we);
341 
end behavioral;
342 
 
343 
library ieee;
344 
use IEEE.std_logic_1164.all;
345 
use work.tech_atc18_sim.all;
346 
entity hdss1_512x32cm4sw0 is
347 
  port (
348 
    addr, taddr : in std_logic_vector(8 downto 0);
349 
    clk         : in std_logic;
350 
    di, tdi     : in std_logic_vector(31 downto 0);
351 
    do          : out std_logic_vector(31 downto 0);
352 
    me, oe, we, tme, twe, awt, biste, toe : in std_logic
353 
  );
354 
end;
355 
architecture behavioral of hdss1_512x32cm4sw0 is
356 
begin
357 
  syncram0 : atc18_syncram_sim
358 
    generic map ( abits => 9, dbits => 32)
359 
    port map ( addr, clk, di, do, me, oe, we);
360 
end behavioral;
361 
 
362 
library ieee;
363 
use IEEE.std_logic_1164.all;
364 
use work.tech_atc18_sim.all;
365 
entity hdss1_1024x32cm4sw0 is
366 
  port (
367 
    addr, taddr : in std_logic_vector(9 downto 0);
368 
    clk         : in std_logic;
369 
    di, tdi     : in std_logic_vector(31 downto 0);
370 
    do          : out std_logic_vector(31 downto 0);
371 
    me, oe, we, tme, twe, awt, biste, toe : in std_logic
372 
  );
373 
end;
374 
architecture behavioral of hdss1_1024x32cm4sw0 is
375 
begin
376 
  syncram0 : atc18_syncram_sim
377 
    generic map ( abits => 10, dbits => 32)
378 
    port map ( addr, clk, di, do, me, oe, we);
379 
end behavioral;
380 
 
381 
library ieee;
382 
use IEEE.std_logic_1164.all;
383 
use work.tech_atc18_sim.all;
384 
entity hdss1_2048x32cm8sw0 is
385 
  port (
386 
    addr, taddr : in std_logic_vector(10 downto 0);
387 
    clk         : in std_logic;
388 
    di, tdi     : in std_logic_vector(31 downto 0);
389 
    do          : out std_logic_vector(31 downto 0);
390 
    me, oe, we, tme, twe, awt, biste, toe : in std_logic
391 
  );
392 
end;
393 
architecture behavioral of hdss1_2048x32cm8sw0 is
394 
begin
395 
  syncram0 : atc18_syncram_sim
396 
    generic map ( abits => 11, dbits => 32)
397 
    port map ( addr, clk, di, do, me, oe, we);
398 
end behavioral;
399 
 
400 
-- 2-port syncronous ram
401 
 
402 
library ieee;
403 
use IEEE.std_logic_1164.all;
404 
use work.tech_atc18_sim.all;
405 
entity rfss2_136x32cm2sw0 is
406 
  port (
407 
    addra, taddra : in std_logic_vector(7 downto 0);
408 
    addrb, taddrb : in std_logic_vector(7 downto 0);
409 
    clka, clkb    : in std_logic;
410 
    dia, tdia     : in std_logic_vector(31 downto 0);
411 
    dob           : out std_logic_vector(31 downto 0);
412 
    mea, wea, tmea, twea, bistea : in std_logic;
413 
    meb, oeb, tmeb,  awtb, bisteb, toeb : in std_logic
414 
  );
415 
end;
416 
architecture behavioral of rfss2_136x32cm2sw0 is
417 
begin
418 
  syncram0 : atc18_2pram_sim
419 
    generic map ( abits => 8, dbits => 32, words => 136)
420 
    port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
421 
end behavioral;
422 
 
423 
library ieee;
424 
use IEEE.std_logic_1164.all;
425 
use work.tech_atc18_sim.all;
426 
entity rfss2_168x32cm2sw0 is
427 
  port (
428 
    addra, taddra : in std_logic_vector(7 downto 0);
429 
    addrb, taddrb : in std_logic_vector(7 downto 0);
430 
    clka, clkb    : in std_logic;
431 
    dia, tdia     : in std_logic_vector(31 downto 0);
432 
    dob           : out std_logic_vector(31 downto 0);
433 
    mea, wea, tmea, twea, bistea : in std_logic;
434 
    meb, oeb, tmeb,  awtb, bisteb, toeb : in std_logic
435 
  );
436 
end;
437 
architecture behavioral of rfss2_168x32cm2sw0 is
438 
begin
439 
  syncram0 : atc18_2pram_sim
440 
    generic map ( abits => 8, dbits => 32, words => 168)
441 
    port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
442 
end behavioral;
443 
 
444 
-- dual-port syncronous ram
445 
 
446 
LIBRARY ieee;
447 
use IEEE.std_logic_1164.all;
448 
use work.tech_atc18_sim.all;
449 
 
450 
entity hdss2_64x32cm4sw0 is
451 
  port (
452 
    addra, taddra : in std_logic_vector(5 downto 0);
453 
    addrb, taddrb : in std_logic_vector(5 downto 0);
454 
    clka, clkb    : in std_logic;
455 
    dia, tdia     : in std_logic_vector(31 downto 0);
456 
    dib, tdib     : in std_logic_vector(31 downto 0);
457 
    doa, dob      : out std_logic_vector(31 downto 0);
458 
    mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
459 
    meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
460 
  );
461 
end;
462 
architecture behavioral of hdss2_64x32cm4sw0 is
463 
begin
464 
  syncram0 : atc18_dpram_sim
465 
    generic map ( abits => 6, dbits => 32)
466 
    port map ( addra, clka, dia, doa, mea, oea, wea,
467 
               addrb, clkb, dib, dob, meb, oeb, web);
468 
end behavioral;
469 
 
470 
library ieee;
471 
use IEEE.std_logic_1164.all;
472 
use work.tech_atc18_sim.all;
473 
entity hdss2_128x32cm4sw0 is
474 
  port (
475 
    addra, taddra : in std_logic_vector(6 downto 0);
476 
    addrb, taddrb : in std_logic_vector(6 downto 0);
477 
    clka, clkb    : in std_logic;
478 
    dia, tdia     : in std_logic_vector(31 downto 0);
479 
    dib, tdib     : in std_logic_vector(31 downto 0);
480 
    doa, dob      : out std_logic_vector(31 downto 0);
481 
    mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
482 
    meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
483 
  );
484 
end;
485 
architecture behavioral of hdss2_128x32cm4sw0 is
486 
begin
487 
  syncram0 : atc18_dpram_sim
488 
    generic map ( abits => 7, dbits => 32)
489 
    port map ( addra, clka, dia, doa, mea, oea, wea,
490 
               addrb, clkb, dib, dob, meb, oeb, web);
491 
end behavioral;
492 
 
493 
library ieee;
494 
use IEEE.std_logic_1164.all;
495 
use work.tech_atc18_sim.all;
496 
entity hdss2_256x32cm4sw0 is
497 
  port (
498 
    addra, taddra : in std_logic_vector(7 downto 0);
499 
    addrb, taddrb : in std_logic_vector(7 downto 0);
500 
    clka, clkb    : in std_logic;
501 
    dia, tdia     : in std_logic_vector(31 downto 0);
502 
    dib, tdib     : in std_logic_vector(31 downto 0);
503 
    doa, dob      : out std_logic_vector(31 downto 0);
504 
    mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
505 
    meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
506 
  );
507 
end;
508 
architecture behavioral of hdss2_256x32cm4sw0 is
509 
begin
510 
  syncram0 : atc18_dpram_sim
511 
    generic map ( abits => 8, dbits => 32)
512 
    port map ( addra, clka, dia, doa, mea, oea, wea,
513 
               addrb, clkb, dib, dob, meb, oeb, web);
514 
end behavioral;
515 
 
516 
library ieee;
517 
use IEEE.std_logic_1164.all;
518 
use work.tech_atc18_sim.all;
519 
entity hdss2_512x32cm4sw0 is
520 
  port (
521 
    addra, taddra : in std_logic_vector(8 downto 0);
522 
    addrb, taddrb : in std_logic_vector(8 downto 0);
523 
    clka, clkb    : in std_logic;
524 
    dia, tdia     : in std_logic_vector(31 downto 0);
525 
    dib, tdib     : in std_logic_vector(31 downto 0);
526 
    doa, dob      : out std_logic_vector(31 downto 0);
527 
    mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
528 
    meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
529 
  );
530 
end;
531 
architecture behavioral of hdss2_512x32cm4sw0 is
532 
begin
533 
  syncram0 : atc18_dpram_sim
534 
    generic map ( abits => 9, dbits => 32)
535 
    port map ( addra, clka, dia, doa, mea, oea, wea,
536 
               addrb, clkb, dib, dob, meb, oeb, web);
537 
end behavioral;
538 
 
539 
-- pragma translate_on
540 
-- component declarations from true tech library
541 
 
542 
LIBRARY ieee;
543 
use IEEE.std_logic_1164.all;
544 
package tech_atc18_syn is
545 
 
546 
  component hdss1_128x32cm4sw0
547 
  port (
548 
    addr, taddr : in std_logic_vector(6 downto 0);
549 
    clk         : in std_logic;
550 
    di, tdi     : in std_logic_vector(31 downto 0);
551 
    do          : out std_logic_vector(31 downto 0);
552 
    me, oe, we, tme, twe, awt, biste, toe : in std_logic
553 
  );
554 
  end component;
555 
 
556 
  component hdss1_256x32cm4sw0
557 
  port (
558 
    addr, taddr : in std_logic_vector(7 downto 0);
559 
    clk         : in std_logic;
560 
    di, tdi     : in std_logic_vector(31 downto 0);
561 
    do          : out std_logic_vector(31 downto 0);
562 
    me, oe, we, tme, twe, awt, biste, toe : in std_logic
563 
  );
564 
  end component;
565 
 
566 
  component hdss1_512x32cm4sw0
567 
  port (
568 
    addr, taddr : in std_logic_vector(8 downto 0);
569 
    clk         : in std_logic;
570 
    di, tdi     : in std_logic_vector(31 downto 0);
571 
    do          : out std_logic_vector(31 downto 0);
572 
    me, oe, we, tme, twe, awt, biste, toe : in std_logic
573 
  );
574 
  end component;
575 
 
576 
  component hdss1_1024x32cm4sw0
577 
  port (
578 
    addr, taddr : in std_logic_vector(9 downto 0);
579 
    clk         : in std_logic;
580 
    di, tdi     : in std_logic_vector(31 downto 0);
581 
    do          : out std_logic_vector(31 downto 0);
582 
    me, oe, we, tme, twe, awt, biste, toe : in std_logic
583 
  );
584 
  end component;
585 
 
586 
  component hdss1_2048x32cm8sw0
587 
  port (
588 
    addr, taddr : in std_logic_vector(10 downto 0);
589 
    clk         : in std_logic;
590 
    di, tdi     : in std_logic_vector(31 downto 0);
591 
    do          : out std_logic_vector(31 downto 0);
592 
    me, oe, we, tme, twe, awt, biste, toe : in std_logic
593 
  );
594 
  end component;
595 
 
596 
  component rfss2_136x32cm2sw0
597 
  port (
598 
    addra, taddra : in std_logic_vector(7 downto 0);
599 
    addrb, taddrb : in std_logic_vector(7 downto 0);
600 
    clka, clkb    : in std_logic;
601 
    dia, tdia     : in std_logic_vector(31 downto 0);
602 
    dob      : out std_logic_vector(31 downto 0);
603 
    mea, wea, tmea, twea, bistea : in std_logic;
604 
    meb, oeb, tmeb,  awtb, bisteb, toeb : in std_logic
605 
  );
606 
  end component;
607 
 
608 
  component rfss2_168x32cm2sw0
609 
  port (
610 
    addra, taddra : in std_logic_vector(7 downto 0);
611 
    addrb, taddrb : in std_logic_vector(7 downto 0);
612 
    clka, clkb    : in std_logic;
613 
    dia, tdia     : in std_logic_vector(31 downto 0);
614 
    dob      : out std_logic_vector(31 downto 0);
615 
    mea, wea, tmea, twea, bistea : in std_logic;
616 
    meb, oeb, tmeb,  awtb, bisteb, toeb : in std_logic
617 
  );
618 
  end component;
619 
 
620 
  component hdss2_64x32cm4sw0
621 
  port (
622 
    addra, taddra : in std_logic_vector(5 downto 0);
623 
    addrb, taddrb : in std_logic_vector(5 downto 0);
624 
    clka, clkb    : in std_logic;
625 
    dia, tdia     : in std_logic_vector(31 downto 0);
626 
    dib, tdib     : in std_logic_vector(31 downto 0);
627 
    doa, dob      : out std_logic_vector(31 downto 0);
628 
    mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
629 
    meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
630 
  );
631 
  end component;
632 
 
633 
  component hdss2_128x32cm4sw0
634 
  port (
635 
    addra, taddra : in std_logic_vector(6 downto 0);
636 
    addrb, taddrb : in std_logic_vector(6 downto 0);
637 
    clka, clkb    : in std_logic;
638 
    dia, tdia     : in std_logic_vector(31 downto 0);
639 
    dib, tdib     : in std_logic_vector(31 downto 0);
640 
    doa, dob      : out std_logic_vector(31 downto 0);
641 
    mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
642 
    meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
643 
  );
644 
  end component;
645 
 
646 
  component hdss2_256x32cm4sw0
647 
  port (
648 
    addra, taddra : in std_logic_vector(7 downto 0);
649 
    addrb, taddrb : in std_logic_vector(7 downto 0);
650 
    clka, clkb    : in std_logic;
651 
    dia, tdia     : in std_logic_vector(31 downto 0);
652 
    dib, tdib     : in std_logic_vector(31 downto 0);
653 
    doa, dob      : out std_logic_vector(31 downto 0);
654 
    mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
655 
    meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
656 
  );
657 
  end component;
658 
 
659 
  component hdss2_512x32cm4sw0
660 
  port (
661 
    addra, taddra : in std_logic_vector(8 downto 0);
662 
    addrb, taddrb : in std_logic_vector(8 downto 0);
663 
    clka, clkb    : in std_logic;
664 
    dia, tdia     : in std_logic_vector(31 downto 0);
665 
    dib, tdib     : in std_logic_vector(31 downto 0);
666 
    doa, dob      : out std_logic_vector(31 downto 0);
667 
    mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
668 
    meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
669 
  );
670 
  end component;
671 
 
672 
  -- input pad
673 
  component pc33d00 port (pad : in std_logic; cin : out std_logic); end component;
674 
  -- schmitt input pad
675 
  component pc33d20 port (pad : in std_logic; cin : out std_logic); end component;
676 
end;
677 
------------------------------------------------------------------
678 
-- sync ram generator --------------------------------------------
679 
------------------------------------------------------------------
680 
 
681 
library IEEE;
682 
use IEEE.std_logic_1164.all;
683 
use work.tech_atc18_syn.all;
684 
use work.leon_iface.all;
685 
 
686 
 
687 
entity atc18_syncram is
688 
  generic ( abits : integer := 10; dbits : integer := 8 );
689 
  port (
690 
    address  : in std_logic_vector(abits -1 downto 0);
691 
    clk      : in clk_type;
692 
    datain   : in std_logic_vector(dbits -1 downto 0);
693 
    dataout  : out std_logic_vector(dbits -1 downto 0);
694 
    enable   : in std_logic;
695 
    write    : in std_logic
696 
  );
697 
end;
698 
 
699 
architecture rtl of atc18_syncram is
700 
  signal d, q, gnd : std_logic_vector(35 downto 0);
701 
  signal a : std_logic_vector(17 downto 0);
702 
  signal vcc : std_logic;
703 
  constant synopsys_bug : std_logic_vector(37 downto 0) := (others => '0');
704 
begin
705 
 
706 
  gnd <= (others => '0'); vcc <= '1';
707 
  a(abits -1 downto 0) <= address;
708 
  d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
709 
  a(17 downto abits) <= synopsys_bug(17 downto abits);
710 
  d(35 downto dbits) <= synopsys_bug(35 downto dbits);
711 
  dataout <= q(dbits -1 downto 0);
712 
  q(35 downto dbits) <= synopsys_bug(35 downto dbits);
713 
 
714 
  a7d32 : if (abits <= 7) and (dbits <= 32) generate
715 
    id0 : hdss1_128x32cm4sw0
716 
      port map (a(6 downto 0), gnd(6 downto 0), clk  ,
717 
        d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
718 
        enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
719 
  end generate;
720 
 
721 
  a8d32 : if (abits = 8) and (dbits <= 32) generate
722 
    id0 : hdss1_256x32cm4sw0
723 
      port map (a(7 downto 0), gnd(7 downto 0), clk  ,
724 
        d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
725 
        enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
726 
  end generate;
727 
 
728 
  a9d32 : if (abits = 9) and (dbits <= 32) generate
729 
    id0 : hdss1_512x32cm4sw0
730 
      port map (address(8 downto 0), gnd(8 downto 0), clk ,
731 
        d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
732 
        enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
733 
 
734 
  end generate;
735 
  a10d32 : if (abits = 10) and (dbits <= 32) generate
736 
    id0 : hdss1_1024x32cm4sw0
737 
      port map (address(9 downto 0), gnd(9 downto 0), clk ,
738 
        d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
739 
        enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
740 
  end generate;
741 
 
742 
  a11d32 : if (abits = 11) and (dbits <= 32) generate
743 
    id0 : hdss1_2048x32cm8sw0
744 
      port map (address(10 downto 0), gnd(10 downto 0), clk ,
745 
        d(31 downto 0), gnd(31 downto 0), q(31 downto 0),
746 
        enable, vcc, write, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
747 
  end generate;
748 
 
749 
end rtl;
750 
 
751 
------------------------------------------------------------------
752 
-- sync dpram generator --------------------------------------------
753 
------------------------------------------------------------------
754 
 
755 
library IEEE;
756 
use IEEE.std_logic_1164.all;
757 
use work.tech_atc18_syn.all;
758 
use work.leon_iface.all;
759 
 
760 
 
761 
entity atc18_dpram is
762 
  generic ( abits : integer := 10; dbits : integer := 8 );
763 
  port (
764 
    address1 : in std_logic_vector((abits -1) downto 0);
765 
    clk      : in clk_type;
766 
    datain1  : in std_logic_vector((dbits -1) downto 0);
767 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
768 
    enable1  : in std_logic;
769 
    write1   : in std_logic;
770 
    address2 : in std_logic_vector((abits -1) downto 0);
771 
    datain2  : in std_logic_vector((dbits -1) downto 0);
772 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
773 
    enable2  : in std_logic;
774 
    write2   : in std_logic
775 
   );
776 
end;
777 
architecture rtl of atc18_dpram is
778 
  signal vcc : std_logic;
779 
  signal d1, d2, a1, a2, q1, q2, gnd : std_logic_vector(35 downto 0);
780 
begin
781 
 
782 
  vcc <= '1'; gnd <=  (others => '0');
783 
  d1(dbits-1 downto 0) <= datain1; d1(35 downto dbits) <= (others => '0');
784 
  d2(dbits-1 downto 0) <= datain2; d2(35 downto dbits) <= (others => '0');
785 
  a1(abits-1 downto 0) <= address1; a1(35 downto abits) <= (others => '0');
786 
  a2(abits-1 downto 0) <= address2; a2(35 downto abits) <= (others => '0');
787 
  dataout1 <= q1(dbits-1 downto 0); dataout2 <= q2(dbits-1 downto 0);
788 
 
789 
  a6d32 : if (abits <= 6) and (dbits <= 32) generate
790 
    id0 : hdss2_64x32cm4sw0
791 
      port map (a1(5 downto 0), gnd(5 downto 0), a2(5 downto 0),
792 
        gnd(5 downto 0), clk  , clk  ,
793 
        d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
794 
        q1(31 downto 0), q2(31 downto 0),
795 
        enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
796 
        enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
797 
  end generate;
798 
 
799 
  a7d32 : if (abits = 7) and (dbits <= 32) generate
800 
    id0 : hdss2_128x32cm4sw0
801 
      port map (a1(6 downto 0), gnd(6 downto 0), a2(6 downto 0),
802 
        gnd(6 downto 0), clk  , clk  ,
803 
        d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
804 
        q1(31 downto 0), q2(31 downto 0),
805 
        enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
806 
        enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
807 
  end generate;
808 
 
809 
  a8d32 : if (abits = 8) and (dbits <= 32) generate
810 
    id0 : hdss2_256x32cm4sw0
811 
      port map (a1(7 downto 0), gnd(7 downto 0), a2(7 downto 0),
812 
        gnd(7 downto 0), clk  , clk  ,
813 
        d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
814 
        q1(31 downto 0), q2(31 downto 0),
815 
        enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
816 
        enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
817 
  end generate;
818 
 
819 
  a9d32 : if (abits = 9) and (dbits <= 32) generate
820 
    id0 : hdss2_512x32cm4sw0
821 
      port map (a1(8 downto 0), gnd(8 downto 0), a2(8 downto 0),
822 
        gnd(8 downto 0), clk  , clk  ,
823 
        d1(31 downto 0), gnd(31 downto 0), d2(31 downto 0), gnd(31 downto 0),
824 
        q1(31 downto 0), q2(31 downto 0),
825 
        enable1, vcc, write1, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0),
826 
        enable2, vcc, write2, gnd(0), gnd(0), gnd(0), gnd(0), gnd(0));
827 
  end generate;
828 
 
829 
end;
830 
 
831 
------------------------------------------------------------------
832 
-- regfile generator  --------------------------------------------
833 
------------------------------------------------------------------
834 
 
835 
LIBRARY ieee;
836 
use IEEE.std_logic_1164.all;
837 
use IEEE.std_logic_arith.all;
838 
use work.tech_generic.all;
839 
use work.tech_atc18_syn.all;
840 
use work.leon_iface.all;
841 
use work.leon_config.all;
842 
 
843 
entity atc18_regfile_iu is
844 
  generic (
845 
    rftype : integer := 1;
846 
    abits : integer := 8;
847 
    dbits : integer := 32;
848 
    words : integer := 136
849 
  );
850 
  port (
851 
    rst      : in std_logic;
852 
    clk      : in clk_type;
853 
    clkn     : in clk_type;
854 
    rfi      : in rf_in_type;
855 
    rfo      : out rf_out_type);
856 
end;
857 
 
858 
architecture rtl of atc18_regfile_iu is
859 
signal din1, din2, qq1, qq2, gnd : std_logic_vector(39 downto 0);
860 
signal vcc : std_logic;
861 
signal ra1, ra2, wa : std_logic_vector(14 downto 0);
862 
begin
863 
 
864 
  vcc <= '1'; gnd <= (others => '0');
865 
  ra1(abits-1 downto 0) <= rfi.rd1addr;
866 
  ra2(abits-1 downto 0) <= rfi.rd2addr;
867 
  wa(abits-1 downto 0) <= rfi.wraddr;
868 
  din1(dbits-1 downto 0) <= rfi.wrdata;
869 
  din2(dbits-1 downto 0) <= rfi.wrdata;
870 
  wa(14 downto abits)   <= gnd(14 downto abits);
871 
  ra1(14 downto abits)  <= gnd(14 downto abits);
872 
  ra2(14 downto abits)  <= gnd(14 downto abits);
873 
  din1(39 downto dbits) <= (others => '0');
874 
  din2(39 downto dbits) <= (others => '0');
875 
 
876 
  rf136x32 : if (words <= 136) and (dbits = 32) generate
877 
    id0 : rfss2_136x32cm2sw0 port map (
878 
      wa(7 downto 0), gnd(7 downto 0), ra1(7 downto 0), gnd(7 downto 0),
879 
      clk , clkn , din1(31 downto 0), gnd(31 downto 0), qq1(31 downto 0), vcc,
880 
      rfi.wren, gnd(0), gnd(0), gnd(0), vcc, vcc, gnd(0), gnd(0),gnd(0), gnd(0));
881 
    id1 : rfss2_136x32cm2sw0 port map (
882 
      wa(7 downto 0), gnd(7 downto 0), ra2(7 downto 0), gnd(7 downto 0),
883 
      clk , clkn , din2(31 downto 0), gnd(31 downto 0), qq2(31 downto 0), vcc,
884 
      rfi.wren, gnd(0), gnd(0), gnd(0), vcc, vcc, gnd(0), gnd(0),gnd(0), gnd(0));
885 
  end generate;
886 
 
887 
  rf168x32 : if (words <= 168) and (words > 136) and (dbits = 32) generate
888 
    id0 : rfss2_168x32cm2sw0 port map (
889 
      wa(7 downto 0), gnd(7 downto 0), ra1(7 downto 0), gnd(7 downto 0),
890 
      clk , clkn , din1(31 downto 0), gnd(31 downto 0), qq1(31 downto 0), vcc,
891 
      rfi.wren, gnd(0), gnd(0), gnd(0), vcc, vcc, gnd(0), gnd(0),gnd(0), gnd(0));
892 
    id1 : rfss2_168x32cm2sw0 port map (
893 
      wa(7 downto 0), gnd(7 downto 0), ra2(7 downto 0), gnd(7 downto 0),
894 
      clk , clkn , din2(31 downto 0), gnd(31 downto 0), qq2(31 downto 0), vcc,
895 
      rfi.wren, gnd(0), gnd(0), gnd(0), vcc, vcc, gnd(0), gnd(0),gnd(0), gnd(0));
896 
  end generate;
897 
 
898 
 
899 
  rfo.data1(dbits-1 downto 0) <= qq1(dbits-1 downto 0);
900 
  rfo.data2(dbits-1 downto 0) <= qq2(dbits-1 downto 0);
901 
 
902 
end;
903 
 
904 
LIBRARY ieee;
905 
use IEEE.std_logic_1164.all;
906 
use IEEE.std_logic_arith.all;
907 
use work.tech_generic.all;
908 
use work.tech_atc18_syn.all;
909 
use work.leon_iface.all;
910 
 
911 
entity atc18_regfile_cp is
912 
  generic (
913 
    abits : integer := 4;
914 
    dbits : integer := 32;
915 
    words : integer := 16
916 
  );
917 
  port (
918 
    rst      : in std_logic;
919 
    clk      : in clk_type;
920 
    rfi      : in rf_cp_in_type;
921 
    rfo      : out rf_cp_out_type);
922 
end;
923 
 
924 
architecture rtl of atc18_regfile_cp is
925 
signal din1, qq1, qq2 : std_logic_vector(39 downto 0);
926 
signal wa : std_logic_vector(abits-1 downto 0);
927 
signal vcc, gnd, wen : std_logic;
928 
begin
929 
  vcc <= '1'; gnd <= '0';
930 
  rfo.data1(dbits-1 downto 0) <= qq1(dbits-1 downto 0);
931 
  rfo.data2(dbits-1 downto 0) <= qq2(dbits-1 downto 0);
932 
 
933 
end;
934 
 
935 
------------------------------------------------------------------
936 
-- mapping generic pads on tech pads ---------------------------------
937 
------------------------------------------------------------------
938 
 
939 
-- input pad
940 
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc18_syn.all;
941 
entity atc18_inpad is port (pad : in std_logic; q : out std_logic); end;
942 
architecture syn of atc18_inpad is begin
943 
  i0 : pc33d00 port map (pad => pad, cin => q);
944 
end;
945 
 
946 
-- input schmitt pad
947 
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc18_syn.all;
948 
entity atc18_smpad is port (pad : in std_logic; q : out std_logic); end;
949 
architecture syn of atc18_smpad is begin
950 
  i0 : pc33d20 port map (pad => pad, cin => q);
951 
end;

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