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[/] [core_arm/] [trunk/] [vhdl/] [tech/] [tech_atc25.vhd] - Blame information for rev 6

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1 2 tarookumic 
 
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----------------------------------------------------------------------------
6 
--  This file is a part of the LEON VHDL model
7 
--  Copyright (C) 1999  European Space Agency (ESA)
8 
--
9 
--  This library is free software; you can redistribute it and/or
10 
--  modify it under the terms of the GNU Lesser General Public
11 
--  License as published by the Free Software Foundation; either
12 
--  version 2 of the License, or (at your option) any later version.
13 
--
14 
--  See the file COPYING.LGPL for the full details of the license.
15 
 
16 
 
17 
-----------------------------------------------------------------------------
18 
-- Entity:      tech_atc25
19 
-- File:        tech_atc25.vhd
20 
-- Author:      Jiri Gaisler - Gaisler Research
21 
-- Description: Contains Atmel ATC25 specific pads and ram generators
22 
------------------------------------------------------------------------------
23 
 
24 
LIBRARY ieee;
25 
use IEEE.std_logic_1164.all;
26 
use work.leon_iface.all;
27 
package tech_atc25 is
28 
 
29 
-- sync ram generator
30 
 
31 
  component atc25_syncram
32 
  generic ( abits : integer := 10; dbits : integer := 8 );
33 
  port (
34 
    address  : in std_logic_vector(abits -1 downto 0);
35 
    clk      : in clk_type;
36 
    datain   : in std_logic_vector(dbits -1 downto 0);
37 
    dataout  : out std_logic_vector(dbits -1 downto 0);
38 
    enable   : in std_logic;
39 
    write    : in std_logic);
40 
  end component;
41 
 
42 
-- IU regfile generator
43 
 
44 
component atc25_regfile_iu
45 
  generic (rftype : integer := 1; abits : integer := 8; dbits : integer := 32; words : integer := 128);
46 
  port (
47 
    rst      : in std_logic;
48 
    clk      : in clk_type;
49 
    clkn     : in clk_type;
50 
    rfi      : in rf_in_type;
51 
    rfo      : out rf_out_type);
52 
  end component;
53 
 
54 
component atc25_regfile_cp
55 
  generic (
56 
    abits : integer := 4;
57 
    dbits : integer := 32;
58 
    words : integer := 16
59 
  );
60 
  port (
61 
    rst      : in std_logic;
62 
    clk      : in clk_type;
63 
    rfi      : in rf_cp_in_type;
64 
    rfo      : out rf_cp_out_type);
65 
end component;
66 
 
67 
component atc25_dpram
68 
  generic ( abits : integer := 10; dbits : integer := 8 );
69 
  port (
70 
    address1 : in std_logic_vector((abits -1) downto 0);
71 
    clk      : in clk_type;
72 
    datain1  : in std_logic_vector((dbits -1) downto 0);
73 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
74 
    enable1  : in std_logic;
75 
    write1   : in std_logic;
76 
    address2 : in std_logic_vector((abits -1) downto 0);
77 
    datain2  : in std_logic_vector((dbits -1) downto 0);
78 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
79 
    enable2  : in std_logic;
80 
    write2   : in std_logic
81 
   );
82 
end component;
83 
 
84 
-- standard pads
85 
 
86 
  component atc25_inpad
87 
    port (pad : in std_logic; q : out std_logic);
88 
  end component;
89 
  component atc25_smpad
90 
    port (pad : in std_logic; q : out std_logic);
91 
  end component;
92 
  component atc25_outpad
93 
    generic (drive : integer := 1);
94 
    port (d : in  std_logic; pad : out  std_logic);
95 
  end component;
96 
  component atc25_toutpad
97 
    generic (drive : integer := 1);
98 
    port (d, en : in  std_logic; pad : out  std_logic);
99 
  end component;
100 
  component atc25_toutpadu
101 
    generic (drive : integer := 1);
102 
    port (d, en : in  std_logic; pad : out  std_logic);
103 
  end component;
104 
  component atc25_iopad
105 
    generic (drive : integer := 1);
106 
    port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
107 
  end component;
108 
  component atc25_iopadu
109 
    generic (drive : integer := 1);
110 
    port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
111 
  end component;
112 
  component atc25_iodpad
113 
    generic (drive : integer := 1);
114 
    port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
115 
  end component;
116 
  component atc25_odpad
117 
    generic (drive : integer := 1);
118 
    port ( d : in std_logic; pad : out std_logic);
119 
  end component;
120 
 
121 
-- PCI pads
122 
  component atc25_pcioutpad port (d : in  std_logic; pad : out  std_logic); end component;
123 
  component atc25_pcitoutpad port (d, en : in  std_logic; pad : out  std_logic); end component;
124 
  component atc25_pciiopad
125 
    port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
126 
  end component;
127 
  component atc25_pciiodpad
128 
    port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
129 
  end component;
130 
 
131 
end;
132 
 
133 
------------------------------------------------------------------
134 
-- behavioural pad models --------------------------------------------
135 
------------------------------------------------------------------
136 
-- Only needed for simulation, not synthesis.
137 
-- pragma translate_off
138 
 
139 
-- input pad
140 
library IEEE;
141 
use IEEE.std_logic_1164.all;
142 
entity pt33d00 is port (pad : in std_logic; cin : out std_logic); end;
143 
architecture rtl of pt33d00 is begin cin <= to_x01(pad) after 1 ns; end;
144 
 
145 
-- input pad with pull-up
146 
library IEEE;
147 
use IEEE.std_logic_1164.all;
148 
entity pt33d00u is port (pad : inout std_logic; cin : out std_logic); end;
149 
architecture rtl of pt33d00u is
150 
begin cin <= to_x01(pad) after 1 ns; pad <= 'H'; end;
151 
 
152 
-- input schmitt pad
153 
library IEEE;
154 
use IEEE.std_logic_1164.all;
155 
entity pt33d20 is port (pad : in std_logic; cin : out std_logic); end;
156 
architecture rtl of pt33d20 is begin cin <= to_x01(pad) after 1 ns; end;
157 
 
158 
-- input schmitt pad with pull-up
159 
library IEEE;
160 
use IEEE.std_logic_1164.all;
161 
entity pt33d20u is port (pad : inout std_logic; cin : out std_logic); end;
162 
architecture rtl of pt33d20u is
163 
begin cin <= to_x01(pad) after 1 ns; pad <= 'H'; end;
164 
 
165 
-- output pads
166 
library IEEE; use IEEE.std_logic_1164.all;
167 
entity pt33o01 is port (i : in  std_logic; pad : out  std_logic); end;
168 
architecture rtl of pt33o01 is begin pad <= to_x01(i) after 2 ns; end;
169 
library IEEE; use IEEE.std_logic_1164.all;
170 
entity pt33o02 is port (i : in  std_logic; pad : out  std_logic); end;
171 
architecture rtl of pt33o02 is begin pad <= to_x01(i) after 2 ns; end;
172 
library IEEE; use IEEE.std_logic_1164.all;
173 
entity pt33o03 is port (i : in  std_logic; pad : out  std_logic); end;
174 
architecture rtl of pt33o03 is begin pad <= to_x01(i) after 2 ns; end;
175 
library IEEE; use IEEE.std_logic_1164.all;
176 
entity pt33o04 is port (i : in  std_logic; pad : out  std_logic); end;
177 
architecture rtl of pt33o04 is begin pad <= to_x01(i) after 2 ns; end;
178 
 
179 
-- output tri-state pads with pull-up
180 
library IEEE; use IEEE.std_logic_1164.all;
181 
entity pt33t01u is port (i, oen : in  std_logic; pad : out  std_logic); end;
182 
architecture rtl of pt33t01u is
183 
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
184 
library IEEE; use IEEE.std_logic_1164.all;
185 
entity pt33t02u is port (i, oen : in  std_logic; pad : out  std_logic); end;
186 
architecture rtl of pt33t02u is
187 
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
188 
library IEEE; use IEEE.std_logic_1164.all;
189 
entity pt33t03u is port (i, oen : in  std_logic; pad : out  std_logic); end;
190 
architecture rtl of pt33t03u is
191 
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns; end;
192 
 
193 
-- bidirectional pad
194 
library IEEE; use IEEE.std_logic_1164.all;
195 
entity pt33b01 is
196 
  port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
197 
end;
198 
architecture rtl of pt33b01 is
199 
begin
200 
  pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
201 
  cin <= to_x01(pad) after 1 ns;
202 
end;
203 
library IEEE;
204 
use IEEE.std_logic_1164.all;
205 
entity pt33b02 is
206 
  port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
207 
end;
208 
architecture rtl of pt33b02 is
209 
begin
210 
  pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
211 
  cin <= to_x01(pad) after 1 ns;
212 
end;
213 
library IEEE;
214 
use IEEE.std_logic_1164.all;
215 
entity pt33b03 is
216 
  port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
217 
end;
218 
architecture rtl of pt33b03 is
219 
begin
220 
  pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
221 
  cin <= to_x01(pad) after 1 ns;
222 
end;
223 
library IEEE;
224 
use IEEE.std_logic_1164.all;
225 
entity pt33b04 is
226 
  port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
227 
end;
228 
architecture rtl of pt33b04 is
229 
begin
230 
  pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
231 
  cin <= to_x01(pad) after 1 ns;
232 
end;
233 
 
234 
-- bidirectional pads with pull-up
235 
library IEEE;
236 
use IEEE.std_logic_1164.all;
237 
entity pt33b01u is
238 
  port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
239 
end;
240 
architecture rtl of pt33b01u is
241 
begin
242 
  pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
243 
  cin <= to_x01(pad) after 1 ns;
244 
end;
245 
library IEEE;
246 
use IEEE.std_logic_1164.all;
247 
entity pt33b02u is
248 
  port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
249 
end;
250 
architecture rtl of pt33b02u is
251 
begin
252 
  pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
253 
  cin <= to_x01(pad) after 1 ns;
254 
end;
255 
library IEEE;
256 
use IEEE.std_logic_1164.all;
257 
entity pt33b03u is
258 
  port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
259 
end;
260 
architecture rtl of pt33b03u is
261 
begin
262 
  pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
263 
  cin <= to_x01(pad) after 1 ns;
264 
end;
265 
library IEEE;
266 
use IEEE.std_logic_1164.all;
267 
entity pt33b04u is
268 
  port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
269 
end;
270 
architecture rtl of pt33b04u is
271 
begin
272 
  pad <= to_x01(i) after 2 ns when oen = '0' else 'H' after 2 ns;
273 
  cin <= to_x01(pad) after 1 ns;
274 
end;
275 
 
276 
-- PCI output pad
277 
library IEEE; use IEEE.std_logic_1164.all;
278 
entity pp33o01 is port (i : in  std_logic; pad : out  std_logic); end;
279 
architecture rtl of pp33o01 is begin pad <= to_x01(i) after 2 ns; end;
280 
-- PCI bidirectional pad
281 
library IEEE; use IEEE.std_logic_1164.all;
282 
entity pp33b015vt is
283 
  port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
284 
end;
285 
architecture rtl of pp33b015vt is
286 
begin
287 
  pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
288 
  cin <= to_x01(pad) after 1 ns;
289 
end;
290 
-- PCI output tri-state pad
291 
library IEEE; use IEEE.std_logic_1164.all;
292 
entity pp33t015vt is port (i, oen : in  std_logic; pad : out  std_logic); end;
293 
architecture rtl of pp33t015vt is
294 
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns; end;
295 
------------------------------------------------------------------
296 
-- behavioural ram models ----------------------------------------
297 
------------------------------------------------------------------
298 
 
299 
-- clocked address + control, unlatched data
300 
 
301 
library ieee;
302 
use ieee.std_logic_1164.all;
303 
use ieee.std_logic_arith.all;
304 
 
305 
entity atc25_syncram_sim is
306 
  generic (
307 
    abits : integer := 10;
308 
    dbits : integer := 8
309 
  );
310 
  port (
311 
    a     : in std_logic_vector((abits -1) downto 0);
312 
    ce    : in std_logic;
313 
    i     : in std_logic_vector((dbits -1) downto 0);
314 
    o     : out std_logic_vector((dbits -1) downto 0);
315 
    csb   : in std_logic;
316 
    web   : in std_logic;
317 
    oeb   : in std_logic
318 
  );
319 
end;
320 
 
321 
architecture behavioral of atc25_syncram_sim is
322 
  subtype word is std_logic_vector((dbits -1) downto 0);
323 
  type mem is array(0 to (2**abits -1)) of word;
324 
begin
325 
  main : process(ce)
326 
  variable memarr : mem;
327 
  begin
328 
    if rising_edge(ce) and (csb = '0') and not is_x(a) then
329 
      if oeb = '0' then o <= memarr(conv_integer(unsigned(a)));
330 
      else o <= (others => 'Z'); end if;
331 
      if (web = '0') then memarr(conv_integer(unsigned(a))) := i; end if;
332 
    end if;
333 
  end process;
334 
end behavioral;
335 
 
336 
--  Asynchronous 2-port ram
337 
 
338 
LIBRARY ieee;
339 
use IEEE.std_logic_1164.all;
340 
use IEEE.std_logic_arith.all;
341 
 
342 
entity atc25_2pram is
343 
  generic (
344 
    abits : integer := 8;
345 
    dbits : integer := 32;
346 
    words : integer := 256
347 
  );
348 
  port (
349 
    ra  : in std_logic_vector (abits -1 downto 0);
350 
    wa  : in std_logic_vector (abits -1 downto 0);
351 
    di  : in std_logic_vector (dbits -1 downto 0);
352 
    do  : out std_logic_vector (dbits -1 downto 0);
353 
    re  : in std_logic;
354 
    oe  : in std_logic;
355 
    we  : in std_logic
356 
  );
357 
end;
358 
 
359 
architecture behav of atc25_2pram is
360 
signal d1  : std_logic_vector (dbits -1 downto 0);
361 
signal ra1, wa1  : std_logic_vector (abits -1 downto 0);
362 
begin
363 
  d1 <= di after 1 ns; ra1 <= ra after 1 ns; wa1 <= wa after 1 ns;
364 
  rp : process(wa1, ra1, d1, re, oe, we)
365 
  subtype dword is std_logic_vector(dbits -1 downto 0);
366 
  type dregtype is array (0 to words - 1) of DWord;
367 
  variable rfd : dregtype;
368 
  begin
369 
    if is_x(we) or ((we = '0') and is_x(wa1)) then
370 
      for i in 0 to words -1 loop rfd(i) := (others => 'X'); end loop;
371 
    elsif (we = '0') then
372 
      rfd(conv_integer(unsigned(wa1)) mod words) := d1;
373 
    end if;
374 
    if (oe or re) = '0' then
375 
      if not is_x (ra1) then
376 
        do <= rfd(conv_integer(unsigned(ra1)) mod words);
377 
      else do <= (others => 'X'); end if;
378 
    else do <= (others => 'Z'); end if;
379 
  end process;
380 
end;
381 
 
382 
--  Asynchronous dual-port ram
383 
 
384 
LIBRARY ieee;
385 
use IEEE.std_logic_1164.all;
386 
use IEEE.std_logic_arith.all;
387 
 
388 
entity atc25_dpram_sim is
389 
  generic (
390 
    abits : integer := 8;
391 
    dbits : integer := 32;
392 
    words : integer := 256
393 
  );
394 
  port (
395 
    a1   : in std_logic_vector (abits -1 downto 0);
396 
    a2   : in std_logic_vector (abits -1 downto 0);
397 
    di1  : in std_logic_vector (dbits -1 downto 0);
398 
    di2  : in std_logic_vector (dbits -1 downto 0);
399 
    do1  : out std_logic_vector (dbits -1 downto 0);
400 
    do2  : out std_logic_vector (dbits -1 downto 0);
401 
    re1  : in std_logic;
402 
    re2  : in std_logic;
403 
    oe1  : in std_logic;
404 
    oe2  : in std_logic;
405 
    we1  : in std_logic;
406 
    we2  : in std_logic
407 
  );
408 
end;
409 
 
410 
architecture behav of atc25_dpram_sim is
411 
signal d1, d2  : std_logic_vector (dbits -1 downto 0);
412 
signal aa1, aa2  : std_logic_vector (abits -1 downto 0);
413 
signal w1, w2, o1, o2  : std_logic;
414 
begin
415 
  d1 <= di1 after 1 ns; d2 <= di2 after 1 ns;
416 
  aa1 <= a1 after 1 ns; aa2 <= a2 after 1 ns;
417 
  w1 <= re1 or we1; w2 <= re2 or we2;
418 
  o1 <= oe1 and we1 and not re1; o2 <= oe2 and we2 and not re2;
419 
  rp : process(w1, w2, aa1, aa2, d1, d2, o1, o2)
420 
  subtype dword is std_logic_vector(dbits -1 downto 0);
421 
  type dregtype is array (0 to words - 1) of DWord;
422 
  variable rfd : dregtype;
423 
  begin
424 
    if w1 = '0' then
425 
      rfd(conv_integer(unsigned(aa1)) mod words) := d1;
426 
    end if;
427 
    if w2 = '0' then
428 
      rfd(conv_integer(unsigned(aa2)) mod words) := d2;
429 
    end if;
430 
    if o1 = '1' then
431 
      if not (is_x (aa1) or ((aa1 = aa2) and (w1 = '0'))) then -- no write-through !
432 
        do1 <= rfd(conv_integer(unsigned(aa1)) mod words);
433 
      else do1 <= (others => 'X'); end if;
434 
    else do1 <= (others => 'Z'); end if;
435 
    if o2 = '1' then
436 
      if not (is_x (aa2) or ((aa2 = aa1) and (w2 = '0'))) then -- no write-through !
437 
        do2 <= rfd(conv_integer(unsigned(aa2)) mod words);
438 
      else do2 <= (others => 'X'); end if;
439 
    else do2 <= (others => 'Z'); end if;
440 
  end process;
441 
end;
442 
 
443 
-- package with common ram simulation models
444 
LIBRARY ieee;
445 
use IEEE.std_logic_1164.all;
446 
use work.leon_iface.all;
447 
package tech_atc25_sim is
448 
-- clocked address + enable, unlatched data and write
449 
component atc25_syncram_sim
450 
  generic ( abits : integer := 10; dbits : integer := 8 );
451 
  port (
452 
    a     : in std_logic_vector((abits -1) downto 0);
453 
    ce    : in std_logic;
454 
    i     : in std_logic_vector((dbits -1) downto 0);
455 
    o     : out std_logic_vector((dbits -1) downto 0);
456 
    csb   : in std_logic;
457 
    web   : in std_logic;
458 
    oeb   : in std_logic
459 
   );
460 
end component;
461 
 
462 
--  asynchronous 2-port ram
463 
component atc25_2pram
464 
  generic (
465 
    abits : integer := 8;
466 
    dbits : integer := 32;
467 
    words : integer := 256
468 
  );
469 
  port (
470 
    ra  : in std_logic_vector (abits -1 downto 0);
471 
    wa  : in std_logic_vector (abits -1 downto 0);
472 
    di  : in std_logic_vector (dbits -1 downto 0);
473 
    do  : out std_logic_vector (dbits -1 downto 0);
474 
    re  : in std_logic;
475 
    oe  : in std_logic;
476 
    we  : in std_logic
477 
  );
478 
end component;
479 
 
480 
component atc25_dpram_sim
481 
  generic (
482 
    abits : integer := 8;
483 
    dbits : integer := 32;
484 
    words : integer := 256
485 
  );
486 
  port (
487 
    a1   : in std_logic_vector (abits -1 downto 0);
488 
    a2   : in std_logic_vector (abits -1 downto 0);
489 
    di1  : in std_logic_vector (dbits -1 downto 0);
490 
    di2  : in std_logic_vector (dbits -1 downto 0);
491 
    do1  : out std_logic_vector (dbits -1 downto 0);
492 
    do2  : out std_logic_vector (dbits -1 downto 0);
493 
    re1  : in std_logic;
494 
    re2  : in std_logic;
495 
    oe1  : in std_logic;
496 
    oe2  : in std_logic;
497 
    we1  : in std_logic;
498 
    we2  : in std_logic
499 
  );
500 
end component;
501 
 
502 
end;
503 
 
504 
-- Address, control and data signals latched on rising ME.
505 
-- Write enable (WEN) active low.
506 
 
507 
library ieee;
508 
use IEEE.std_logic_1164.all;
509 
use work.tech_atc25_sim.all;
510 
entity RAM_256x26 is
511 
  port (
512 
    a     : in std_logic_vector(7 downto 0);
513 
    i     : in std_logic_vector(25 downto 0);
514 
    o     : out std_logic_vector(25 downto 0);
515 
    ce, csb, oeb, web : in std_logic
516 
  );
517 
end;
518 
architecture behavioral of RAM_256x26 is
519 
begin
520 
  syncram0 : atc25_syncram_sim
521 
    generic map ( abits => 8, dbits => 26)
522 
    port map ( a, ce, i, o, csb, web, oeb);
523 
end behavioral;
524 
 
525 
library ieee;
526 
use IEEE.std_logic_1164.all;
527 
use work.tech_atc25_sim.all;
528 
entity RAM_256x28 is
529 
  port (
530 
    a     : in std_logic_vector(7 downto 0);
531 
    i     : in std_logic_vector(27 downto 0);
532 
    o     : out std_logic_vector(27 downto 0);
533 
    ce, csb, oeb, web : in std_logic
534 
  );
535 
end;
536 
architecture behavioral of RAM_256x28 is
537 
begin
538 
  syncram0 : atc25_syncram_sim
539 
    generic map ( abits => 8, dbits => 28)
540 
    port map ( a, ce, i, o, csb, web, oeb);
541 
end behavioral;
542 
 
543 
library ieee;
544 
use IEEE.std_logic_1164.all;
545 
use work.tech_atc25_sim.all;
546 
entity RAM_256x30 is
547 
  port (
548 
    a     : in std_logic_vector(7 downto 0);
549 
    i     : in std_logic_vector(29 downto 0);
550 
    o     : out std_logic_vector(29 downto 0);
551 
    ce, csb, oeb, web : in std_logic
552 
  );
553 
end;
554 
architecture behavioral of RAM_256x30 is
555 
begin
556 
  syncram0 : atc25_syncram_sim
557 
    generic map ( abits => 8, dbits => 30)
558 
    port map ( a, ce, i, o, csb, web, oeb);
559 
end behavioral;
560 
 
561 
library ieee;
562 
use IEEE.std_logic_1164.all;
563 
use work.tech_atc25_sim.all;
564 
entity RAM_512x28 is
565 
  port (
566 
    a     : in std_logic_vector(8 downto 0);
567 
    i     : in std_logic_vector(27 downto 0);
568 
    o     : out std_logic_vector(27 downto 0);
569 
    ce, csb, oeb, web : in std_logic
570 
  );
571 
end;
572 
architecture behavioral of RAM_512x28 is
573 
begin
574 
  syncram0 : atc25_syncram_sim
575 
    generic map ( abits => 9, dbits => 28)
576 
    port map ( a, ce, i, o, csb, web, oeb);
577 
end behavioral;
578 
 
579 
library ieee;
580 
use IEEE.std_logic_1164.all;
581 
use work.tech_atc25_sim.all;
582 
entity RAM_512x30 is
583 
  port (
584 
    a     : in std_logic_vector(8 downto 0);
585 
    i     : in std_logic_vector(29 downto 0);
586 
    o     : out std_logic_vector(29 downto 0);
587 
    ce, csb, oeb, web : in std_logic
588 
  );
589 
end;
590 
architecture behavioral of RAM_512x30 is
591 
begin
592 
  syncram0 : atc25_syncram_sim
593 
    generic map ( abits => 9, dbits => 30)
594 
    port map ( a, ce, i, o, csb, web, oeb);
595 
end behavioral;
596 
 
597 
library ieee;
598 
use IEEE.std_logic_1164.all;
599 
use work.tech_atc25_sim.all;
600 
entity RAM_512x32 is
601 
  port (
602 
    a     : in std_logic_vector(8 downto 0);
603 
    i     : in std_logic_vector(31 downto 0);
604 
    o     : out std_logic_vector(31 downto 0);
605 
    ce, csb, oeb, web : in std_logic
606 
  );
607 
end;
608 
architecture behavioral of RAM_512x32 is
609 
begin
610 
  syncram0 : atc25_syncram_sim
611 
    generic map ( abits => 9, dbits => 32)
612 
    port map ( a, ce, i, o, csb, web, oeb);
613 
end behavioral;
614 
 
615 
library ieee;
616 
use IEEE.std_logic_1164.all;
617 
use work.tech_atc25_sim.all;
618 
entity RAM_1024x32 is
619 
  port (
620 
    a     : in std_logic_vector(9 downto 0);
621 
    i     : in std_logic_vector(31 downto 0);
622 
    o     : out std_logic_vector(31 downto 0);
623 
    ce, csb, oeb, web : in std_logic
624 
  );
625 
end;
626 
 
627 
architecture behavioral of RAM_1024x32 is
628 
begin
629 
  syncram0 : atc25_syncram_sim
630 
    generic map ( abits => 10, dbits => 32)
631 
    port map ( a, ce, i, o, csb, web, oeb);
632 
end behavioral;
633 
 
634 
library ieee;
635 
use IEEE.std_logic_1164.all;
636 
use work.tech_atc25_sim.all;
637 
entity RAM_2048x32 is
638 
  port (
639 
    a     : in std_logic_vector(10 downto 0);
640 
    i     : in std_logic_vector(31 downto 0);
641 
    o     : out std_logic_vector(31 downto 0);
642 
    ce, csb, oeb, web : in std_logic
643 
  );
644 
end;
645 
architecture behavioral of RAM_2048x32 is
646 
begin
647 
  syncram0 : atc25_syncram_sim
648 
    generic map ( abits => 11, dbits => 32)
649 
    port map ( a, ce, i, o, csb, web, oeb);
650 
end behavioral;
651 
 
652 
LIBRARY ieee;
653 
use IEEE.std_logic_1164.all;
654 
use work.tech_atc25_sim.all;
655 
entity RAM2P_16X32 is
656 
 port (
657 
    RA, WA  : in  std_logic_vector(3 downto 0);
658 
    DI      : in  std_logic_vector(31 downto 0);
659 
    DO      : out std_logic_vector(31 downto 0);
660 
    REB, OEB, WEB : in std_logic );
661 
end;
662 
architecture behav of RAM2P_16X32 is
663 
begin
664 
    dp0 : atc25_2pram
665 
          generic map (abits => 4, dbits => 32, words => 16)
666 
          port map (ra, wa, di, do, reb, oeb, web);
667 
end;
668 
 
669 
LIBRARY ieee;
670 
use IEEE.std_logic_1164.all;
671 
use work.tech_atc25_sim.all;
672 
entity RAM2P_136X32 is
673 
 port (
674 
    RA, WA  : in  std_logic_vector(7 downto 0);
675 
    DI      : in  std_logic_vector(31 downto 0);
676 
    DO      : out std_logic_vector(31 downto 0);
677 
    REB, OEB, WEB : in std_logic );
678 
end;
679 
architecture behav of RAM2P_136X32 is
680 
begin
681 
    dp0 : atc25_2pram
682 
          generic map (abits => 8, dbits => 32, words => 136)
683 
          port map (ra, wa, di, do, reb, oeb, web);
684 
end;
685 
 
686 
LIBRARY ieee;
687 
use IEEE.std_logic_1164.all;
688 
use work.tech_atc25_sim.all;
689 
entity RAM2P_168X32 is
690 
 port (
691 
    RA, WA  : in  std_logic_vector(7 downto 0);
692 
    DI      : in  std_logic_vector(31 downto 0);
693 
    DO      : out std_logic_vector(31 downto 0);
694 
    REB, OEB, WEB : in std_logic );
695 
end;
696 
architecture behav of RAM2P_168X32 is
697 
begin
698 
    dp0 : atc25_2pram
699 
          generic map (abits => 8, dbits => 32, words => 168)
700 
          port map (ra, wa, di, do, reb, oeb, web);
701 
end;
702 
 
703 
LIBRARY ieee;
704 
use IEEE.std_logic_1164.all;
705 
use work.tech_atc25_sim.all;
706 
entity DPRAM_256x26 is
707 
  port (A1     : IN std_logic_vector(7 DOWNTO 0);
708 
        A2     : IN std_logic_vector(7 DOWNTO 0);
709 
        CSB1   : IN std_logic;
710 
        CSB2   : IN std_logic;
711 
        WEB1   : IN std_logic;
712 
        WEB2   : IN std_logic;
713 
        OE1    : IN std_logic;
714 
        OE2    : IN std_logic;
715 
        I1     : IN std_logic_vector(25 downto 0);
716 
        I2     : IN std_logic_vector(25 downto 0);
717 
        O1     : OUT std_logic_vector(25 downto 0);
718 
        O2     : OUT std_logic_vector(25 downto 0));
719 
end;
720 
architecture behav of DPRAM_256x26 is
721 
begin
722 
    dp0 : atc25_dpram_sim
723 
          generic map (abits => 8, dbits => 26, words => 256)
724 
          port map (a1, a2, i1, i2, o1, o2, csb1, csb2, oe1, oe2, web1, web2);
725 
end;
726 
 
727 
LIBRARY ieee;
728 
use IEEE.std_logic_1164.all;
729 
use work.tech_atc25_sim.all;
730 
entity DPRAM_256x28 is
731 
  port (A1     : IN std_logic_vector(7 DOWNTO 0);
732 
        A2     : IN std_logic_vector(7 DOWNTO 0);
733 
        CSB1   : IN std_logic;
734 
        CSB2   : IN std_logic;
735 
        WEB1   : IN std_logic;
736 
        WEB2   : IN std_logic;
737 
        OE1    : IN std_logic;
738 
        OE2    : IN std_logic;
739 
        I1     : IN std_logic_vector(27 downto 0);
740 
        I2     : IN std_logic_vector(27 downto 0);
741 
        O1     : OUT std_logic_vector(27 downto 0);
742 
        O2     : OUT std_logic_vector(27 downto 0));
743 
end;
744 
architecture behav of DPRAM_256x28 is
745 
begin
746 
    dp0 : atc25_dpram_sim
747 
          generic map (abits => 8, dbits => 28, words => 256)
748 
          port map (a1, a2, i1, i2, o1, o2, csb1, csb2, oe1, oe2, web1, web2);
749 
end;
750 
 
751 
LIBRARY ieee;
752 
use IEEE.std_logic_1164.all;
753 
use work.tech_atc25_sim.all;
754 
entity DPRAM_256x30 is
755 
  port (A1     : IN std_logic_vector(7 DOWNTO 0);
756 
        A2     : IN std_logic_vector(7 DOWNTO 0);
757 
        CSB1   : IN std_logic;
758 
        CSB2   : IN std_logic;
759 
        WEB1   : IN std_logic;
760 
        WEB2   : IN std_logic;
761 
        OE1    : IN std_logic;
762 
        OE2    : IN std_logic;
763 
        I1     : IN std_logic_vector(29 downto 0);
764 
        I2     : IN std_logic_vector(29 downto 0);
765 
        O1     : OUT std_logic_vector(29 downto 0);
766 
        O2     : OUT std_logic_vector(29 downto 0));
767 
end;
768 
architecture behav of DPRAM_256x30 is
769 
begin
770 
    dp0 : atc25_dpram_sim
771 
          generic map (abits => 8, dbits => 30, words => 256)
772 
          port map (a1, a2, i1, i2, o1, o2, csb1, csb2, oe1, oe2, web1, web2);
773 
end;
774 
 
775 
LIBRARY ieee;
776 
use IEEE.std_logic_1164.all;
777 
use work.tech_atc25_sim.all;
778 
entity DPRAM_256x32 is
779 
  port (A1     : IN std_logic_vector(7 DOWNTO 0);
780 
        A2     : IN std_logic_vector(7 DOWNTO 0);
781 
        CSB1   : IN std_logic;
782 
        CSB2   : IN std_logic;
783 
        WEB1   : IN std_logic;
784 
        WEB2   : IN std_logic;
785 
        OE1    : IN std_logic;
786 
        OE2    : IN std_logic;
787 
        I1     : IN std_logic_vector(31 downto 0);
788 
        I2     : IN std_logic_vector(31 downto 0);
789 
        O1     : OUT std_logic_vector(31 downto 0);
790 
        O2     : OUT std_logic_vector(31 downto 0));
791 
end;
792 
architecture behav of DPRAM_256x32 is
793 
begin
794 
    dp0 : atc25_dpram_sim
795 
          generic map (abits => 8, dbits => 32, words => 256)
796 
          port map (a1, a2, i1, i2, o1, o2, csb1, csb2, oe1, oe2, web1, web2);
797 
end;
798 
 
799 
LIBRARY ieee;
800 
use IEEE.std_logic_1164.all;
801 
use work.tech_atc25_sim.all;
802 
entity DPRAM_512x28 is
803 
  port (A1     : IN std_logic_vector(8 DOWNTO 0);
804 
        A2     : IN std_logic_vector(8 DOWNTO 0);
805 
        CSB1   : IN std_logic;
806 
        CSB2   : IN std_logic;
807 
        WEB1   : IN std_logic;
808 
        WEB2   : IN std_logic;
809 
        OE1    : IN std_logic;
810 
        OE2    : IN std_logic;
811 
        I1     : IN std_logic_vector(27 downto 0);
812 
        I2     : IN std_logic_vector(27 downto 0);
813 
        O1     : OUT std_logic_vector(27 downto 0);
814 
        O2     : OUT std_logic_vector(27 downto 0));
815 
end;
816 
architecture behav of DPRAM_512x28 is
817 
begin
818 
    dp0 : atc25_dpram_sim
819 
          generic map (abits => 9, dbits => 28, words => 512)
820 
          port map (a1, a2, i1, i2, o1, o2, csb1, csb2, oe1, oe2, web1, web2);
821 
end;
822 
 
823 
LIBRARY ieee;
824 
use IEEE.std_logic_1164.all;
825 
use work.tech_atc25_sim.all;
826 
entity DPRAM_512x30 is
827 
  port (A1     : IN std_logic_vector(8 DOWNTO 0);
828 
        A2     : IN std_logic_vector(8 DOWNTO 0);
829 
        CSB1   : IN std_logic;
830 
        CSB2   : IN std_logic;
831 
        WEB1   : IN std_logic;
832 
        WEB2   : IN std_logic;
833 
        OE1    : IN std_logic;
834 
        OE2    : IN std_logic;
835 
        I1     : IN std_logic_vector(29 downto 0);
836 
        I2     : IN std_logic_vector(29 downto 0);
837 
        O1     : OUT std_logic_vector(29 downto 0);
838 
        O2     : OUT std_logic_vector(29 downto 0));
839 
end;
840 
architecture behav of DPRAM_512x30 is
841 
begin
842 
    dp0 : atc25_dpram_sim
843 
          generic map (abits => 9, dbits => 30, words => 512)
844 
          port map (a1, a2, i1, i2, o1, o2, csb1, csb2, oe1, oe2, web1, web2);
845 
end;
846 
 
847 
LIBRARY ieee;
848 
use IEEE.std_logic_1164.all;
849 
use work.tech_atc25_sim.all;
850 
entity DPRAM_512x32 is
851 
  port (A1     : IN std_logic_vector(8 DOWNTO 0);
852 
        A2     : IN std_logic_vector(8 DOWNTO 0);
853 
        CSB1   : IN std_logic;
854 
        CSB2   : IN std_logic;
855 
        WEB1   : IN std_logic;
856 
        WEB2   : IN std_logic;
857 
        OE1    : IN std_logic;
858 
        OE2    : IN std_logic;
859 
        I1     : IN std_logic_vector(31 downto 0);
860 
        I2     : IN std_logic_vector(31 downto 0);
861 
        O1     : OUT std_logic_vector(31 downto 0);
862 
        O2     : OUT std_logic_vector(31 downto 0));
863 
end;
864 
architecture behav of DPRAM_512x32 is
865 
begin
866 
    dp0 : atc25_dpram_sim
867 
          generic map (abits => 9, dbits => 32, words => 512)
868 
          port map (a1, a2, i1, i2, o1, o2, csb1, csb2, oe1, oe2, web1, web2);
869 
end;
870 
 
871 
 
872 
-- pragma translate_on
873 
-- component declarations from true tech library
874 
 
875 
LIBRARY ieee;
876 
use IEEE.std_logic_1164.all;
877 
package tech_atc25_syn is
878 
 
879 
  -- various two-port rams (used for regfile)
880 
  component RAM2P_16X32 port (
881 
      RA, WA   : in  std_logic_vector(3 downto 0);
882 
      DI   : in  std_logic_vector(31 downto 0);
883 
      DO   : out std_logic_vector(31 downto 0);
884 
      REB, OEB, WEB  : in  std_logic );
885 
  end component;
886 
  component RAM2P_136X32 port (
887 
      RA, WA   : in  std_logic_vector(7 downto 0);
888 
      DI   : in  std_logic_vector(31 downto 0);
889 
      DO   : out std_logic_vector(31 downto 0);
890 
      REB, OEB, WEB  : in  std_logic );
891 
  end component;
892 
  component RAM2P_168X32 port (
893 
      RA, WA   : in  std_logic_vector(7 downto 0);
894 
      DI   : in  std_logic_vector(31 downto 0);
895 
      DO   : out std_logic_vector(31 downto 0);
896 
      REB, OEB, WEB  : in  std_logic );
897 
  end component;
898 
 
899 
  -- various single-port synchronous ram cells (used for caches)
900 
  component RAM_256x26 port (
901 
    a     : in std_logic_vector(7 downto 0);
902 
    i     : in std_logic_vector(25 downto 0);
903 
    o     : out std_logic_vector(25 downto 0);
904 
    ce, csb, oeb, web : in std_logic);
905 
  end component;
906 
  component RAM_256x28 port (
907 
    a     : in std_logic_vector(7 downto 0);
908 
    i     : in std_logic_vector(27 downto 0);
909 
    o     : out std_logic_vector(27 downto 0);
910 
    ce, csb, oeb, web : in std_logic);
911 
  end component;
912 
  component RAM_256x30 port (
913 
    a     : in std_logic_vector(7 downto 0);
914 
    i     : in std_logic_vector(29 downto 0);
915 
    o     : out std_logic_vector(29 downto 0);
916 
    ce, csb, oeb, web : in std_logic);
917 
  end component;
918 
  component RAM_512x28 port (
919 
    a     : in std_logic_vector(8 downto 0);
920 
    i     : in std_logic_vector(27 downto 0);
921 
    o     : out std_logic_vector(27 downto 0);
922 
    ce, csb, oeb, web : in std_logic);
923 
  end component;
924 
  component RAM_512x30 port (
925 
    a     : in std_logic_vector(8 downto 0);
926 
    i     : in std_logic_vector(29 downto 0);
927 
    o     : out std_logic_vector(29 downto 0);
928 
    ce, csb, oeb, web : in std_logic);
929 
  end component;
930 
  component RAM_512x32 port (
931 
    a     : in std_logic_vector(8 downto 0);
932 
    i     : in std_logic_vector(31 downto 0);
933 
    o     : out std_logic_vector(31 downto 0);
934 
    ce, csb, oeb, web : in std_logic);
935 
  end component;
936 
  component RAM_1024x32 port (
937 
    a     : in std_logic_vector(9 downto 0);
938 
    i     : in std_logic_vector(31 downto 0);
939 
    o     : out std_logic_vector(31 downto 0);
940 
    ce, csb, oeb, web : in std_logic);
941 
  end component;
942 
  component RAM_2048x32 port (
943 
    a     : in std_logic_vector(10 downto 0);
944 
    i     : in std_logic_vector(31 downto 0);
945 
    o     : out std_logic_vector(31 downto 0);
946 
    ce, csb, oeb, web : in std_logic);
947 
  end component;
948 
 
949 
-- dpram for tags when snooping is enabled or DSU trace buffer
950 
  component DPRAM_256x26
951 
  port (A1     : IN std_logic_vector(7 DOWNTO 0);
952 
        A2     : IN std_logic_vector(7 DOWNTO 0);
953 
        CSB1   : IN std_logic;
954 
        CSB2   : IN std_logic;
955 
        WEB1   : IN std_logic;
956 
        WEB2   : IN std_logic;
957 
        OE1    : IN std_logic;
958 
        OE2    : IN std_logic;
959 
        I1     : IN std_logic_vector(25 downto 0);
960 
        I2     : IN std_logic_vector(25 downto 0);
961 
        O1     : OUT std_logic_vector(25 downto 0);
962 
        O2     : OUT std_logic_vector(25 downto 0));
963 
  end component;
964 
  component DPRAM_256x28
965 
  port (A1     : IN std_logic_vector(7 DOWNTO 0);
966 
        A2     : IN std_logic_vector(7 DOWNTO 0);
967 
        CSB1   : IN std_logic;
968 
        CSB2   : IN std_logic;
969 
        WEB1   : IN std_logic;
970 
        WEB2   : IN std_logic;
971 
        OE1    : IN std_logic;
972 
        OE2    : IN std_logic;
973 
        I1     : IN std_logic_vector(27 downto 0);
974 
        I2     : IN std_logic_vector(27 downto 0);
975 
        O1     : OUT std_logic_vector(27 downto 0);
976 
        O2     : OUT std_logic_vector(27 downto 0));
977 
  end component;
978 
  component DPRAM_256x30
979 
  port (A1     : IN std_logic_vector(7 DOWNTO 0);
980 
        A2     : IN std_logic_vector(7 DOWNTO 0);
981 
        CSB1   : IN std_logic;
982 
        CSB2   : IN std_logic;
983 
        WEB1   : IN std_logic;
984 
        WEB2   : IN std_logic;
985 
        OE1    : IN std_logic;
986 
        OE2    : IN std_logic;
987 
        I1     : IN std_logic_vector(29 downto 0);
988 
        I2     : IN std_logic_vector(29 downto 0);
989 
        O1     : OUT std_logic_vector(29 downto 0);
990 
        O2     : OUT std_logic_vector(29 downto 0));
991 
  end component;
992 
  component DPRAM_256x32
993 
  port (A1     : IN std_logic_vector(7 DOWNTO 0);
994 
        A2     : IN std_logic_vector(7 DOWNTO 0);
995 
        CSB1   : IN std_logic;
996 
        CSB2   : IN std_logic;
997 
        WEB1   : IN std_logic;
998 
        WEB2   : IN std_logic;
999 
        OE1    : IN std_logic;
1000 
        OE2    : IN std_logic;
1001 
        I1     : IN std_logic_vector(31 downto 0);
1002 
        I2     : IN std_logic_vector(31 downto 0);
1003 
        O1     : OUT std_logic_vector(31 downto 0);
1004 
        O2     : OUT std_logic_vector(31 downto 0));
1005 
  end component;
1006 
  component DPRAM_512x28
1007 
  port (A1     : IN std_logic_vector(8 DOWNTO 0);
1008 
        A2     : IN std_logic_vector(8 DOWNTO 0);
1009 
        CSB1   : IN std_logic;
1010 
        CSB2   : IN std_logic;
1011 
        WEB1   : IN std_logic;
1012 
        WEB2   : IN std_logic;
1013 
        OE1    : IN std_logic;
1014 
        OE2    : IN std_logic;
1015 
        I1     : IN std_logic_vector(27 downto 0);
1016 
        I2     : IN std_logic_vector(27 downto 0);
1017 
        O1     : OUT std_logic_vector(27 downto 0);
1018 
        O2     : OUT std_logic_vector(27 downto 0));
1019 
  end component;
1020 
  component DPRAM_512x30
1021 
  port (A1     : IN std_logic_vector(8 DOWNTO 0);
1022 
        A2     : IN std_logic_vector(8 DOWNTO 0);
1023 
        CSB1   : IN std_logic;
1024 
        CSB2   : IN std_logic;
1025 
        WEB1   : IN std_logic;
1026 
        WEB2   : IN std_logic;
1027 
        OE1    : IN std_logic;
1028 
        OE2    : IN std_logic;
1029 
        I1     : IN std_logic_vector(29 downto 0);
1030 
        I2     : IN std_logic_vector(29 downto 0);
1031 
        O1     : OUT std_logic_vector(29 downto 0);
1032 
        O2     : OUT std_logic_vector(29 downto 0));
1033 
  end component;
1034 
  component DPRAM_512x32
1035 
  port (A1     : IN std_logic_vector(8 DOWNTO 0);
1036 
        A2     : IN std_logic_vector(8 DOWNTO 0);
1037 
        CSB1   : IN std_logic;
1038 
        CSB2   : IN std_logic;
1039 
        WEB1   : IN std_logic;
1040 
        WEB2   : IN std_logic;
1041 
        OE1    : IN std_logic;
1042 
        OE2    : IN std_logic;
1043 
        I1     : IN std_logic_vector(31 downto 0);
1044 
        I2     : IN std_logic_vector(31 downto 0);
1045 
        O1     : OUT std_logic_vector(31 downto 0);
1046 
        O2     : OUT std_logic_vector(31 downto 0));
1047 
  end component;
1048 
 
1049 
  -- input pad
1050 
  component pt33d00 port (pad : in std_logic; cin : out std_logic); end component;
1051 
  -- input pad with pull-up
1052 
  component pt33d00u port (pad : in std_logic; cin : out std_logic); end component;
1053 
  -- schmitt input pad
1054 
  component pt33d20 port (pad : in std_logic; cin : out std_logic); end component;
1055 
  -- schmitt input pad with pull-up
1056 
  component pt33d20u port (pad : inout std_logic; cin : out std_logic); end component;
1057 
  -- output pads
1058 
  component pt33o01 port (i : in std_logic; pad : out std_logic); end component;
1059 
  component pt33o02 port (i : in std_logic; pad : out std_logic); end component;
1060 
  component pt33o03 port (i : in std_logic; pad : out std_logic); end component;
1061 
  component pt33o04 port (i : in std_logic; pad : out std_logic); end component;
1062 
  -- tri-state output pads with pull-up
1063 
  component pt33t01u port (i, oen : in std_logic; pad : out std_logic); end component;
1064 
  component pt33t02u port (i, oen : in std_logic; pad : out std_logic); end component;
1065 
  component pt33t03u port (i, oen : in std_logic; pad : out std_logic); end component;
1066 
  component pt33t04u port (i, oen : in std_logic; pad : out std_logic); end component;
1067 
  -- bidirectional pads
1068 
  component pt33b01
1069 
    port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
1070 
  end component;
1071 
  component pt33b02
1072 
    port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
1073 
  end component;
1074 
  component pt33b03
1075 
    port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
1076 
  end component;
1077 
  component pt33b04
1078 
    port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
1079 
  end component;
1080 
  -- bidirectional pads with pull-up
1081 
  component pt33b01u
1082 
    port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
1083 
  end component;
1084 
  component pt33b02u
1085 
    port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
1086 
  end component;
1087 
  component pt33b03u
1088 
    port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
1089 
  end component;
1090 
  component pt33b04u
1091 
    port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
1092 
  end component;
1093 
--PCI pads
1094 
  component pp33o01
1095 
    port (i : in  std_logic; pad : out  std_logic);
1096 
  end component;
1097 
  component pp33b015vt
1098 
    port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
1099 
  end component;
1100 
  component pp33t015vt
1101 
    port (i, oen : in  std_logic; pad : out  std_logic);
1102 
  end component;
1103 
end;
1104 
------------------------------------------------------------------
1105 
-- sync ram generator --------------------------------------------
1106 
------------------------------------------------------------------
1107 
 
1108 
library IEEE;
1109 
use IEEE.std_logic_1164.all;
1110 
use work.tech_atc25_syn.all;
1111 
use work.leon_iface.all;
1112 
 
1113 
 
1114 
entity atc25_syncram is
1115 
  generic ( abits : integer := 10; dbits : integer := 8 );
1116 
  port (
1117 
    address  : in std_logic_vector(abits -1 downto 0);
1118 
    clk      : in clk_type;
1119 
    datain   : in std_logic_vector(dbits -1 downto 0);
1120 
    dataout  : out std_logic_vector(dbits -1 downto 0);
1121 
    enable   : in std_logic;
1122 
    write    : in std_logic
1123 
  );
1124 
end;
1125 
 
1126 
architecture rtl of atc25_syncram is
1127 
  signal wen, wel, gnd   : std_logic;
1128 
  signal d, q : std_logic_vector(35 downto 0);
1129 
  signal a : std_logic_vector(17 downto 0);
1130 
  constant synopsys_bug : std_logic_vector(37 downto 0) := (others => '0');
1131 
begin
1132 
 
1133 
 
1134 
  lat : process(clk, datain, write)
1135 
  begin
1136 
    if clk = '0' then d(dbits -1 downto 0) <= datain; wel <= write; end if;
1137 
  end process;
1138 
 
1139 
  gnd <= '0';
1140 
  wen <= not wel;
1141 
  a(abits -1 downto 0) <= address;
1142 
  a(abits+1 downto abits) <= synopsys_bug(abits+1 downto abits);
1143 
  d(dbits+1 downto dbits) <= synopsys_bug(dbits+1 downto dbits);
1144 
  dataout <= q(dbits -1 downto 0);
1145 
 
1146 
  a8d26 : if (abits <= 8) and (dbits <= 26) generate
1147 
    id0 : RAM_256x26
1148 
 
1149 
          port map (a(7 downto 0), d(25 downto 0), q(25 downto 0), clk, gnd, gnd, wen);
1150 
 
1151 
  end generate;
1152 
  a8d28 : if (abits <= 8) and (dbits > 26) and (dbits <= 28) generate
1153 
    id0 : RAM_256x28
1154 
 
1155 
          port map (a(7 downto 0), d(27 downto 0), q(27 downto 0), clk, gnd, gnd, wen);
1156 
 
1157 
  end generate;
1158 
  a8d30 : if (abits <= 8) and (dbits > 28) and (dbits <= 30) generate
1159 
    id0 : RAM_256x30
1160 
 
1161 
          port map (a(7 downto 0), d(29 downto 0), q(29 downto 0), clk, gnd, gnd, wen);
1162 
 
1163 
  end generate;
1164 
  a9d28 : if (abits = 9) and (dbits <= 28) generate
1165 
    id0 : RAM_512x28
1166 
 
1167 
          port map (a(8 downto 0), d(27 downto 0), q(27 downto 0), clk, gnd, gnd, wen);
1168 
 
1169 
  end generate;
1170 
  a9d30 : if (abits = 9) and (dbits > 28) and (dbits <= 30) generate
1171 
    id0 : RAM_512x30
1172 
 
1173 
          port map (a(8 downto 0), d(29 downto 0), q(29 downto 0), clk, gnd, gnd, wen);
1174 
 
1175 
  end generate;
1176 
  a9d32 : if ((abits = 9) and (dbits > 29) and (dbits <= 32)) or
1177 
               ((abits <= 9) and (dbits = 32)) generate
1178 
    id0 : RAM_512X32
1179 
 
1180 
          port map (a(8 downto 0), d(31 downto 0), q(31 downto 0), clk, gnd, gnd, wen);
1181 
 
1182 
  end generate;
1183 
  a10d32 : if ((abits = 10) and (dbits <= 32)) generate
1184 
    id0 : RAM_1024X32
1185 
 
1186 
          port map (a(9 downto 0), d(31 downto 0), q(31 downto 0), clk, gnd, gnd, wen);
1187 
 
1188 
  end generate;
1189 
  a11d32 : if (abits = 11) and (dbits <= 32) generate
1190 
    id0 : RAM_2048X32
1191 
 
1192 
          port map (a(10 downto 0), d(31 downto 0), q(31 downto 0), clk, gnd, gnd, wen);
1193 
 
1194 
  end generate;
1195 
 
1196 
end rtl;
1197 
 
1198 
------------------------------------------------------------------
1199 
-- sync dpram generator --------------------------------------------
1200 
------------------------------------------------------------------
1201 
 
1202 
library IEEE;
1203 
use IEEE.std_logic_1164.all;
1204 
use work.tech_atc25_syn.all;
1205 
use work.leon_iface.all;
1206 
 
1207 
 
1208 
entity atc25_dpram is
1209 
  generic ( abits : integer := 10; dbits : integer := 8 );
1210 
  port (
1211 
    address1 : in std_logic_vector((abits -1) downto 0);
1212 
    clk      : in clk_type;
1213 
    datain1  : in std_logic_vector((dbits -1) downto 0);
1214 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
1215 
    enable1  : in std_logic;
1216 
    write1   : in std_logic;
1217 
    address2 : in std_logic_vector((abits -1) downto 0);
1218 
    datain2  : in std_logic_vector((dbits -1) downto 0);
1219 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
1220 
    enable2  : in std_logic;
1221 
    write2   : in std_logic
1222 
   );
1223 
end;
1224 
architecture rtl of atc25_dpram is
1225 
  signal web1, web2, csb1, csb2, vcc : std_logic;
1226 
  signal web1n, web2n, csb1n, csb2n  : std_logic;
1227 
  signal web1nc, web2nc : std_logic;
1228 
  signal i1, i2, a1, a2, i11, i22, a11, a22, o1, o2 : std_logic_vector(35 downto 0);
1229 
begin
1230 
 
1231 
  vcc <= '1';
1232 
  i11(35 downto dbits) <= (others => '0');
1233 
  i22(35 downto dbits) <= (others => '0');
1234 
  a11(35 downto abits) <= (others => '0');
1235 
  a22(35 downto abits) <= (others => '0');
1236 
  -- add delay or address/data will not be valid during write
1237 
  a1 <= a11; a2 <= a22; i1 <= i11; i2 <= i22;
1238 
  csb1n <= not enable1; csb2n <= not enable2;
1239 
  web1n <= not write1;  web2n <= not write2;
1240 
 
1241 
  web1nc <= web1 or clk; web2nc <= web2 or clk;
1242 
  r : process (clk)
1243 
  begin
1244 
    if rising_edge(clk) then
1245 
      a11(abits-1 downto 0) <= address1;
1246 
      a22(abits-1 downto 0) <= address2;
1247 
      i11(dbits-1 downto 0) <= datain1;
1248 
      i22(dbits-1 downto 0) <= datain2;
1249 
      csb1 <= csb1n; csb2 <= csb2n;
1250 
      web1 <= web1n; web2 <= web2n;
1251 
    end if;
1252 
  end process;
1253 
 
1254 
  dp256x26 : if (abits <= 8) and (dbits <= 26) generate
1255 
    dp0 : DPRAM_256x26 port map (
1256 
        a1(7 downto 0), a2(7 downto 0),
1257 
        csb1, csb2, web1nc, web2nc, vcc, web2,
1258 
        i1(25 downto 0), i2(25 downto 0),
1259 
        o1(25 downto 0), o2(25 downto 0));
1260 
  end generate;
1261 
 
1262 
  dp256x28 : if (abits <= 8) and (dbits <= 28) and (dbits >= 27) generate
1263 
    dp0 : DPRAM_256x28 port map (
1264 
        a1(7 downto 0), a2(7 downto 0),
1265 
        csb1, csb2, web1nc, web2nc, vcc, web2,
1266 
        i1(27 downto 0), i2(27 downto 0),
1267 
        o1(27 downto 0), o2(27 downto 0));
1268 
  end generate;
1269 
 
1270 
  dp256x30 : if (abits <= 8) and (dbits <= 30) and (dbits >= 29) generate
1271 
    dp0 : DPRAM_256x30 port map (
1272 
        a1(7 downto 0), a2(7 downto 0),
1273 
        csb1, csb2, web1nc, web2nc, vcc, web2,
1274 
        i1(29 downto 0), i2(29 downto 0),
1275 
        o1(29 downto 0), o2(29 downto 0));
1276 
  end generate;
1277 
 
1278 
  dp256x32 : if (abits <= 8) and (dbits <= 32) and (dbits >= 31) generate
1279 
    dp0 : DPRAM_256x32 port map (
1280 
        a1(7 downto 0), a2(7 downto 0),
1281 
        csb1, csb2, web1nc, web2nc, vcc, web2,
1282 
        i1(31 downto 0), i2(31 downto 0),
1283 
        o1(31 downto 0), o2(31 downto 0));
1284 
  end generate;
1285 
 
1286 
  dp512x28 : if (abits = 9) and (dbits <= 28) generate
1287 
    dp0 : DPRAM_512x28 port map (
1288 
        a1(8 downto 0), a2(8 downto 0),
1289 
        csb1, csb2, web1nc, web2nc, vcc, web2,
1290 
        i1(27 downto 0), i2(27 downto 0),
1291 
        o1(27 downto 0), o2(27 downto 0));
1292 
  end generate;
1293 
 
1294 
  dp512x30 : if (abits = 9) and (dbits <= 30) and (dbits >= 29) generate
1295 
    dp0 : DPRAM_512x30 port map (
1296 
        a1(8 downto 0), a2(8 downto 0),
1297 
        csb1, csb2, web1nc, web2nc, vcc, web2,
1298 
        i1(29 downto 0), i2(29 downto 0),
1299 
        o1(29 downto 0), o2(29 downto 0));
1300 
  end generate;
1301 
 
1302 
  dp512x32 : if (abits = 9) and (dbits <= 32) and (dbits >= 31) generate
1303 
    dp0 : DPRAM_512x32 port map (
1304 
        a1(8 downto 0), a2(8 downto 0),
1305 
        csb1, csb2, web1nc, web2nc, vcc, web2,
1306 
        i1(31 downto 0), i2(31 downto 0),
1307 
        o1(31 downto 0), o2(31 downto 0));
1308 
  end generate;
1309 
 
1310 
  dataout1 <= o1(dbits-1 downto 0);
1311 
  dataout2 <= o2(dbits-1 downto 0);
1312 
 
1313 
end;
1314 
 
1315 
------------------------------------------------------------------
1316 
-- regfile generator  --------------------------------------------
1317 
------------------------------------------------------------------
1318 
 
1319 
LIBRARY ieee;
1320 
use IEEE.std_logic_1164.all;
1321 
use IEEE.std_logic_arith.all;
1322 
use work.tech_generic.all;
1323 
use work.tech_atc25_syn.all;
1324 
use work.leon_iface.all;
1325 
use work.leon_config.all;
1326 
 
1327 
entity atc25_regfile_iu is
1328 
  generic (
1329 
    rftype : integer := 1;
1330 
    abits : integer := 8;
1331 
    dbits : integer := 32;
1332 
    words : integer := 128
1333 
  );
1334 
  port (
1335 
    rst      : in std_logic;
1336 
    clk      : in clk_type;
1337 
    clkn     : in clk_type;
1338 
    rfi      : in rf_in_type;
1339 
    rfo      : out rf_out_type);
1340 
end;
1341 
 
1342 
architecture rtl of atc25_regfile_iu is
1343 
signal din1, din2, qq1, qq2 : std_logic_vector(39 downto 0);
1344 
signal vcc, gnd, we, wen, ren1, ren2 : std_logic;
1345 
signal ra1, ra2, wa : std_logic_vector(12 downto 0);
1346 
begin
1347 
 
1348 
  rf2 : if rftype = 2 generate
1349 
 
1350 
      r : process (clkn, rfi) begin
1351 
 
1352 
        if clkn = '1' then
1353 
          din2(dbits-1 downto 0) <= rfi.wrdata;
1354 
 
1355 
          din1(dbits-1 downto 0) <= rfi.wrdata;
1356 
          wa(abits-1 downto 0)  <= rfi.wraddr(abits -1 downto 0);
1357 
          we <= rfi.wren;
1358 
        end if;
1359 
      end process;
1360 
 
1361 
    wen <= not (clk and we);
1362 
 
1363 
  end generate;
1364 
  rf1 : if rftype = 1 generate
1365 
    wa(abits-1 downto 0)  <= rfi.wraddr(abits -1 downto 0);
1366 
    din1(dbits-1 downto 0) <= rfi.wrdata;
1367 
    din2(dbits-1 downto 0) <= rfi.wrdata;
1368 
 
1369 
    wen <= clk or not rfi.wren;
1370 
 
1371 
  end generate;
1372 
 
1373 
  vcc <= '1'; gnd <= '0'; ren1 <= not rfi.ren1; ren2 <= not rfi.ren2;
1374 
  ra1(12 downto abits)  <= (others => '0');
1375 
  ra2(12 downto abits)  <= (others => '0');
1376 
  ra1(abits-1 downto 0) <= rfi.rd1addr(abits -1 downto 0);
1377 
  ra2(abits-1 downto 0) <= rfi.rd2addr(abits -1 downto 0);
1378 
 
1379 
  wa(12 downto abits)   <= (others => '0');
1380 
  din1(39 downto dbits) <= (others => '0');
1381 
  din2(39 downto dbits) <= (others => '0');
1382 
 
1383 
  dp136x32 : if (words = 136) and (dbits = 32) generate
1384 
    u0: RAM2P_136X32
1385 
        port map (ra1(7 downto 0), wa(7 downto 0), din1(31 downto 0),
1386 
                  qq1(31 downto 0), ren1, gnd, wen);
1387 
    u1: RAM2P_136X32
1388 
        port map (ra2(7 downto 0), wa(7 downto 0), din2(31 downto 0),
1389 
                  qq2(31 downto 0), ren2, gnd, wen);
1390 
  end generate;
1391 
 
1392 
  dp168x32 : if (words = 168) and (dbits = 32) generate
1393 
    u0: RAM2P_168X32
1394 
        port map (ra1(7 downto 0), wa(7 downto 0), din1(31 downto 0),
1395 
                  qq1(31 downto 0), ren1, gnd, wen);
1396 
    u1: RAM2P_168X32
1397 
        port map (ra2(7 downto 0), wa(7 downto 0), din2(31 downto 0),
1398 
                  qq2(31 downto 0), ren2, gnd, wen);
1399 
  end generate;
1400 
 
1401 
 
1402 
  rfo.data1(dbits-1 downto 0) <= qq1(dbits-1 downto 0);
1403 
  rfo.data2(dbits-1 downto 0) <= qq2(dbits-1 downto 0);
1404 
 
1405 
end;
1406 
 
1407 
LIBRARY ieee;
1408 
use IEEE.std_logic_1164.all;
1409 
use IEEE.std_logic_arith.all;
1410 
use work.tech_generic.all;
1411 
use work.tech_atc25_syn.all;
1412 
use work.leon_iface.all;
1413 
 
1414 
entity atc25_regfile_cp is
1415 
  generic (
1416 
    abits : integer := 4;
1417 
    dbits : integer := 32;
1418 
    words : integer := 16
1419 
  );
1420 
  port (
1421 
    rst      : in std_logic;
1422 
    clk      : in clk_type;
1423 
    rfi      : in rf_cp_in_type;
1424 
    rfo      : out rf_cp_out_type);
1425 
end;
1426 
 
1427 
architecture rtl of atc25_regfile_cp is
1428 
type reg_type is record
1429 
  raddr1  : std_logic_vector(abits-1 downto 0);
1430 
  raddr2  : std_logic_vector(abits-1 downto 0);
1431 
  wraddr  : std_logic_vector(abits-1 downto 0);
1432 
  wrdata  : std_logic_vector(dbits-1 downto 0);
1433 
  wren    : std_logic;
1434 
end record;
1435 
signal r, rin : reg_type;
1436 
 
1437 
signal din1, qq1, qq2 : std_logic_vector(39 downto 0);
1438 
signal wa : std_logic_vector(abits-1 downto 0);
1439 
signal vcc, gnd, wen : std_logic;
1440 
begin
1441 
  vcc <= '1'; gnd <= '0';
1442 
 
1443 
  wen <= clk or not r.wren;
1444 
 
1445 
  din1(dbits-1 downto 0) <= r.wrdata;
1446 
  din1(39 downto dbits) <= (others => '0');
1447 
  wa <= r.wraddr;
1448 
 
1449 
  dp16x32 : if (words = 16) and (dbits = 32) generate
1450 
    u0: RAM2P_16X32
1451 
        port map (r.raddr1(3 downto 0), wa(3 downto 0), din1(dbits-1 downto 0),
1452 
                  qq1(31 downto 0), gnd, gnd, wen);
1453 
    u1: RAM2P_16X32
1454 
        port map (r.raddr2(3 downto 0), wa(3 downto 0), din1(dbits-1 downto 0),
1455 
                  qq2(31 downto 0), gnd, gnd, wen);
1456 
  end generate;
1457 
 
1458 
    adr_reg : process(clk)
1459 
    begin
1460 
 
1461 
      if rising_edge(clk) then
1462 
 
1463 
        r.raddr1 <= rfi.rd1addr(abits -1 downto 0);
1464 
        r.raddr2 <= rfi.rd2addr(abits -1 downto 0);
1465 
        r.wraddr <= rfi.wraddr(abits -1 downto 0);
1466 
        r.wrdata <= rfi.wrdata;
1467 
        r.wren <= rfi.wren;
1468 
      end if;
1469 
    end process;
1470 
 
1471 
  rfo.data1(dbits-1 downto 0) <= qq1(dbits-1 downto 0);
1472 
  rfo.data2(dbits-1 downto 0) <= qq2(dbits-1 downto 0);
1473 
 
1474 
end;
1475 
 
1476 
------------------------------------------------------------------
1477 
-- mapping generic pads on tech pads ---------------------------------
1478 
------------------------------------------------------------------
1479 
 
1480 
-- input pad
1481 
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc25_syn.all;
1482 
entity atc25_inpad is port (pad : in std_logic; q : out std_logic); end;
1483 
architecture syn of atc25_inpad is begin
1484 
  i0 : pt33d00 port map (pad => pad, cin => q);
1485 
end;
1486 
 
1487 
-- input schmitt pad
1488 
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc25_syn.all;
1489 
entity atc25_smpad is port (pad : in std_logic; q : out std_logic); end;
1490 
architecture syn of atc25_smpad is begin
1491 
  i0 : pt33d20 port map (pad => pad, cin => q);
1492 
end;
1493 
 
1494 
-- output pad
1495 
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc25_syn.all;
1496 
entity atc25_outpad is
1497 
  generic (drive : integer := 1);
1498 
  port (d : in std_logic; pad : out std_logic);
1499 
end;
1500 
architecture syn of atc25_outpad is begin
1501 
  d1 : if drive = 1 generate
1502 
    i0 : pt33o01 port map (pad => pad, i => d);
1503 
  end generate;
1504 
  d2 : if drive = 2 generate
1505 
    i0 : pt33o02 port map (pad => pad, i => d);
1506 
  end generate;
1507 
  d3 : if drive > 2 generate
1508 
    i0 : pt33o03 port map (pad => pad, i => d);
1509 
  end generate;
1510 
end;
1511 
 
1512 
-- tri-state output pads with pull-up, oen active low
1513 
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc25_syn.all;
1514 
entity atc25_toutpadu is
1515 
  generic (drive : integer := 1);
1516 
  port (d, en : in  std_logic; pad : out  std_logic);
1517 
end;
1518 
architecture syn of atc25_toutpadu is
1519 
begin
1520 
  d1 : if drive = 1 generate
1521 
    i0 : pt33t01u port map (pad => pad, i => d, oen => en);
1522 
  end generate;
1523 
  d2 : if drive = 2 generate
1524 
    i0 : pt33t02u port map (pad => pad, i => d, oen => en);
1525 
  end generate;
1526 
  d3 : if drive > 3 generate
1527 
    i0 : pt33t03u port map (pad => pad, i => d, oen => en);
1528 
  end generate;
1529 
end;
1530 
 
1531 
-- bidirectional pad, oen active low
1532 
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc25_syn.all;
1533 
entity atc25_iopad is
1534 
  generic (drive : integer := 1);
1535 
  port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
1536 
end;
1537 
architecture syn of atc25_iopad is
1538 
begin
1539 
  d1 : if drive = 1 generate
1540 
    i0 : pt33b01 port map (pad => pad, i => d, oen => en, cin => q);
1541 
  end generate;
1542 
  d2 : if drive = 2 generate
1543 
    i0 : pt33b02 port map (pad => pad, i => d, oen => en, cin => q);
1544 
  end generate;
1545 
  d3 : if drive > 2 generate
1546 
    i0 : pt33b03 port map (pad => pad, i => d, oen => en, cin => q);
1547 
  end generate;
1548 
end;
1549 
 
1550 
-- bidirectional pad with pull-up, oen active low
1551 
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc25_syn.all;
1552 
entity atc25_iopadu is
1553 
  generic (drive : integer := 1);
1554 
  port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
1555 
end;
1556 
architecture syn of atc25_iopadu is
1557 
begin
1558 
  d1 : if drive = 1 generate
1559 
    i0 : pt33b01u port map (pad => pad, i => d, oen => en, cin => q);
1560 
  end generate;
1561 
  d2 : if drive = 2 generate
1562 
    i0 : pt33b02u port map (pad => pad, i => d, oen => en, cin => q);
1563 
  end generate;
1564 
  d3 : if drive > 2 generate
1565 
    i0 : pt33b03u port map (pad => pad, i => d, oen => en, cin => q);
1566 
  end generate;
1567 
end;
1568 
 
1569 
-- bidirectional pad with open-drain
1570 
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc25_syn.all;
1571 
entity atc25_iodpad is
1572 
  generic (drive : integer := 1);
1573 
  port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
1574 
end;
1575 
architecture syn of atc25_iodpad is
1576 
signal gnd : std_logic;
1577 
begin
1578 
  gnd <= '0';
1579 
  d1 : if drive = 1 generate
1580 
    i0 : pt33b01u port map (pad => pad, i => gnd, oen => d, cin => q);
1581 
  end generate;
1582 
  d2 : if drive = 2 generate
1583 
    i0 : pt33b02u port map (pad => pad, i => gnd, oen => d, cin => q);
1584 
  end generate;
1585 
  d3 : if drive > 2 generate
1586 
    i0 : pt33b03u port map (pad => pad, i => gnd, oen => d, cin => q);
1587 
  end generate;
1588 
end;
1589 
 
1590 
-- output pad with open-drain
1591 
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc25_syn.all;
1592 
entity atc25_odpad is
1593 
  generic (drive : integer := 1);
1594 
  port (d : in std_logic; pad : out std_logic);
1595 
end;
1596 
architecture syn of atc25_odpad is
1597 
signal gnd : std_logic;
1598 
begin
1599 
  gnd <= '0';
1600 
  d1 : if drive = 1 generate
1601 
    i0 : pt33t01u port map (pad => pad, i => gnd, oen => d);
1602 
  end generate;
1603 
  d2 : if drive = 2 generate
1604 
    i0 : pt33t02u port map (pad => pad, i => gnd, oen => d);
1605 
  end generate;
1606 
  d3 : if drive > 2 generate
1607 
    i0 : pt33t03u port map (pad => pad, i => gnd, oen => d);
1608 
  end generate;
1609 
end;
1610 
 
1611 
-- PCI output pad
1612 
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc25_syn.all;
1613 
entity atc25_pcioutpad is port (d : in std_logic; pad : out std_logic); end;
1614 
architecture syn of atc25_pcioutpad is begin
1615 
  i0 : pp33o01 port map (pad => pad, i => d);
1616 
end;
1617 
-- PCI tristate output pad
1618 
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc25_syn.all;
1619 
entity atc25_pcitoutpad is
1620 
port (d, en : in  std_logic; pad : out  std_logic); end;
1621 
architecture syn of atc25_pcitoutpad is
1622 
begin
1623 
  i0 : pp33t015vt port map (pad => pad, i => d, oen => en);
1624 
end;
1625 
-- PCI bidirectional pad, oen active low
1626 
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc25_syn.all;
1627 
entity atc25_pciiopad is
1628 
  port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
1629 
end;
1630 
architecture syn of atc25_pciiopad is
1631 
begin
1632 
  i0 : pp33b015vt port map (pad => pad, i => d, oen => en, cin => q);
1633 
end;
1634 
-- bidirectional pad with open-drain
1635 
library IEEE; use IEEE.std_logic_1164.all; use work.tech_atc25_syn.all;
1636 
entity atc25_pciiodpad is
1637 
  port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
1638 
end;
1639 
architecture syn of atc25_pciiodpad is
1640 
signal gnd : std_logic;
1641 
begin
1642 
  gnd <= '0';
1643 
  i0 : pp33b015vt port map (pad => pad, i => gnd, oen => d, cin => q);
1644 
end;
1645 
 

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