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[/] [core_arm/] [trunk/] [vhdl/] [tech/] [tech_atc35.vhd] - Blame information for rev 4

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2 
 
3 
 
4 
 
5 
----------------------------------------------------------------------------
6 
--  This file is a part of the LEON VHDL model
7 
--  Copyright (C) 1999  European Space Agency (ESA)
8 
--
9 
--  This library is free software; you can redistribute it and/or
10 
--  modify it under the terms of the GNU Lesser General Public
11 
--  License as published by the Free Software Foundation; either
12 
--  version 2 of the License, or (at your option) any later version.
13 
--
14 
--  See the file COPYING.LGPL for the full details of the license.
15 
 
16 
 
17 
-----------------------------------------------------------------------------
18 
-- Entity:      tech_atc35
19 
-- File:        tech_atc35.vhd
20 
-- Author:      Jiri Gaisler - ESA/ESTEC
21 
-- Description: Contains Atmel ATC35 specific pads and ram generators
22 
------------------------------------------------------------------------------
23 
 
24 
LIBRARY ieee;
25 
use IEEE.std_logic_1164.all;
26 
use work.leon_iface.all;
27 
 
28 
package tech_atc35 is
29 
 
30 
-- sync ram generator
31 
 
32 
  component atc35_syncram
33 
  generic ( abits : integer := 10; dbits : integer := 8 );
34 
  port (
35 
    address  : in std_logic_vector(abits -1 downto 0);
36 
    clk      : in std_logic;
37 
    datain   : in std_logic_vector(dbits -1 downto 0);
38 
    dataout  : out std_logic_vector(dbits -1 downto 0);
39 
    enable   : in std_logic;
40 
    write    : in std_logic);
41 
  end component;
42 
 
43 
-- regfile generator
44 
 
45 
  component atc35_regfile
46 
  generic ( abits : integer := 8; dbits : integer := 32; words : integer := 128);
47 
  port (
48 
    rst      : in std_logic;
49 
    clk      : in clk_type;
50 
    clkn     : in clk_type;
51 
    rfi      : in rf_in_type;
52 
    rfo      : out rf_out_type);
53 
  end component;
54 
 
55 
  component atc35_regfile_cp
56 
  generic ( abits : integer := 4; dbits : integer := 32; words : integer := 16);
57 
  port (
58 
    rst      : in std_logic;
59 
    clk      : in clk_type;
60 
    rfi      : in rf_cp_in_type;
61 
    rfo      : out rf_cp_out_type);
62 
  end component;
63 
 
64 
-- pads
65 
 
66 
  component atc35_inpad port (pad : in std_logic; q : out std_logic); end component;
67 
  component atc35_smpad port (pad : in std_logic; q : out std_logic); end component;
68 
  component atc35_outpad
69 
    generic (drive : integer := 1);
70 
    port (d : in  std_logic; pad : out  std_logic);
71 
  end component;
72 
  component atc35_toutpadu
73 
    generic (drive : integer := 1);
74 
    port (d, en : in  std_logic; pad : out  std_logic);
75 
  end component;
76 
  component atc35_iopad
77 
    generic (drive : integer := 1);
78 
    port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
79 
  end component;
80 
  component atc35_iopadu
81 
    generic (drive : integer := 1);
82 
    port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
83 
  end component;
84 
  component atc35_iodpad
85 
    generic (drive : integer := 1);
86 
    port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
87 
  end component;
88 
  component atc35_odpad
89 
    generic (drive : integer := 1);
90 
    port ( d : in std_logic; pad : out std_logic);
91 
  end component;
92 
 
93 
end;
94 
 
95 
------------------------------------------------------------------
96 
-- behavioural pad models --------------------------------------------
97 
------------------------------------------------------------------
98 
-- Only needed for simulation, not synthesis.
99 
-- pragma translate_off
100 
 
101 
-- input pad
102 
library IEEE;
103 
use IEEE.std_logic_1164.all;
104 
entity pc3d01 is port (pad : in std_logic; cin : out std_logic); end;
105 
architecture rtl of pc3d01 is begin cin <= to_x01(pad) after 1 ns; end;
106 
 
107 
-- input schmitt pad
108 
library IEEE;
109 
use IEEE.std_logic_1164.all;
110 
entity pc3d21 is port (pad : in std_logic; cin : out std_logic); end;
111 
architecture rtl of pc3d21 is begin cin <= to_x01(pad) after 1 ns; end;
112 
 
113 
-- output pads
114 
library IEEE;
115 
use IEEE.std_logic_1164.all;
116 
entity pt3o01 is port (i : in  std_logic; pad : out  std_logic); end;
117 
architecture rtl of pt3o01 is begin pad <= to_x01(i) after 2 ns; end;
118 
library IEEE;
119 
use IEEE.std_logic_1164.all;
120 
entity pt3o02 is port (i : in  std_logic; pad : out  std_logic); end;
121 
architecture rtl of pt3o02 is begin pad <= to_x01(i) after 2 ns; end;
122 
library IEEE;
123 
use IEEE.std_logic_1164.all;
124 
entity pt3o03 is port (i : in  std_logic; pad : out  std_logic); end;
125 
architecture rtl of pt3o03 is begin pad <= to_x01(i) after 2 ns; end;
126 
 
127 
-- output tri-state pads
128 
library IEEE;
129 
use IEEE.std_logic_1164.all;
130 
entity pc3t01u is port (i, oen : in  std_logic; pad : out  std_logic); end;
131 
architecture rtl of pc3t01u is
132 
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns; end;
133 
library IEEE;
134 
use IEEE.std_logic_1164.all;
135 
entity pc3t02u is port (i, oen : in  std_logic; pad : out  std_logic); end;
136 
architecture rtl of pc3t02u is
137 
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns; end;
138 
library IEEE;
139 
use IEEE.std_logic_1164.all;
140 
entity pc3t03u is port (i, oen : in  std_logic; pad : out  std_logic); end;
141 
architecture rtl of pc3t03u is
142 
begin pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns; end;
143 
 
144 
-- bidirectional pad
145 
library IEEE;
146 
use IEEE.std_logic_1164.all;
147 
entity pt3b01 is
148 
  port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
149 
end;
150 
architecture rtl of pt3b01 is
151 
begin
152 
  pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
153 
  cin <= to_x01(pad) after 2 ns;
154 
end;
155 
library IEEE;
156 
use IEEE.std_logic_1164.all;
157 
entity pt3b02 is
158 
  port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
159 
end;
160 
architecture rtl of pt3b02 is
161 
begin
162 
  pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
163 
  cin <= to_x01(pad) after 2 ns;
164 
end;
165 
library IEEE;
166 
use IEEE.std_logic_1164.all;
167 
entity pt3b03 is
168 
  port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
169 
end;
170 
architecture rtl of pt3b03 is
171 
begin
172 
  pad <= to_x01(i) after 2 ns when oen = '0' else 'Z' after 2 ns;
173 
  cin <= to_x01(pad) after 2 ns;
174 
end;
175 
 
176 
------------------------------------------------------------------
177 
-- behavioural ram models ----------------------------------------
178 
------------------------------------------------------------------
179 
--  Address and control latched on rising clka, data latched on falling clkb.
180 
 
181 
LIBRARY ieee;
182 
use IEEE.std_logic_1164.all;
183 
use IEEE.std_logic_arith.all;
184 
 
185 
entity atc35_dpram_ss_dn is
186 
  generic (
187 
    abits : integer := 8;
188 
    dbits : integer := 32;
189 
    words : integer := 256
190 
  );
191 
  port (
192 
    data: in std_logic_vector (dbits -1 downto 0);
193 
    rdaddress: in std_logic_vector (abits -1 downto 0);
194 
    wraddress: in std_logic_vector (abits -1 downto 0);
195 
    wren : in std_logic;
196 
    clka, clkb : in std_logic;
197 
    q: out std_logic_vector (dbits -1 downto 0)
198 
  );
199 
end;
200 
 
201 
architecture behav of atc35_dpram_ss_dn is
202 
signal dr : std_logic_vector (dbits -1 downto 0);
203 
signal ra,wa : std_logic_vector (abits -1 downto 0);
204 
signal wer : std_logic;
205 
begin
206 
  rp : process(clka, clkb, rdaddress, wren, wraddress, data, wa, ra, wer)
207 
  subtype dword is std_logic_vector(dbits -1 downto 0);
208 
  type dregtype is array (0 to words - 1) of DWord;
209 
  variable rfd : dregtype;
210 
  begin
211 
    if falling_edge(clkb) and (wer = '1') then
212 
      if not is_x (wa) then
213 
        rfd(conv_integer(unsigned(wa)) mod words) := data;
214 
      end if;
215 
    end if;
216 
    if rising_edge(clka) then
217 
      ra <= rdaddress; wa <= wraddress; wer <= wren;
218 
    end if;
219 
    if not (is_x (ra) or ((wer = '1') and (ra = wa))) then
220 
      q <= rfd(conv_integer(unsigned(ra)) mod words);
221 
    else q <= (others => 'X'); end if;
222 
  end process;
223 
end;
224 
 
225 
LIBRARY ieee;
226 
use IEEE.std_logic_1164.all;
227 
package tech_atc35_sim is
228 
 
229 
-- syncronous dpram with data latched on falling edge
230 
 
231 
component atc35_dpram_ss_dn
232 
  generic (
233 
    abits : integer := 8;
234 
    dbits : integer := 32;
235 
    words : integer := 256
236 
  );
237 
  port (
238 
    data: in std_logic_vector (dbits -1 downto 0);
239 
    rdaddress: in std_logic_vector (abits -1 downto 0);
240 
    wraddress: in std_logic_vector (abits -1 downto 0);
241 
    wren : in std_logic;
242 
    clka, clkb : in std_logic;
243 
    q: out std_logic_vector (dbits -1 downto 0)
244 
  );
245 
end component;
246 
 
247 
end;
248 
-- Address, control and data signals latched on rising ME.
249 
-- Write enable (WEN) active low.
250 
 
251 
library ieee;
252 
use IEEE.std_logic_1164.all;
253 
use work.tech_generic.all;
254 
 
255 
entity ATC35_RAM_256x26 is
256 
  port (
257 
    add   : in std_logic_vector(7 downto 0);
258 
    di    : in std_logic_vector(25 downto 0);
259 
    do    : out std_logic_vector(25 downto 0);
260 
    me    : in std_logic;
261 
    wen   : in std_logic
262 
  );
263 
end;
264 
 
265 
architecture behavioral of ATC35_RAM_256x26 is
266 
signal we, vcc : std_logic;
267 
begin
268 
  vcc <= '1'; we <= not wen;
269 
  syncram0 : generic_syncram
270 
    generic map ( abits => 8, dbits => 26)
271 
    port map ( add, me, di, do, vcc, we);
272 
end behavioral;
273 
 
274 
library ieee;
275 
use IEEE.std_logic_1164.all;
276 
use work.tech_generic.all;
277 
 
278 
entity ATC35_RAM_1024x32 is
279 
  port (
280 
    add   : in std_logic_vector(9 downto 0);
281 
    di    : in std_logic_vector(31 downto 0);
282 
    do    : out std_logic_vector(31 downto 0);
283 
    me    : in std_logic;
284 
    wen   : in std_logic
285 
  );
286 
end;
287 
 
288 
architecture behavioral of ATC35_RAM_1024x32 is
289 
signal we, vcc : std_logic;
290 
begin
291 
  vcc <= '1'; we <= not wen;
292 
  syncram0 : generic_syncram
293 
    generic map ( abits => 10, dbits => 32)
294 
    port map ( add, me, di, do, vcc, we);
295 
end behavioral;
296 
 
297 
library ieee;
298 
use IEEE.std_logic_1164.all;
299 
use work.tech_generic.all;
300 
 
301 
entity ATC35_RAM_2048x32 is
302 
  port (
303 
    add   : in std_logic_vector(10 downto 0);
304 
    di    : in std_logic_vector(31 downto 0);
305 
    do    : out std_logic_vector(31 downto 0);
306 
    me    : in std_logic;
307 
    wen   : in std_logic
308 
  );
309 
end;
310 
 
311 
architecture behavioral of ATC35_RAM_2048x32 is
312 
signal we, vcc : std_logic;
313 
begin
314 
  vcc <= '1'; we <= not wen;
315 
  syncram0 : generic_syncram
316 
    generic map ( abits => 11, dbits => 32)
317 
    port map ( add, me, di, do, vcc, we);
318 
end behavioral;
319 
 
320 
 
321 
library ieee;
322 
use IEEE.std_logic_1164.all;
323 
use work.tech_generic.all;
324 
 
325 
entity ATC35_RAM_256x28 is
326 
  port (
327 
    add   : in std_logic_vector(7 downto 0);
328 
    di    : in std_logic_vector(27 downto 0);
329 
    do    : out std_logic_vector(27 downto 0);
330 
    me    : in std_logic;
331 
    wen   : in std_logic
332 
  );
333 
end;
334 
 
335 
architecture behavioral of ATC35_RAM_256x28 is
336 
signal we, vcc : std_logic;
337 
begin
338 
  vcc <= '1'; we <= not wen;
339 
  syncram0 : generic_syncram
340 
    generic map ( abits => 8, dbits => 28)
341 
    port map ( add, me, di, do, vcc, we);
342 
end behavioral;
343 
 
344 
library ieee;
345 
use IEEE.std_logic_1164.all;
346 
use work.tech_generic.all;
347 
 
348 
entity ATC35_RAM_1024x34 is
349 
  port (
350 
    add   : in std_logic_vector(9 downto 0);
351 
    di    : in std_logic_vector(33 downto 0);
352 
    do    : out std_logic_vector(33 downto 0);
353 
    me    : in std_logic;
354 
    wen   : in std_logic
355 
  );
356 
end;
357 
 
358 
architecture behavioral of ATC35_RAM_1024x34 is
359 
signal we, vcc : std_logic;
360 
begin
361 
  vcc <= '1'; we <= not wen;
362 
  syncram0 : generic_syncram
363 
    generic map ( abits => 10, dbits => 34)
364 
    port map ( add, me, di, do, vcc, we);
365 
end behavioral;
366 
 
367 
library ieee;
368 
use IEEE.std_logic_1164.all;
369 
use work.tech_generic.all;
370 
 
371 
entity ATC35_RAM_2048x34 is
372 
  port (
373 
    add   : in std_logic_vector(10 downto 0);
374 
    di    : in std_logic_vector(33 downto 0);
375 
    do    : out std_logic_vector(33 downto 0);
376 
    me    : in std_logic;
377 
    wen   : in std_logic
378 
  );
379 
end;
380 
 
381 
architecture behavioral of ATC35_RAM_2048x34 is
382 
signal we, vcc : std_logic;
383 
begin
384 
  vcc <= '1'; we <= not wen;
385 
  syncram0 : generic_syncram
386 
    generic map ( abits => 11, dbits => 34)
387 
    port map ( add, me, di, do, vcc, we);
388 
end behavioral;
389 
 
390 
 
391 
LIBRARY ieee;
392 
use IEEE.std_logic_1164.all;
393 
use work.tech_atc35_sim.all;
394 
 
395 
entity DPRAMRWRW_16X32 is
396 
 port (
397 
    ADDA : in  std_logic_vector(3 downto 0);
398 
    ADDB : in  std_logic_vector(3 downto 0);
399 
    DIA  : in  std_logic_vector(31 downto 0);
400 
    DIB  : in  std_logic_vector(31 downto 0);
401 
    DOA  : out std_logic_vector(31 downto 0);
402 
    DOB  : out std_logic_vector(31 downto 0);
403 
    MEA  : in  std_logic;
404 
    MEB  : in  std_logic;
405 
    WENA : in  std_logic;
406 
    WENB : in  std_logic
407 
    );
408 
end;
409 
 
410 
architecture behav of DPRAMRWRW_16X32 is
411 
signal wen : std_logic;
412 
begin
413 
    wen <= not wenb;
414 
    dp0 : atc35_dpram_ss_dn generic map (abits => 4, dbits => 32, words => 16)
415 
                      port map ( dib, adda, addb, wen, mea, meb, doa);
416 
end;
417 
 
418 
LIBRARY ieee;
419 
use IEEE.std_logic_1164.all;
420 
use work.tech_atc35_sim.all;
421 
 
422 
entity DPRAMRWRW_136X32 is
423 
 port (
424 
    ADDA : in  std_logic_vector(7 downto 0);
425 
    ADDB : in  std_logic_vector(7 downto 0);
426 
    DIA  : in  std_logic_vector(31 downto 0);
427 
    DIB  : in  std_logic_vector(31 downto 0);
428 
    DOA  : out std_logic_vector(31 downto 0);
429 
    DOB  : out std_logic_vector(31 downto 0);
430 
    MEA  : in  std_logic;
431 
    MEB  : in  std_logic;
432 
    WENA : in  std_logic;
433 
    WENB : in  std_logic
434 
    );
435 
end;
436 
 
437 
architecture behav of DPRAMRWRW_136X32 is
438 
signal wen : std_logic;
439 
begin
440 
    wen <= not wenb;
441 
    dp0 : atc35_dpram_ss_dn generic map (abits => 8, dbits => 32, words => 136)
442 
                      port map ( dib, adda, addb, wen, mea, meb, doa);
443 
end;
444 
 
445 
LIBRARY ieee;
446 
use IEEE.std_logic_1164.all;
447 
use work.tech_atc35_sim.all;
448 
 
449 
entity DPRAMRWRW_168X32 is
450 
 port (
451 
    ADDA : in  std_logic_vector(7 downto 0);
452 
    ADDB : in  std_logic_vector(7 downto 0);
453 
    DIA  : in  std_logic_vector(31 downto 0);
454 
    DIB  : in  std_logic_vector(31 downto 0);
455 
    DOA  : out std_logic_vector(31 downto 0);
456 
    DOB  : out std_logic_vector(31 downto 0);
457 
    MEA  : in  std_logic;
458 
    MEB  : in  std_logic;
459 
    WENA : in  std_logic;
460 
    WENB : in  std_logic
461 
    );
462 
end;
463 
 
464 
architecture behav of DPRAMRWRW_168X32 is
465 
signal wen : std_logic;
466 
begin
467 
    wen <= not wenb;
468 
    dp0 : atc35_dpram_ss_dn generic map (abits => 8, dbits => 32, words => 168)
469 
                      port map ( dib, adda, addb, wen, mea, meb, doa);
470 
end;
471 
 
472 
 
473 
 
474 
-- pragma translate_on
475 
 
476 
-- component declarations from true tech library
477 
LIBRARY ieee;
478 
use IEEE.std_logic_1164.all;
479 
package tech_atc35_syn is
480 
-- Atmel ram cells
481 
  component ATC35_RAM_256x26
482 
    port (
483 
    add   : in std_logic_vector(7 downto 0);
484 
    di    : in std_logic_vector(25 downto 0);
485 
    do    : out std_logic_vector(25 downto 0);
486 
    me    : in std_logic;
487 
    wen   : in std_logic);
488 
  end component;
489 
  component ATC35_RAM_1024x32
490 
    port (
491 
    add   : in std_logic_vector(9 downto 0);
492 
    di    : in std_logic_vector(31 downto 0);
493 
    do    : out std_logic_vector(31 downto 0);
494 
    me    : in std_logic;
495 
    wen   : in std_logic);
496 
  end component;
497 
  component ATC35_RAM_2048x32
498 
    port (
499 
    add   : in std_logic_vector(10 downto 0);
500 
    di    : in std_logic_vector(31 downto 0);
501 
    do    : out std_logic_vector(31 downto 0);
502 
    me    : in std_logic;
503 
    wen   : in std_logic);
504 
  end component;
505 
 
506 
component DPRAMRWRW_16X32
507 
 port (
508 
    ADDA : in  std_logic_vector(3 downto 0);
509 
    ADDB : in  std_logic_vector(3 downto 0);
510 
    DIA  : in  std_logic_vector(31 downto 0);
511 
    DIB  : in  std_logic_vector(31 downto 0);
512 
    DOA  : out std_logic_vector(31 downto 0);
513 
    DOB  : out std_logic_vector(31 downto 0);
514 
    MEA  : in  std_logic;
515 
    MEB  : in  std_logic;
516 
    WENA : in  std_logic;
517 
    WENB : in  std_logic
518 
    );
519 
end component;
520 
component DPRAMRWRW_136X32
521 
 port (
522 
    ADDA : in  std_logic_vector(7 downto 0);
523 
    ADDB : in  std_logic_vector(7 downto 0);
524 
    DIA  : in  std_logic_vector(31 downto 0);
525 
    DIB  : in  std_logic_vector(31 downto 0);
526 
    DOA  : out std_logic_vector(31 downto 0);
527 
    DOB  : out std_logic_vector(31 downto 0);
528 
    MEA  : in  std_logic;
529 
    MEB  : in  std_logic;
530 
    WENA : in  std_logic;
531 
    WENB : in  std_logic
532 
    );
533 
end component;
534 
component DPRAMRWRW_168X32
535 
 port (
536 
    ADDA : in  std_logic_vector(7 downto 0);
537 
    ADDB : in  std_logic_vector(7 downto 0);
538 
    DIA  : in  std_logic_vector(31 downto 0);
539 
    DIB  : in  std_logic_vector(31 downto 0);
540 
    DOA  : out std_logic_vector(31 downto 0);
541 
    DOB  : out std_logic_vector(31 downto 0);
542 
    MEA  : in  std_logic;
543 
    MEB  : in  std_logic;
544 
    WENA : in  std_logic;
545 
    WENB : in  std_logic
546 
    );
547 
end component;
548 
 
549 
  component
550 
    pc3d01 port (pad : in std_logic; cin : out std_logic);
551 
  end component;
552 
  component
553 
    pc3d21 port (pad : in std_logic; cin : out std_logic);
554 
  end component;
555 
  component
556 
    pt3o01 port (i : in std_logic; pad : out std_logic);
557 
  end component;
558 
  component
559 
    pt3o02 port (i : in std_logic; pad : out std_logic);
560 
  end component;
561 
  component
562 
    pt3o03 port (i : in std_logic; pad : out std_logic);
563 
  end component;
564 
  component
565 
    pc3t01u port (i, oen : in std_logic; pad : out std_logic);
566 
  end component;
567 
  component
568 
    pc3t02u port (i, oen : in std_logic; pad : out std_logic);
569 
  end component;
570 
  component
571 
    pc3t03u port (i, oen : in std_logic; pad : out std_logic);
572 
 end component;
573 
  component pt3b01
574 
    port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
575 
  end component;
576 
  component pt3b02
577 
    port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
578 
  end component;
579 
  component pt3b03
580 
    port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
581 
  end component;
582 
end;
583 
 
584 
------------------------------------------------------------------
585 
-- sync ram generator --------------------------------------------
586 
------------------------------------------------------------------
587 
 
588 
library IEEE;
589 
use IEEE.std_logic_1164.all;
590 
use work.tech_atc35_syn.all;
591 
 
592 
entity atc35_syncram is
593 
  generic ( abits : integer := 10; dbits : integer := 8 );
594 
  port (
595 
    address  : in std_logic_vector(abits -1 downto 0);
596 
    clk      : in std_logic;
597 
    datain   : in std_logic_vector(dbits -1 downto 0);
598 
    dataout  : out std_logic_vector(dbits -1 downto 0);
599 
    enable   : in std_logic;
600 
    write    : in std_logic
601 
  );
602 
end;
603 
 
604 
architecture rtl of atc35_syncram is
605 
  signal wr   : std_logic;
606 
  signal a    : std_logic_vector(19 downto 0);
607 
  signal d, q : std_logic_vector(34 downto 0);
608 
  constant synopsys_bug : std_logic_vector(37 downto 0) := (others => '0');
609 
begin
610 
 
611 
  wr <= not write;
612 
  a(abits -1 downto 0) <= address;
613 
  a(abits+1 downto abits) <= synopsys_bug(abits+1 downto abits);
614 
  d(dbits -1 downto 0) <= datain;
615 
  d(dbits+1 downto dbits) <= synopsys_bug(dbits+1 downto dbits);
616 
 
617 
  dataout <= q(dbits -1 downto 0);
618 
 
619 
  a8d26 : if (abits <= 8) and (dbits <= 26) generate
620 
    id0 : ATC35_RAM_256x26
621 
          port map ( a(7 downto 0), d(25 downto 0), q(25 downto 0), clk, wr);
622 
  end generate;
623 
  a10d32 : if (abits > 8) and (abits <= 10) and (dbits <= 32) generate
624 
    id0 : ATC35_RAM_1024X32
625 
          port map ( a(9 downto 0), d(31 downto 0), q(31 downto 0), clk, wr);
626 
  end generate;
627 
  a11d32 : if (abits = 11) and (dbits <= 32) generate
628 
    id0 : ATC35_RAM_2048X32
629 
          port map ( a(10 downto 0), d(31 downto 0), q(31 downto 0), clk, wr);
630 
  end generate;
631 
 
632 
end rtl;
633 
 
634 
------------------------------------------------------------------
635 
-- regfile generator  --------------------------------------------
636 
------------------------------------------------------------------
637 
 
638 
LIBRARY ieee;
639 
use IEEE.std_logic_1164.all;
640 
use IEEE.std_logic_arith.all;
641 
use work.leon_iface.all;
642 
 
643 
use work.tech_atc35_syn.all;
644 
 
645 
entity atc35_regfile is
646 
  generic (
647 
    abits : integer := 8;
648 
    dbits : integer := 32;
649 
    words : integer := 128
650 
  );
651 
  port (
652 
    rst      : in std_logic;
653 
    clk      : in clk_type;
654 
    clkn     : in clk_type;
655 
    rfi      : in rf_in_type;
656 
    rfo      : out rf_out_type);
657 
end;
658 
 
659 
architecture rtl of atc35_regfile is
660 
 
661 
signal din, dx, qq1, qq2, qx1, qx2 : std_logic_vector(31 downto 0);
662 
 
663 
signal vcc, wen : std_logic;
664 
signal ra1, ra2, wa : std_logic_vector(12 downto 0);
665 
begin
666 
  wen <= not rfi.wren; dx <= (others => '0'); vcc <= '1';
667 
  ra1(abits-1 downto 0) <= rfi.rd1addr;
668 
  ra1(12 downto abits) <= (others => '0');
669 
  ra2(abits-1 downto 0) <= rfi.rd2addr;
670 
  ra2(12 downto abits) <= (others => '0');
671 
  wa(abits-1 downto 0) <= rfi.wraddr;
672 
  wa(12 downto abits) <= (others => '0');
673 
  rfo.data1 <= qq1(dbits-1 downto 0);
674 
  rfo.data2 <= qq2(dbits-1 downto 0);
675 
 
676 
 
677 
  lat : process(rfi, clkn)
678 
  begin
679 
    if (clkn = '0') then din(dbits-1 downto 0) <= rfi.wrdata; end if;
680 
  end process;
681 
 
682 
 
683 
  dp16x32 : if (words = 16) and (dbits = 32) generate
684 
    u0: DPRAMRWRW_16X32
685 
        port map (ra1(3 downto 0), wa(3 downto 0), dx(31 downto 0),
686 
 
687 
                  din(31 downto 0), qq1(31 downto 0), qx1(31 downto 0), clkn,
688 
                  clkn, vcc, wen);
689 
 
690 
    u1: DPRAMRWRW_16X32
691 
        port map (ra2(3 downto 0), wa(3 downto 0), dx(31 downto 0),
692 
 
693 
                  din(31 downto 0), qq2(31 downto 0), qx2(31 downto 0), clkn,
694 
                  clkn, vcc, wen);
695 
 
696 
  end generate;
697 
 
698 
  dp136x32 : if (words = 136) and (dbits = 32) generate
699 
    u0: DPRAMRWRW_136X32
700 
        port map (ra1(7 downto 0), wa(7 downto 0), dx(31 downto 0), din(31 downto 0),
701 
 
702 
                  qq1(31 downto 0), qx1(31 downto 0), clkn, clkn, vcc, wen);
703 
 
704 
    u1: DPRAMRWRW_136X32
705 
        port map (ra2(7 downto 0), wa(7 downto 0), dx(31 downto 0), din(31 downto 0),
706 
 
707 
                  qq2(31 downto 0), qx2(31 downto 0), clkn, clkn, vcc, wen);
708 
 
709 
  end generate;
710 
 
711 
  dp168x32 : if (words = 168) and (dbits = 32) generate
712 
    u0: DPRAMRWRW_168X32
713 
        port map (ra1(7 downto 0), wa(7 downto 0), dx(31 downto 0), din(31 downto 0),
714 
 
715 
                  qq1(31 downto 0), qx1(31 downto 0), clkn, clkn, vcc, wen);
716 
 
717 
    u1: DPRAMRWRW_168X32
718 
        port map (ra2(7 downto 0), wa(7 downto 0), dx(31 downto 0), din(31 downto 0),
719 
 
720 
                  qq2(31 downto 0), qx2(31 downto 0), clkn, clkn, vcc, wen);
721 
 
722 
  end generate;
723 
 
724 
 
725 
 
726 
end;
727 
 
728 
LIBRARY ieee;
729 
use IEEE.std_logic_1164.all;
730 
use IEEE.std_logic_arith.all;
731 
use work.leon_iface.all;
732 
 
733 
use work.tech_atc35_syn.all;
734 
 
735 
entity atc35_regfile_cp is
736 
  generic (
737 
    abits : integer := 4;
738 
    dbits : integer := 32;
739 
    words : integer := 16
740 
  );
741 
  port (
742 
    rst      : in std_logic;
743 
    clk      : in clk_type;
744 
    rfi      : in rf_cp_in_type;
745 
    rfo      : out rf_cp_out_type);
746 
end;
747 
 
748 
architecture rtl of atc35_regfile_cp is
749 
 
750 
signal din, dx, qq1, qq2, qx1, qx2 : std_logic_vector(31 downto 0);
751 
 
752 
signal vcc, wen : std_logic;
753 
signal ra1, ra2, wa : std_logic_vector(12 downto 0);
754 
begin
755 
  wen <= not rfi.wren; dx <= (others => '0'); vcc <= '1';
756 
  ra1(abits-1 downto 0) <= rfi.rd1addr;
757 
  ra1(12 downto abits) <= (others => '0');
758 
  ra2(abits-1 downto 0) <= rfi.rd2addr;
759 
  ra2(12 downto abits) <= (others => '0');
760 
  wa(abits-1 downto 0) <= rfi.wraddr;
761 
  wa(12 downto abits) <= (others => '0');
762 
  rfo.data1 <= qq1(dbits-1 downto 0);
763 
  rfo.data2 <= qq2(dbits-1 downto 0);
764 
 
765 
 
766 
  lat : process(rfi, clk)
767 
  begin
768 
    if (clk = '0') then din(dbits-1 downto 0) <= rfi.wrdata; end if;
769 
  end process;
770 
 
771 
 
772 
  dp16x32 : if (words = 16) and (dbits = 32) generate
773 
    u0: DPRAMRWRW_16X32
774 
        port map (ra1(3 downto 0), wa(3 downto 0), dx(31 downto 0),
775 
 
776 
                  din(31 downto 0), qq1(31 downto 0), qx1(31 downto 0), clk,
777 
                  clk, vcc, wen);
778 
 
779 
    u1: DPRAMRWRW_16X32
780 
        port map (ra2(3 downto 0), wa(3 downto 0), dx(31 downto 0),
781 
 
782 
                  din(31 downto 0), qq2(31 downto 0), qx2(31 downto 0), clk,
783 
                  clk, vcc, wen);
784 
 
785 
  end generate;
786 
 
787 
 
788 
end;
789 
 
790 
------------------------------------------------------------------
791 
-- mapping generic pads on tech pads ---------------------------------
792 
------------------------------------------------------------------
793 
 
794 
-- input pad
795 
library IEEE;
796 
use IEEE.std_logic_1164.all;
797 
use work.tech_atc35_syn.all;
798 
entity atc35_inpad is port (pad : in std_logic; q : out std_logic); end;
799 
architecture syn of atc35_inpad is begin
800 
  i0 : pc3d01 port map (pad => pad, cin => q);
801 
end;
802 
 
803 
-- input schmitt pad
804 
library IEEE;
805 
use IEEE.std_logic_1164.all;
806 
use work.tech_atc35_syn.all;
807 
entity atc35_smpad is port (pad : in std_logic; q : out std_logic); end;
808 
architecture syn of atc35_smpad is begin
809 
  i0 : pc3d21 port map (pad => pad, cin => q);
810 
end;
811 
 
812 
-- output pads
813 
library IEEE;
814 
use IEEE.std_logic_1164.all;
815 
use work.tech_atc35_syn.all;
816 
entity atc35_outpad is
817 
  generic (drive : integer := 1);
818 
  port (d : in std_logic; pad : out std_logic);
819 
end;
820 
architecture syn of atc35_outpad is begin
821 
  d1 : if drive = 1 generate
822 
    i0 : pt3o01 port map (pad => pad, i => d);
823 
  end generate;
824 
  d2 : if drive = 2 generate
825 
    i0 : pt3o02 port map (pad => pad, i => d);
826 
  end generate;
827 
  d3 : if drive > 2 generate
828 
    i0 : pt3o03 port map (pad => pad, i => d);
829 
  end generate;
830 
end;
831 
 
832 
-- tri-state output pads with pull-up
833 
library IEEE;
834 
use IEEE.std_logic_1164.all;
835 
use work.tech_atc35_syn.all;
836 
entity atc35_toutpadu is
837 
  generic (drive : integer := 1);
838 
  port (d, en : in  std_logic; pad : out  std_logic);
839 
end;
840 
architecture syn of atc35_toutpadu is
841 
begin
842 
  d1 : if drive = 1 generate
843 
    i0 : pc3t01u port map (pad => pad, i => d, oen => en);
844 
  end generate;
845 
  d2 : if drive = 2 generate
846 
    i0 : pc3t02u port map (pad => pad, i => d, oen => en);
847 
  end generate;
848 
  d3 : if drive > 2 generate
849 
    i0 : pc3t03u port map (pad => pad, i => d, oen => en);
850 
  end generate;
851 
end;
852 
 
853 
-- bidirectional pad
854 
library IEEE;
855 
use IEEE.std_logic_1164.all;
856 
use work.tech_atc35_syn.all;
857 
entity atc35_iopad is
858 
  generic (drive : integer := 1);
859 
  port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
860 
end;
861 
architecture syn of atc35_iopad is
862 
begin
863 
  d1 : if drive = 1 generate
864 
    i0 : pt3b01 port map (pad => pad, i => d, oen => en, cin => q);
865 
  end generate;
866 
  d2 : if drive = 2 generate
867 
    i0 : pt3b02 port map (pad => pad, i => d, oen => en, cin => q);
868 
  end generate;
869 
  d3 : if drive > 2 generate
870 
    i0 : pt3b03 port map (pad => pad, i => d, oen => en, cin => q);
871 
  end generate;
872 
end;
873 
 
874 
-- bidirectional pad with open-drain
875 
library IEEE;
876 
use IEEE.std_logic_1164.all;
877 
use work.tech_atc35_syn.all;
878 
entity atc35_iodpad is
879 
  generic (drive : integer := 1);
880 
  port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
881 
end;
882 
architecture syn of atc35_iodpad is
883 
signal gnd : std_logic;
884 
begin
885 
  gnd <= '0';
886 
  d1 : if drive = 1 generate
887 
    i0 : pt3b01 port map (pad => pad, i => gnd, oen => d, cin => q);
888 
  end generate;
889 
  d2 : if drive = 2 generate
890 
    i0 : pt3b02 port map (pad => pad, i => gnd, oen => d, cin => q);
891 
  end generate;
892 
  d3 : if drive > 2 generate
893 
    i0 : pt3b03 port map (pad => pad, i => gnd, oen => d, cin => q);
894 
  end generate;
895 
end;
896 
 
897 
-- output pad with open-drain
898 
library IEEE;
899 
use IEEE.std_logic_1164.all;
900 
use work.tech_atc35_syn.all;
901 
entity atc35_odpad is
902 
  generic (drive : integer := 1);
903 
  port (d : in std_logic; pad : out std_logic);
904 
end;
905 
architecture syn of atc35_odpad is
906 
signal gnd : std_logic;
907 
begin
908 
  gnd <= '0';
909 
  d1 : if drive = 1 generate
910 
    i0 : pc3t01u port map (pad => pad, i => gnd, oen => d);
911 
  end generate;
912 
  d2 : if drive = 2 generate
913 
    i0 : pc3t02u port map (pad => pad, i => gnd, oen => d);
914 
  end generate;
915 
  d3 : if drive > 2 generate
916 
    i0 : pc3t03u port map (pad => pad, i => gnd, oen => d);
917 
  end generate;
918 
end;
919 
 

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