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[/] [core_arm/] [trunk/] [vhdl/] [tech/] [tech_axcel.vhd] - Blame information for rev 4

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----------------------------------------------------------------------------
--  This file is a part of the LEON VHDL model
--  Copyright (C) 1999  European Space Agency (ESA)
--
--  This library is free software; you can redistribute it and/or
--  modify it under the terms of the GNU Lesser General Public
--  License as published by the Free Software Foundation; either
--  version 2 of the License, or (at your option) any later version.
--
--  See the file COPYING.LGPL for the full details of the license.
 
 
-----------------------------------------------------------------------------
-- Entity:      tech_axcel
-- File:        tech_axcel.vhd
-- Author:      Jiri Gaisler - Gaisler Research
-- Description: Ram generators for Actel Axcelerator FPGAs
------------------------------------------------------------------------------
 
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.leon_iface.all;
package tech_axcel is
 
-- generic sync ram
 
component axcel_syncram
  generic ( abits : integer := 10; dbits : integer := 8 );
  port (
    address  : in std_logic_vector((abits -1) downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector((dbits -1) downto 0);
    dataout  : out std_logic_vector((dbits -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
   );
end component;
 
-- regfile generator
 
component axcel_regfile_iu
  generic (
    rftype : integer := 1;
    abits : integer := 8; dbits : integer := 32; words : integer := 128
  );
  port (
    rst      : in std_logic;
    clk      : in std_logic;
    clkn     : in std_logic;
    rfi      : in rf_in_type;
    rfo      : out rf_out_type);
  end component;
 
component axcel_regfile_cp
  generic (
    abits : integer := 4; dbits : integer := 32; words : integer := 16
  );
  port (
    rst      : in std_logic;
    clk      : in std_logic;
    rfi      : in rf_cp_in_type;
    rfo      : out rf_cp_out_type);
end component;
 
end;
 
------------------------------------------------------------------
-- behavioural ram models --------------------------------------------
------------------------------------------------------------------
 
-- pragma translate_off
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.tech_generic.all;
 
entity RAM64K36 is generic (abits : integer := 16); port(
  WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,
  WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,
  WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,
  WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,
  WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,
  RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,
  RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;
  RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,
  RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,
  RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);
end;
 
architecture rtl of RAM64K36 is
  signal re : std_logic;
begin
 
  rp : process(RCLK, WCLK)
  constant words : integer := 2**abits;
  subtype word is std_logic_vector(35 downto 0);
  type dregtype is array (0 to words - 1) of word;
  variable rfd : dregtype;
  variable wa, ra : std_logic_vector(15 downto 0);
  variable q : std_logic_vector(35 downto 0);
  begin
    if rising_edge(WCLK) and (wen = '0') then
      wa := WRAD15 & WRAD14 & WRAD13 & WRAD12 & WRAD11 & WRAD10 & WRAD9 &
            WRAD8 & WRAD7 & WRAD6 & WRAD5 & WRAD4 & WRAD3 & WRAD2 & WRAD1 & WRAD0;
      if not is_x (wa) then
        rfd(conv_integer(unsigned(wa)) mod words) :=
          WD35 & WD34 & WD33 & WD32 & WD31 & WD30 & WD29 & WD28 & WD27 &
          WD26 & WD25 & WD24 & WD23 & WD22 & WD21 & WD20 & WD19 & WD18 &
          WD17 & WD16 & WD15 & WD14 & WD13 & WD12 & WD11 & WD10 & WD9 &
          WD8 & WD7 & WD6 & WD5 & WD4 & WD3 & WD2 & WD1 & WD0;
      end if;
    end if;
    if rising_edge(RCLK) then
      ra := RDAD15 & RDAD14 & RDAD13 & RDAD12 & RDAD11 & RDAD10 & RDAD9 &
            RDAD8 & RDAD7 & RDAD6 & RDAD5 & RDAD4 & RDAD3 & RDAD2 & RDAD1 & RDAD0;
      if not (is_x (ra)) and REN = '0' then
        q := rfd(conv_integer(unsigned(ra)) mod words);
      else q := (others => 'X'); end if;
    end if;
    RD35 <= q(35); RD34 <= q(34); RD33 <= q(33); RD32 <= q(32); RD31 <= q(31);
    RD30 <= q(30); RD29 <= q(29); RD28 <= q(28); RD27 <= q(27); RD26 <= q(26);
    RD25 <= q(25); RD24 <= q(24); RD23 <= q(23); RD22 <= q(22); RD21 <= q(21);
    RD20 <= q(20); RD19 <= q(19); RD18 <= q(18); RD17 <= q(17); RD16 <= q(16);
    RD15 <= q(15); RD14 <= q(14); RD13 <= q(13); RD12 <= q(12); RD11 <= q(11);
    RD10 <= q(10); RD9 <= q(9); RD8 <= q(8); RD7 <= q(7); RD6 <= q(6);
    RD5 <= q(5); RD4 <= q(4); RD3 <= q(3); RD2 <= q(2); RD1 <= q(1);
    RD0 <= q(0);
  end process;
end;
 
-- pragma translate_on
 
--------------------------------------------------------------------
-- A simpler interface to the syncram
--------------------------------------------------------------------
 
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.leon_config.all;
use work.leon_iface.all;
entity axcel_ssram is
  generic (abits : integer := 16; dbits : integer := 36);
  port (
    wa, ra       : in  std_logic_vector(15 downto 0);
    wclk, rclk   : in  std_logic;
    di           : in  std_logic_vector(dbits -1 downto 0);
    do           : out std_logic_vector(dbits -1 downto 0);
    width        : in  std_logic_vector(2 downto 0);
    ren, wen     : in  std_logic
   );
end;
 
architecture rtl of axcel_ssram is
signal gnd : std_logic;
component RAM64K36
-- pragma translate_off
  generic (abits : integer := 16);
-- pragma translate_on
  port(
  WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,
  WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,
  WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,
  WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,
  WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,
  RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,
  RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;
  RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,
  RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,
  RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);
end component;
attribute syn_black_box : boolean;
attribute syn_black_box of RAM64K36 : component is true;
attribute syn_tco1 : string;
attribute syn_tco1 of RAM64K36 : component is
"RCLK->RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13, RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26, RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 = 4.0";
signal depth : std_logic_vector(4 downto 0);
signal d, q : std_logic_vector(36 downto 0);
begin
  depth <= "00000";
  do <= q(dbits-1 downto 0);
  d(dbits-1 downto 0) <= di;
  d(36 downto dbits) <= (others => '0');
    u0 : RAM64K36
-- pragma translate_off
    generic map (abits => abits)
-- pragma translate_on
    port map (
      WRAD0 => wa(0), WRAD1 => wa(1), WRAD2 => wa(2), WRAD3 => wa(3),
      WRAD4 => wa(4), WRAD5 => wa(5), WRAD6 => wa(6), WRAD7 => wa(7),
      WRAD8 => wa(8), WRAD9 => wa(9), WRAD10 => wa(10), WRAD11 => wa(11),
      WRAD12 => wa(12), WRAD13 => wa(13), WRAD14 => wa(14), WRAD15 => wa(15),
      WD0 => d(0), WD1 => d(1), WD2 => d(2), WD3 => d(3), WD4 => d(4),
      WD5 => d(5), WD6 => d(6), WD7 => d(7), WD8 => d(8), WD9 => d(9),
      WD10 => d(10), WD11 => d(11), WD12 => d(12), WD13 => d(13), WD14 => d(14),
      WD15 => d(15), WD16 => d(16), WD17 => d(17), WD18 => d(18), WD19 => d(19),
      WD20 => d(20), WD21 => d(21), WD22 => d(22), WD23 => d(23), WD24 => d(24),
      WD25 => d(25), WD26 => d(26), WD27 => d(27), WD28 => d(28), WD29 => d(29),
      WD30 => d(30), WD31 => d(31), WD32 => d(32), WD33 => d(33), WD34 => d(34),
      WD35 => d(35), WEN => wen, DEPTH0 => depth(0),
      DEPTH1 => depth(1), DEPTH2 => depth(2), DEPTH3 => depth(3),
      WW0 => width(0), WW1 => width(1), WW2 => width(2), WCLK => wclk,
      RDAD0 => ra(0), RDAD1 => ra(1), RDAD2 => ra(2), RDAD3 => ra(3),
      RDAD4 => ra(4), RDAD5 => ra(5), RDAD6 => ra(6), RDAD7 => ra(7),
      RDAD8 => ra(8), RDAD9 => ra(9), RDAD10 => ra(10), RDAD11 => ra(11),
      RDAD12 => ra(12), RDAD13 => ra(13), RDAD14 => ra(14), RDAD15 => ra(15),
      REN => ren, RW0 => width(0), RW1 => width(1), RW2 => width(2),
      RCLK => rclk,
      RD0 => q(0), RD1 => q(1), RD2 => q(2), RD3 => q(3), RD4 => q(4),
      RD5 => q(5), RD6 => q(6), RD7 => q(7), RD8 => q(8), RD9 => q(9),
      RD10 => q(10), RD11 => q(11), RD12 => q(12), RD13 => q(13), RD14 => q(14),
      RD15 => q(15), RD16 => q(16), RD17 => q(17), RD18 => q(18), RD19 => q(19),
      RD20 => q(20), RD21 => q(21), RD22 => q(22), RD23 => q(23), RD24 => q(24),
      RD25 => q(25), RD26 => q(26), RD27 => q(27), RD28 => q(28), RD29 => q(29),
      RD30 => q(30), RD31 => q(31), RD32 => q(32), RD33 => q(33), RD34 => q(34),
      RD35 => q(35));
 
  d(dbits -1 downto 0) <= di;
  do <= q(dbits -1 downto 0);
end;
 
--------------------------------------------------------------------
-- regfile generators
--------------------------------------------------------------------
 
-- integer unit regfile
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.leon_config.all;
use work.leon_iface.all;
use work.tech_generic.all;
entity axcel_regfile_iu is
  generic (
    rftype : integer := 1;
    abits : integer := 8; dbits : integer := 32; words : integer := 128
  );
  port (
    rst      : in std_logic;
    clk      : in std_logic;
    clkn     : in std_logic;
    rfi      : in rf_in_type;
    rfo      : out rf_out_type);
end;
 
architecture rtl of axcel_regfile_iu is
component axcel_ssram
  generic (abits : integer := 16; dbits : integer := 36);
  port (
    wa, ra       : in  std_logic_vector(15 downto 0);
    wclk, rclk   : in  std_logic;
    di           : in  std_logic_vector(dbits -1 downto 0);
    do           : out std_logic_vector(dbits -1 downto 0);
    width        : in  std_logic_vector(2 downto 0);
    ren, wen     : in  std_logic
   );
end component;
signal wen, gnd : std_logic;
signal width : std_logic_vector(2 downto 0);
signal depth : std_logic_vector(4 downto 0);
signal wa, ra1, ra2 : std_logic_vector(15 downto 0);
signal di, q1, qq1, q2, qq2 : std_logic_vector(35 downto 0);
signal ren1, ren2 : std_logic;
constant xbits : integer := 32/(2**(abits-7));
begin
  width <= "101" when abits <= 7 else
           "100" when abits = 8 else
           "011" when abits = 9 else
           "010" when abits = 10 else
           "001" when abits = 11 else
           "000";
 
  wen <= not rfi.wren; gnd <= '0';
  wa(15 downto abits) <= (others =>'0');
  wa(abits-1 downto 0) <= rfi.wraddr(abits-1 downto 0);
  ra1(15 downto abits) <= (others =>'0');
  ra1(abits-1 downto 0) <= rfi.rd1addr(abits-1 downto 0);
  ra2(15 downto abits) <= (others =>'0');
  ra2(abits-1 downto 0) <= rfi.rd2addr(abits-1 downto 0);
  di(35 downto dbits) <= (others =>'0');
  di(dbits-1 downto 0) <= rfi.wrdata(dbits-1 downto 0);
  rfo.data1 <= q1(dbits-1 downto 0);
  rfo.data2 <= q2(dbits-1 downto 0);
  ren1 <= not rfi.ren1;
  ren2 <= not rfi.ren2;
 
  rt1 : if RFIMPTYPE = 1 generate
    a7 : if abits <= 7 generate
      u0 : axcel_ssram
      generic map (abits => abits, dbits => 32)
      port map ( ra => ra1, wa => wa, di => di(31 downto 0), wen => wen,
      width => width, wclk => clkn, ren => ren1, rclk => clkn, do => q1(31 downto 0));
      u1 : axcel_ssram
      generic map (abits => abits, dbits => 32)
      port map ( ra => ra2, wa => wa, di => di(31 downto 0), wen => wen,
      width => width, wclk => clkn, ren => ren2, rclk => clkn, do => q2(31 downto 0));
    end generate;
    a8to12 : if abits > 7 generate
      agen : for i in 0 to (dbits+xbits-1)/xbits-1 generate
        u0 : axcel_ssram
        generic map (abits => abits, dbits => xbits)
        port map ( ra => ra1, wa => wa, di => di(xbits*(i+1)-1 downto xbits*i),
           wen => wen, width => width, wclk => clkn, ren => ren1, rclk => clkn,
           do => q1(xbits*(i+1)-1 downto xbits*i));
        u1 : axcel_ssram
        generic map (abits => abits, dbits => xbits)
        port map ( ra => ra2, wa => wa, di => di(xbits*(i+1)-1 downto xbits*i),
           wen => wen, width => width, wclk => clkn, ren => ren2, rclk => clkn,
           do => q2(xbits*(i+1)-1 downto xbits*i));
      end generate;
    end generate;
  end generate;
 
  rt2 : if RFIMPTYPE = 2 generate
    a7 : if abits <= 7 generate
      u0 : axcel_ssram
      generic map (abits => abits, dbits => 32)
      port map ( ra => ra1, wa => wa, di => di(31 downto 0), wen => wen,
      width => width, wclk => clk, ren => ren1, rclk => clkn, do => q1(31 downto 0));
      u1 : axcel_ssram
      generic map (abits => abits, dbits => 32)
      port map ( ra => ra2, wa => wa, di => di(31 downto 0), wen => wen,
      width => width, wclk => clk, ren => ren2, rclk => clkn, do => q2(31 downto 0));
    end generate;
    a8to12 : if abits > 7 generate
      agen : for i in 0 to (dbits+xbits-1)/xbits-1 generate
        u0 : axcel_ssram
        generic map (abits => abits, dbits => xbits)
        port map ( ra => ra1, wa => wa, di => di(xbits*(i+1)-1 downto xbits*i),
           wen => wen, width => width, wclk => clk, ren => ren1, rclk => clkn,
           do => q1(xbits*(i+1)-1 downto xbits*i));
        u1 : axcel_ssram
        generic map (abits => abits, dbits => xbits)
        port map ( ra => ra2, wa => wa, di => di(xbits*(i+1)-1 downto xbits*i),
           wen => wen, width => width, wclk => clk, ren => ren2, rclk => clkn,
           do => q2(xbits*(i+1)-1 downto xbits*i));
      end generate;
    end generate;
  end generate;
end;
 
-- co-processor regfile
-- synchronous operation without write-through support
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use work.leon_config.all;
use work.leon_iface.all;
entity axcel_regfile_cp is
  generic (
    abits : integer := 4; dbits : integer := 32; words : integer := 16
  );
  port (
    rst      : in std_logic;
    clk      : in std_logic;
    rfi      : in rf_cp_in_type;
    rfo      : out rf_cp_out_type);
end;
 
architecture rtl of axcel_regfile_cp is
component axcel_ssram
  generic (abits : integer := 16; dbits : integer := 36);
  port (
    wa, ra       : in  std_logic_vector(15 downto 0);
    wclk, rclk   : in  std_logic;
    di           : in  std_logic_vector(dbits -1 downto 0);
    do           : out std_logic_vector(dbits -1 downto 0);
    width        : in  std_logic_vector(2 downto 0);
    ren, wen     : in  std_logic
   );
end component;
signal wen, gnd : std_logic;
signal width : std_logic_vector(2 downto 0);
signal wa, ra1, ra2 : std_logic_vector(15 downto 0);
signal di, q1, q2 : std_logic_vector(35 downto 0);
signal ren1, ren2 : std_logic;
begin
 
  width <= "101";
  wen <= not rfi.wren; gnd <= '0';
  wa(15 downto abits) <= (others =>'0');
  wa(abits-1 downto 0) <= rfi.wraddr(abits-1 downto 0);
  ra1(15 downto abits) <= (others =>'0');
  ra1(abits-1 downto 0) <= rfi.rd1addr(abits-1 downto 0);
  ra2(15 downto abits) <= (others =>'0');
  ra2(abits-1 downto 0) <= rfi.rd2addr(abits-1 downto 0);
  di(35 downto dbits) <= (others =>'0');
  di(dbits-1 downto 0) <= rfi.wrdata(dbits-1 downto 0);
  rfo.data1 <= q1(dbits-1 downto 0);
  rfo.data2 <= q2(dbits-1 downto 0);
  ren1 <= not rfi.ren1;
  ren2 <= not rfi.ren2;
 
  u0 : axcel_ssram
  generic map (abits => abits, dbits => 32)
  port map ( ra => ra1, wa => wa, di => di(31 downto 0), wen => wen,
  width => width, wclk => clk, ren => ren1, rclk => clk, do => q1(31 downto 0));
 
  u1 : axcel_ssram
  generic map (abits => abits, dbits => 32)
  port map ( ra => ra2, wa => wa, di => di(31 downto 0), wen => wen,
  width => width, wclk => clk, ren => ren2, rclk => clk, do => q2(31 downto 0));
 
end;
 
LIBRARY ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.leon_config.all;
use work.leon_iface.all;
entity axcel_syncram is
  generic ( abits : integer := 10; dbits : integer := 8 );
  port (
    address  : in std_logic_vector((abits -1) downto 0);
    clk      : in std_logic;
    datain   : in std_logic_vector((dbits -1) downto 0);
    dataout  : out std_logic_vector((dbits -1) downto 0);
    enable   : in std_logic;
    write    : in std_logic
   );
end;
 
architecture rtl of axcel_syncram is
component axcel_ssram
  generic (abits : integer := 16; dbits : integer := 36);
  port (
    wa, ra       : in  std_logic_vector(15 downto 0);
    wclk, rclk   : in  std_logic;
    di           : in  std_logic_vector(dbits -1 downto 0);
    do           : out std_logic_vector(dbits -1 downto 0);
    width        : in  std_logic_vector(2 downto 0);
    ren, wen     : in  std_logic
   );
end component;
 
signal wen, gnd : std_logic;
signal a : std_logic_vector(15 downto 0);
signal d, q : std_logic_vector(35 downto 0);
signal ren  : std_logic;
constant xbits : integer := 32/(2**(abits-7));
signal width : std_logic_vector(2 downto 0);
begin
  width <= "101" when abits <= 7 else
           "100" when abits = 8 else
           "011" when abits = 9 else
           "010" when abits = 10 else
           "001" when abits = 11 else
           "000";
  wen <= not write; gnd <= '0';
  a(15 downto abits) <= (others =>'0');
  a(abits-1 downto 0) <= address(abits-1 downto 0);
  d(35 downto dbits) <= (others =>'0');
  d(dbits-1 downto 0) <= datain(dbits-1 downto 0);
  dataout <= q(dbits-1 downto 0);
  ren <= '0';
 
  a7 : if abits <= 7 generate
    u0 : axcel_ssram
    generic map (abits => abits)
    port map ( ra => a, wa => a, di => d, wen => wen, width => width,
         wclk => clk, ren => ren, rclk => clk, do => q);
  end generate;
  a8to12 : if abits > 7 generate
    agen : for i in 0 to (dbits+xbits-1)/xbits-1 generate
      u0 : axcel_ssram
      generic map (abits => abits, dbits => xbits)
      port map ( ra => a, wa => a, di => d(xbits*(i+1)-1 downto xbits*i),
         wen => wen, width => width, wclk => clk, ren => ren, rclk => clk,
         do => q(xbits*(i+1)-1 downto xbits*i));
    end generate;
  end generate;
end;

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[/] [core_arm/] [trunk/] [vhdl/] [tech/] [tech_axcel.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	tarookumic
2
3
4
5			`----------------------------------------------------------------------------`
6			`-- This file is a part of the LEON VHDL model`
7			`-- Copyright (C) 1999 European Space Agency (ESA)`
8			`--`
9			`-- This library is free software; you can redistribute it and/or`
10			`-- modify it under the terms of the GNU Lesser General Public`
11			`-- License as published by the Free Software Foundation; either`
12			`-- version 2 of the License, or (at your option) any later version.`
13			`--`
14			`-- See the file COPYING.LGPL for the full details of the license.`
15
16
17			`-----------------------------------------------------------------------------`
18			`-- Entity: tech_axcel`
19			`-- File: tech_axcel.vhd`
20			`-- Author: Jiri Gaisler - Gaisler Research`
21			`-- Description: Ram generators for Actel Axcelerator FPGAs`
22			`------------------------------------------------------------------------------`
23
24			`LIBRARY ieee;`
25			`use IEEE.std_logic_1164.all;`
26			`use work.leon_iface.all;`
27			`package tech_axcel is`
28
29			`-- generic sync ram`
30
31			`component axcel_syncram`
32			`generic ( abits : integer := 10; dbits : integer := 8 );`
33			`port (`
34			`address : in std_logic_vector((abits -1) downto 0);`
35			`clk : in std_logic;`
36			`datain : in std_logic_vector((dbits -1) downto 0);`
37			`dataout : out std_logic_vector((dbits -1) downto 0);`
38			`enable : in std_logic;`
39			`write : in std_logic`
40			`);`
41			`end component;`
42
43			`-- regfile generator`
44
45			`component axcel_regfile_iu`
46			`generic (`
47			`rftype : integer := 1;`
48			`abits : integer := 8; dbits : integer := 32; words : integer := 128`
49			`);`
50			`port (`
51			`rst : in std_logic;`
52			`clk : in std_logic;`
53			`clkn : in std_logic;`
54			`rfi : in rf_in_type;`
55			`rfo : out rf_out_type);`
56			`end component;`
57
58			`component axcel_regfile_cp`
59			`generic (`
60			`abits : integer := 4; dbits : integer := 32; words : integer := 16`
61			`);`
62			`port (`
63			`rst : in std_logic;`
64			`clk : in std_logic;`
65			`rfi : in rf_cp_in_type;`
66			`rfo : out rf_cp_out_type);`
67			`end component;`
68
69			`end;`
70
71			`------------------------------------------------------------------`
72			`-- behavioural ram models --------------------------------------------`
73			`------------------------------------------------------------------`
74
75			`-- pragma translate_off`
76
77			`library IEEE;`
78			`use IEEE.std_logic_1164.all;`
79			`use IEEE.std_logic_arith.all;`
80			`use work.tech_generic.all;`
81
82			`entity RAM64K36 is generic (abits : integer := 16); port(`
83			`WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,`
84			`WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,`
85			`WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,`
86			`WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,`
87			`WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,`
88			`RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,`
89			`RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;`
90			`RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,`
91			`RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,`
92			`RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);`
93			`end;`
94
95			`architecture rtl of RAM64K36 is`
96			`signal re : std_logic;`
97			`begin`
98
99			`rp : process(RCLK, WCLK)`
100			`constant words : integer := 2**abits;`
101			`subtype word is std_logic_vector(35 downto 0);`
102			`type dregtype is array (0 to words - 1) of word;`
103			`variable rfd : dregtype;`
104			`variable wa, ra : std_logic_vector(15 downto 0);`
105			`variable q : std_logic_vector(35 downto 0);`
106			`begin`
107			`if rising_edge(WCLK) and (wen = '0') then`
108			`wa := WRAD15 & WRAD14 & WRAD13 & WRAD12 & WRAD11 & WRAD10 & WRAD9 &`
109			`WRAD8 & WRAD7 & WRAD6 & WRAD5 & WRAD4 & WRAD3 & WRAD2 & WRAD1 & WRAD0;`
110			`if not is_x (wa) then`
111			`rfd(conv_integer(unsigned(wa)) mod words) :=`
112			`WD35 & WD34 & WD33 & WD32 & WD31 & WD30 & WD29 & WD28 & WD27 &`
113			`WD26 & WD25 & WD24 & WD23 & WD22 & WD21 & WD20 & WD19 & WD18 &`
114			`WD17 & WD16 & WD15 & WD14 & WD13 & WD12 & WD11 & WD10 & WD9 &`
115			`WD8 & WD7 & WD6 & WD5 & WD4 & WD3 & WD2 & WD1 & WD0;`
116			`end if;`
117			`end if;`
118			`if rising_edge(RCLK) then`
119			`ra := RDAD15 & RDAD14 & RDAD13 & RDAD12 & RDAD11 & RDAD10 & RDAD9 &`
120			`RDAD8 & RDAD7 & RDAD6 & RDAD5 & RDAD4 & RDAD3 & RDAD2 & RDAD1 & RDAD0;`
121			`if not (is_x (ra)) and REN = '0' then`
122			`q := rfd(conv_integer(unsigned(ra)) mod words);`
123			`else q := (others => 'X'); end if;`
124			`end if;`
125			`RD35 <= q(35); RD34 <= q(34); RD33 <= q(33); RD32 <= q(32); RD31 <= q(31);`
126			`RD30 <= q(30); RD29 <= q(29); RD28 <= q(28); RD27 <= q(27); RD26 <= q(26);`
127			`RD25 <= q(25); RD24 <= q(24); RD23 <= q(23); RD22 <= q(22); RD21 <= q(21);`
128			`RD20 <= q(20); RD19 <= q(19); RD18 <= q(18); RD17 <= q(17); RD16 <= q(16);`
129			`RD15 <= q(15); RD14 <= q(14); RD13 <= q(13); RD12 <= q(12); RD11 <= q(11);`
130			`RD10 <= q(10); RD9 <= q(9); RD8 <= q(8); RD7 <= q(7); RD6 <= q(6);`
131			`RD5 <= q(5); RD4 <= q(4); RD3 <= q(3); RD2 <= q(2); RD1 <= q(1);`
132			`RD0 <= q(0);`
133			`end process;`
134			`end;`
135
136			`-- pragma translate_on`
137
138			`--------------------------------------------------------------------`
139			`-- A simpler interface to the syncram`
140			`--------------------------------------------------------------------`
141
142			`LIBRARY ieee;`
143			`use IEEE.std_logic_1164.all;`
144			`use IEEE.std_logic_arith.all;`
145			`use work.leon_config.all;`
146			`use work.leon_iface.all;`
147			`entity axcel_ssram is`
148			`generic (abits : integer := 16; dbits : integer := 36);`
149			`port (`
150			`wa, ra : in std_logic_vector(15 downto 0);`
151			`wclk, rclk : in std_logic;`
152			`di : in std_logic_vector(dbits -1 downto 0);`
153			`do : out std_logic_vector(dbits -1 downto 0);`
154			`width : in std_logic_vector(2 downto 0);`
155			`ren, wen : in std_logic`
156			`);`
157			`end;`
158
159			`architecture rtl of axcel_ssram is`
160			`signal gnd : std_logic;`
161			`component RAM64K36`
162			`-- pragma translate_off`
163			`generic (abits : integer := 16);`
164			`-- pragma translate_on`
165			`port(`
166			`WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,`
167			`WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,`
168			`WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,`
169			`WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,`
170			`WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,`
171			`RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,`
172			`RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;`
173			`RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,`
174			`RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,`
175			`RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);`
176			`end component;`
177			`attribute syn_black_box : boolean;`
178			`attribute syn_black_box of RAM64K36 : component is true;`
179			`attribute syn_tco1 : string;`
180			`attribute syn_tco1 of RAM64K36 : component is`
181			`"RCLK->RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13, RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26, RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 = 4.0";`
182			`signal depth : std_logic_vector(4 downto 0);`
183			`signal d, q : std_logic_vector(36 downto 0);`
184			`begin`
185			`depth <= "00000";`
186			`do <= q(dbits-1 downto 0);`
187			`d(dbits-1 downto 0) <= di;`
188			`d(36 downto dbits) <= (others => '0');`
189			`u0 : RAM64K36`
190			`-- pragma translate_off`
191			`generic map (abits => abits)`
192			`-- pragma translate_on`
193			`port map (`
194			`WRAD0 => wa(0), WRAD1 => wa(1), WRAD2 => wa(2), WRAD3 => wa(3),`
195			`WRAD4 => wa(4), WRAD5 => wa(5), WRAD6 => wa(6), WRAD7 => wa(7),`
196			`WRAD8 => wa(8), WRAD9 => wa(9), WRAD10 => wa(10), WRAD11 => wa(11),`
197			`WRAD12 => wa(12), WRAD13 => wa(13), WRAD14 => wa(14), WRAD15 => wa(15),`
198			`WD0 => d(0), WD1 => d(1), WD2 => d(2), WD3 => d(3), WD4 => d(4),`
199			`WD5 => d(5), WD6 => d(6), WD7 => d(7), WD8 => d(8), WD9 => d(9),`
200			`WD10 => d(10), WD11 => d(11), WD12 => d(12), WD13 => d(13), WD14 => d(14),`
201			`WD15 => d(15), WD16 => d(16), WD17 => d(17), WD18 => d(18), WD19 => d(19),`
202			`WD20 => d(20), WD21 => d(21), WD22 => d(22), WD23 => d(23), WD24 => d(24),`
203			`WD25 => d(25), WD26 => d(26), WD27 => d(27), WD28 => d(28), WD29 => d(29),`
204			`WD30 => d(30), WD31 => d(31), WD32 => d(32), WD33 => d(33), WD34 => d(34),`
205			`WD35 => d(35), WEN => wen, DEPTH0 => depth(0),`
206			`DEPTH1 => depth(1), DEPTH2 => depth(2), DEPTH3 => depth(3),`
207			`WW0 => width(0), WW1 => width(1), WW2 => width(2), WCLK => wclk,`
208			`RDAD0 => ra(0), RDAD1 => ra(1), RDAD2 => ra(2), RDAD3 => ra(3),`
209			`RDAD4 => ra(4), RDAD5 => ra(5), RDAD6 => ra(6), RDAD7 => ra(7),`
210			`RDAD8 => ra(8), RDAD9 => ra(9), RDAD10 => ra(10), RDAD11 => ra(11),`
211			`RDAD12 => ra(12), RDAD13 => ra(13), RDAD14 => ra(14), RDAD15 => ra(15),`
212			`REN => ren, RW0 => width(0), RW1 => width(1), RW2 => width(2),`
213			`RCLK => rclk,`
214			`RD0 => q(0), RD1 => q(1), RD2 => q(2), RD3 => q(3), RD4 => q(4),`
215			`RD5 => q(5), RD6 => q(6), RD7 => q(7), RD8 => q(8), RD9 => q(9),`
216			`RD10 => q(10), RD11 => q(11), RD12 => q(12), RD13 => q(13), RD14 => q(14),`
217			`RD15 => q(15), RD16 => q(16), RD17 => q(17), RD18 => q(18), RD19 => q(19),`
218			`RD20 => q(20), RD21 => q(21), RD22 => q(22), RD23 => q(23), RD24 => q(24),`
219			`RD25 => q(25), RD26 => q(26), RD27 => q(27), RD28 => q(28), RD29 => q(29),`
220			`RD30 => q(30), RD31 => q(31), RD32 => q(32), RD33 => q(33), RD34 => q(34),`
221			`RD35 => q(35));`
222
223			`d(dbits -1 downto 0) <= di;`
224			`do <= q(dbits -1 downto 0);`
225			`end;`
226
227			`--------------------------------------------------------------------`
228			`-- regfile generators`
229			`--------------------------------------------------------------------`
230
231			`-- integer unit regfile`
232			`LIBRARY ieee;`
233			`use IEEE.std_logic_1164.all;`
234			`use work.leon_config.all;`
235			`use work.leon_iface.all;`
236			`use work.tech_generic.all;`
237			`entity axcel_regfile_iu is`
238			`generic (`
239			`rftype : integer := 1;`
240			`abits : integer := 8; dbits : integer := 32; words : integer := 128`
241			`);`
242			`port (`
243			`rst : in std_logic;`
244			`clk : in std_logic;`
245			`clkn : in std_logic;`
246			`rfi : in rf_in_type;`
247			`rfo : out rf_out_type);`
248			`end;`
249
250			`architecture rtl of axcel_regfile_iu is`
251			`component axcel_ssram`
252			`generic (abits : integer := 16; dbits : integer := 36);`
253			`port (`
254			`wa, ra : in std_logic_vector(15 downto 0);`
255			`wclk, rclk : in std_logic;`
256			`di : in std_logic_vector(dbits -1 downto 0);`
257			`do : out std_logic_vector(dbits -1 downto 0);`
258			`width : in std_logic_vector(2 downto 0);`
259			`ren, wen : in std_logic`
260			`);`
261			`end component;`
262			`signal wen, gnd : std_logic;`
263			`signal width : std_logic_vector(2 downto 0);`
264			`signal depth : std_logic_vector(4 downto 0);`
265			`signal wa, ra1, ra2 : std_logic_vector(15 downto 0);`
266			`signal di, q1, qq1, q2, qq2 : std_logic_vector(35 downto 0);`
267			`signal ren1, ren2 : std_logic;`
268			`constant xbits : integer := 32/(2**(abits-7));`
269			`begin`
270			`width <= "101" when abits <= 7 else`
271			`"100" when abits = 8 else`
272			`"011" when abits = 9 else`
273			`"010" when abits = 10 else`
274			`"001" when abits = 11 else`
275			`"000";`
276
277			`wen <= not rfi.wren; gnd <= '0';`
278			`wa(15 downto abits) <= (others =>'0');`
279			`wa(abits-1 downto 0) <= rfi.wraddr(abits-1 downto 0);`
280			`ra1(15 downto abits) <= (others =>'0');`
281			`ra1(abits-1 downto 0) <= rfi.rd1addr(abits-1 downto 0);`
282			`ra2(15 downto abits) <= (others =>'0');`
283			`ra2(abits-1 downto 0) <= rfi.rd2addr(abits-1 downto 0);`
284			`di(35 downto dbits) <= (others =>'0');`
285			`di(dbits-1 downto 0) <= rfi.wrdata(dbits-1 downto 0);`
286			`rfo.data1 <= q1(dbits-1 downto 0);`
287			`rfo.data2 <= q2(dbits-1 downto 0);`
288			`ren1 <= not rfi.ren1;`
289			`ren2 <= not rfi.ren2;`
290
291			`rt1 : if RFIMPTYPE = 1 generate`
292			`a7 : if abits <= 7 generate`
293			`u0 : axcel_ssram`
294			`generic map (abits => abits, dbits => 32)`
295			`port map ( ra => ra1, wa => wa, di => di(31 downto 0), wen => wen,`
296			`width => width, wclk => clkn, ren => ren1, rclk => clkn, do => q1(31 downto 0));`
297			`u1 : axcel_ssram`
298			`generic map (abits => abits, dbits => 32)`
299			`port map ( ra => ra2, wa => wa, di => di(31 downto 0), wen => wen,`
300			`width => width, wclk => clkn, ren => ren2, rclk => clkn, do => q2(31 downto 0));`
301			`end generate;`
302			`a8to12 : if abits > 7 generate`
303			`agen : for i in 0 to (dbits+xbits-1)/xbits-1 generate`
304			`u0 : axcel_ssram`
305			`generic map (abits => abits, dbits => xbits)`
306			`port map ( ra => ra1, wa => wa, di => di(xbits(i+1)-1 downto xbitsi),`
307			`wen => wen, width => width, wclk => clkn, ren => ren1, rclk => clkn,`
308			`do => q1(xbits(i+1)-1 downto xbitsi));`
309			`u1 : axcel_ssram`
310			`generic map (abits => abits, dbits => xbits)`
311			`port map ( ra => ra2, wa => wa, di => di(xbits(i+1)-1 downto xbitsi),`
312			`wen => wen, width => width, wclk => clkn, ren => ren2, rclk => clkn,`
313			`do => q2(xbits(i+1)-1 downto xbitsi));`
314			`end generate;`
315			`end generate;`
316			`end generate;`
317
318			`rt2 : if RFIMPTYPE = 2 generate`
319			`a7 : if abits <= 7 generate`
320			`u0 : axcel_ssram`
321			`generic map (abits => abits, dbits => 32)`
322			`port map ( ra => ra1, wa => wa, di => di(31 downto 0), wen => wen,`
323			`width => width, wclk => clk, ren => ren1, rclk => clkn, do => q1(31 downto 0));`
324			`u1 : axcel_ssram`
325			`generic map (abits => abits, dbits => 32)`
326			`port map ( ra => ra2, wa => wa, di => di(31 downto 0), wen => wen,`
327			`width => width, wclk => clk, ren => ren2, rclk => clkn, do => q2(31 downto 0));`
328			`end generate;`
329			`a8to12 : if abits > 7 generate`
330			`agen : for i in 0 to (dbits+xbits-1)/xbits-1 generate`
331			`u0 : axcel_ssram`
332			`generic map (abits => abits, dbits => xbits)`
333			`port map ( ra => ra1, wa => wa, di => di(xbits(i+1)-1 downto xbitsi),`
334			`wen => wen, width => width, wclk => clk, ren => ren1, rclk => clkn,`
335			`do => q1(xbits(i+1)-1 downto xbitsi));`
336			`u1 : axcel_ssram`
337			`generic map (abits => abits, dbits => xbits)`
338			`port map ( ra => ra2, wa => wa, di => di(xbits(i+1)-1 downto xbitsi),`
339			`wen => wen, width => width, wclk => clk, ren => ren2, rclk => clkn,`
340			`do => q2(xbits(i+1)-1 downto xbitsi));`
341			`end generate;`
342			`end generate;`
343			`end generate;`
344			`end;`
345
346			`-- co-processor regfile`
347			`-- synchronous operation without write-through support`
348			`LIBRARY ieee;`
349			`use IEEE.std_logic_1164.all;`
350			`use work.leon_config.all;`
351			`use work.leon_iface.all;`
352			`entity axcel_regfile_cp is`
353			`generic (`
354			`abits : integer := 4; dbits : integer := 32; words : integer := 16`
355			`);`
356			`port (`
357			`rst : in std_logic;`
358			`clk : in std_logic;`
359			`rfi : in rf_cp_in_type;`
360			`rfo : out rf_cp_out_type);`
361			`end;`
362
363			`architecture rtl of axcel_regfile_cp is`
364			`component axcel_ssram`
365			`generic (abits : integer := 16; dbits : integer := 36);`
366			`port (`
367			`wa, ra : in std_logic_vector(15 downto 0);`
368			`wclk, rclk : in std_logic;`
369			`di : in std_logic_vector(dbits -1 downto 0);`
370			`do : out std_logic_vector(dbits -1 downto 0);`
371			`width : in std_logic_vector(2 downto 0);`
372			`ren, wen : in std_logic`
373			`);`
374			`end component;`
375			`signal wen, gnd : std_logic;`
376			`signal width : std_logic_vector(2 downto 0);`
377			`signal wa, ra1, ra2 : std_logic_vector(15 downto 0);`
378			`signal di, q1, q2 : std_logic_vector(35 downto 0);`
379			`signal ren1, ren2 : std_logic;`
380			`begin`
381
382			`width <= "101";`
383			`wen <= not rfi.wren; gnd <= '0';`
384			`wa(15 downto abits) <= (others =>'0');`
385			`wa(abits-1 downto 0) <= rfi.wraddr(abits-1 downto 0);`
386			`ra1(15 downto abits) <= (others =>'0');`
387			`ra1(abits-1 downto 0) <= rfi.rd1addr(abits-1 downto 0);`
388			`ra2(15 downto abits) <= (others =>'0');`
389			`ra2(abits-1 downto 0) <= rfi.rd2addr(abits-1 downto 0);`
390			`di(35 downto dbits) <= (others =>'0');`
391			`di(dbits-1 downto 0) <= rfi.wrdata(dbits-1 downto 0);`
392			`rfo.data1 <= q1(dbits-1 downto 0);`
393			`rfo.data2 <= q2(dbits-1 downto 0);`
394			`ren1 <= not rfi.ren1;`
395			`ren2 <= not rfi.ren2;`
396
397			`u0 : axcel_ssram`
398			`generic map (abits => abits, dbits => 32)`
399			`port map ( ra => ra1, wa => wa, di => di(31 downto 0), wen => wen,`
400			`width => width, wclk => clk, ren => ren1, rclk => clk, do => q1(31 downto 0));`
401
402			`u1 : axcel_ssram`
403			`generic map (abits => abits, dbits => 32)`
404			`port map ( ra => ra2, wa => wa, di => di(31 downto 0), wen => wen,`
405			`width => width, wclk => clk, ren => ren2, rclk => clk, do => q2(31 downto 0));`
406
407			`end;`
408
409			`LIBRARY ieee;`
410			`use IEEE.std_logic_1164.all;`
411			`use IEEE.std_logic_arith.all;`
412			`use work.leon_config.all;`
413			`use work.leon_iface.all;`
414			`entity axcel_syncram is`
415			`generic ( abits : integer := 10; dbits : integer := 8 );`
416			`port (`
417			`address : in std_logic_vector((abits -1) downto 0);`
418			`clk : in std_logic;`
419			`datain : in std_logic_vector((dbits -1) downto 0);`
420			`dataout : out std_logic_vector((dbits -1) downto 0);`
421			`enable : in std_logic;`
422			`write : in std_logic`
423			`);`
424			`end;`
425
426			`architecture rtl of axcel_syncram is`
427			`component axcel_ssram`
428			`generic (abits : integer := 16; dbits : integer := 36);`
429			`port (`
430			`wa, ra : in std_logic_vector(15 downto 0);`
431			`wclk, rclk : in std_logic;`
432			`di : in std_logic_vector(dbits -1 downto 0);`
433			`do : out std_logic_vector(dbits -1 downto 0);`
434			`width : in std_logic_vector(2 downto 0);`
435			`ren, wen : in std_logic`
436			`);`
437			`end component;`
438
439			`signal wen, gnd : std_logic;`
440			`signal a : std_logic_vector(15 downto 0);`
441			`signal d, q : std_logic_vector(35 downto 0);`
442			`signal ren : std_logic;`
443			`constant xbits : integer := 32/(2**(abits-7));`
444			`signal width : std_logic_vector(2 downto 0);`
445			`begin`
446			`width <= "101" when abits <= 7 else`
447			`"100" when abits = 8 else`
448			`"011" when abits = 9 else`
449			`"010" when abits = 10 else`
450			`"001" when abits = 11 else`
451			`"000";`
452			`wen <= not write; gnd <= '0';`
453			`a(15 downto abits) <= (others =>'0');`
454			`a(abits-1 downto 0) <= address(abits-1 downto 0);`
455			`d(35 downto dbits) <= (others =>'0');`
456			`d(dbits-1 downto 0) <= datain(dbits-1 downto 0);`
457			`dataout <= q(dbits-1 downto 0);`
458			`ren <= '0';`
459
460			`a7 : if abits <= 7 generate`
461			`u0 : axcel_ssram`
462			`generic map (abits => abits)`
463			`port map ( ra => a, wa => a, di => d, wen => wen, width => width,`
464			`wclk => clk, ren => ren, rclk => clk, do => q);`
465			`end generate;`
466			`a8to12 : if abits > 7 generate`
467			`agen : for i in 0 to (dbits+xbits-1)/xbits-1 generate`
468			`u0 : axcel_ssram`
469			`generic map (abits => abits, dbits => xbits)`
470			`port map ( ra => a, wa => a, di => d(xbits(i+1)-1 downto xbitsi),`
471			`wen => wen, width => width, wclk => clk, ren => ren, rclk => clk,`
472			`do => q(xbits(i+1)-1 downto xbitsi));`
473			`end generate;`
474			`end generate;`
475			`end;`