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[/] [core_arm/] [trunk/] [vhdl/] [tech/] [tech_fs90.vhd] - Blame information for rev 5

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1 2 tarookumic 
 
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5 
----------------------------------------------------------------------------
6 
--  This file is a part of the LEON VHDL model
7 
--  Copyright (C) 1999  European Space Agency (ESA)
8 
--
9 
--  This library is free software; you can redistribute it and/or
10 
--  modify it under the terms of the GNU Lesser General Public
11 
--  License as published by the Free Software Foundation; either
12 
--  version 2 of the License, or (at your option) any later version.
13 
--
14 
--  See the file COPYING.LGPL for the full details of the license.
15 
 
16 
 
17 
-----------------------------------------------------------------------------
18 
-- Entity:      tech_fs90
19 
-- File:        tech_fs90.vhd
20 
-- Author:      Jiri Gaisler - Gaisler Research
21 
-- Description: Contains UMC (Farraday Technology) FS90A/B specific pads and
22 
--              ram generators
23 
------------------------------------------------------------------------------
24 
 
25 
LIBRARY ieee;
26 
use IEEE.std_logic_1164.all;
27 
use work.leon_iface.all;
28 
 
29 
package tech_fs90 is
30 
 
31 
-- sync ram generator
32 
 
33 
  component fs90_syncram
34 
  generic ( abits : integer := 10; dbits : integer := 8 );
35 
  port (
36 
    address  : in std_logic_vector(abits -1 downto 0);
37 
    clk      : in std_logic;
38 
    datain   : in std_logic_vector(dbits -1 downto 0);
39 
    dataout  : out std_logic_vector(dbits -1 downto 0);
40 
    enable   : in std_logic;
41 
    write    : in std_logic);
42 
  end component;
43 
 
44 
-- regfile generator
45 
 
46 
  component fs90_regfile
47 
  generic ( abits : integer := 8; dbits : integer := 32; words : integer := 128);
48 
  port (
49 
    rst      : in std_logic;
50 
    clk      : in clk_type;
51 
    clkn     : in clk_type;
52 
    rfi      : in rf_in_type;
53 
    rfo      : out rf_out_type);
54 
  end component;
55 
 
56 
-- pads
57 
 
58 
  component fs90_inpad
59 
    port (pad : in std_logic; q : out std_logic); end component;
60 
  component fs90_smpad
61 
    port (pad : in std_logic; q : out std_logic);
62 
  end component;
63 
  component fs90_outpad
64 
    generic (drive : integer := 1);
65 
    port (d : in  std_logic; pad : out  std_logic);
66 
  end component;
67 
  component fs90_toutpadu
68 
    generic (drive : integer := 1);
69 
    port (d, en : in  std_logic; pad : out  std_logic);
70 
  end component;
71 
  component fs90_iopad
72 
    generic (drive : integer := 1);
73 
    port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
74 
  end component;
75 
  component fs90_smiopad
76 
    generic (drive : integer := 1);
77 
    port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
78 
  end component;
79 
  component fs90_iopadu
80 
    generic (drive : integer := 1);
81 
    port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
82 
  end component;
83 
  component fs90_iodpad
84 
    generic (drive : integer := 1);
85 
    port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
86 
  end component;
87 
  component fs90_odpad
88 
    generic (drive : integer := 1);
89 
    port ( d : in std_logic; pad : out std_logic);
90 
  end component;
91 
 
92 
end;
93 
 
94 
------------------------------------------------------------------
95 
-- behavioural pad models --------------------------------------------
96 
------------------------------------------------------------------
97 
-- Only needed for simulation, not synthesis.
98 
-- pragma translate_off
99 
 
100 
-- input pad
101 
library IEEE;
102 
use IEEE.std_logic_1164.all;
103 
entity uyfaa is port (
104 
  o   : out std_logic;
105 
  i   : in std_logic;
106 
  pu  : in std_logic;
107 
  pd  : in std_logic;
108 
  smt : in std_logic);
109 
end;
110 
architecture rtl of uyfaa is
111 
signal inode : std_logic;
112 
begin
113 
  inode <= to_x01(i) after 1 ns;
114 
  inode <= 'H' when pu = '1' else 'L' when pd = '1' else 'Z';
115 
  o <= to_x01(inode);
116 
end;
117 
 
118 
-- output pad
119 
library IEEE;
120 
use IEEE.std_logic_1164.all;
121 
entity vyfa2gsa is port (
122 
  o   : out  std_logic;
123 
  i   : in  std_logic;
124 
  e   : in  std_logic;
125 
  e2  : in  std_logic;
126 
  e4  : in  std_logic;
127 
  e8  : in  std_logic;
128 
  sr  : in  std_logic);
129 
end;
130 
architecture rtl of vyfa2gsa is begin
131 
  o <= to_x01(i) after 2 ns when e = '1' else 'Z' after 2 ns;
132 
end;
133 
 
134 
-- bidirectional pad
135 
library IEEE;
136 
use IEEE.std_logic_1164.all;
137 
entity wyfa2gsa is port (
138 
  o   : out  std_logic;
139 
  i   : in  std_logic;
140 
  io  : inout  std_logic;
141 
  e   : in  std_logic;
142 
  e2  : in  std_logic;
143 
  e4  : in  std_logic;
144 
  e8  : in  std_logic;
145 
  sr  : in  std_logic;
146 
  pu  : in std_logic;
147 
  pd  : in std_logic;
148 
  smt : in std_logic);
149 
end;
150 
architecture rtl of wyfa2gsa is begin
151 
  io <= to_x01(i) after 2 ns when e = '1' else 'Z' after 2 ns;
152 
  io <= 'H' when pu = '1' else 'L' when pd = '1' else 'Z';
153 
  o <= to_x01(io);
154 
end;
155 
 
156 
------------------------------------------------------------------
157 
-- behavioural ram models ----------------------------------------
158 
------------------------------------------------------------------
159 
-- synchronous ram
160 
library ieee;
161 
use ieee.std_logic_1164.all;
162 
use ieee.std_logic_arith.all;
163 
use work.leon_iface.all;
164 
 
165 
entity fs90_syncram_sim is
166 
  generic ( abits : integer := 10; dbits : integer := 8 );
167 
  port (
168 
    address  : in std_logic_vector((abits -1) downto 0);
169 
    clk      : in std_logic;
170 
    datain   : in std_logic_vector((dbits -1) downto 0);
171 
    dataout  : out std_logic_vector((dbits -1) downto 0);
172 
    cselect  : in std_logic;
173 
    oenable  : in std_logic;
174 
    write    : in std_logic
175 
  );
176 
end;
177 
 
178 
architecture behavioral of fs90_syncram_sim is
179 
  type mem is array(0 to (2**abits -1))
180 
        of std_logic_vector((dbits -1) downto 0);
181 
  signal memarr : mem;
182 
begin
183 
  main : process(clk, memarr)
184 
  variable do  : std_logic_vector((dbits -1) downto 0);
185 
  begin
186 
    if rising_edge(clk) then
187 
      do := (others => 'X');
188 
      if cselect = '1' then
189 
        if (write = '0') and not is_x(address) then
190 
          memarr(conv_integer(unsigned(address))) <= datain;
191 
        end if;
192 
        if (write = '1') and not is_x(address) then
193 
          do := memarr(conv_integer(unsigned(address)));
194 
        end if;
195 
      end if;
196 
      if oenable = '1' then dataout <= do; else dataout <= (others => 'Z'); end if;
197 
    end if;
198 
  end process;
199 
end;
200 
 
201 
--  2-port ram
202 
LIBRARY ieee;
203 
use IEEE.std_logic_1164.all;
204 
use IEEE.std_logic_arith.all;
205 
 
206 
entity fs90_dpram_ss is
207 
  generic (
208 
    abits : integer := 8;
209 
    dbits : integer := 32;
210 
    words : integer := 256
211 
  );
212 
  port (
213 
    data: in std_logic_vector (dbits -1 downto 0);
214 
    rdaddress: in std_logic_vector (abits -1 downto 0);
215 
    wraddress: in std_logic_vector (abits -1 downto 0);
216 
    wren : in std_logic;
217 
    clka, clkb : in std_logic;
218 
    sela, selb : in std_logic;
219 
    oe : in std_logic;
220 
    q: out std_logic_vector (dbits -1 downto 0)
221 
  );
222 
end;
223 
 
224 
architecture behav of fs90_dpram_ss is
225 
  type mem is array(0 to (2**abits -1))
226 
        of std_logic_vector((dbits -1) downto 0);
227 
  signal memarr : mem;
228 
begin
229 
  main : process(clka, clkb, memarr)
230 
  variable do  : std_logic_vector((dbits -1) downto 0);
231 
  begin
232 
    if rising_edge(clka) then
233 
      do := (others => 'X');
234 
      if sela = '1' then
235 
        if ((wren = '1') or (rdaddress /= wraddress)) and not is_x(rdaddress)
236 
        then do := memarr(conv_integer(unsigned(rdaddress))); end if;
237 
      end if;
238 
      if oe = '1' then q <= do; else q <= (others => 'Z'); end if;
239 
    end if;
240 
    if rising_edge(clkb) then
241 
      if (selb = '1') and (wren = '0') and not is_x(wraddress) then
242 
        memarr(conv_integer(unsigned(wraddress))) <= data;
243 
      end if;
244 
    end if;
245 
  end process;
246 
end;
247 
 
248 
LIBRARY ieee;
249 
use IEEE.std_logic_1164.all;
250 
package tech_fs90_sim is
251 
 
252 
component fs90_syncram_sim
253 
  generic ( abits : integer := 10; dbits : integer := 8 );
254 
  port (
255 
    address  : in std_logic_vector((abits -1) downto 0);
256 
    clk      : in std_logic;
257 
    datain   : in std_logic_vector((dbits -1) downto 0);
258 
    dataout  : out std_logic_vector((dbits -1) downto 0);
259 
    cselect  : in std_logic;
260 
    oenable  : in std_logic;
261 
    write    : in std_logic
262 
  );
263 
end component;
264 
 
265 
component fs90_dpram_ss
266 
  generic (
267 
    abits : integer := 8;
268 
    dbits : integer := 32;
269 
    words : integer := 256
270 
  );
271 
  port (
272 
    data: in std_logic_vector (dbits -1 downto 0);
273 
    rdaddress: in std_logic_vector (abits -1 downto 0);
274 
    wraddress: in std_logic_vector (abits -1 downto 0);
275 
    wren : in std_logic;
276 
    clka, clkb : in std_logic;
277 
    sela, selb : in std_logic;
278 
    oe : in std_logic;
279 
    q: out std_logic_vector (dbits -1 downto 0)
280 
  );
281 
end component;
282 
 
283 
end;
284 
 
285 
-- Syncronous SRAM
286 
-- Address, control and data signals latched on rising CK.
287 
-- Write enable (WEB) active low.
288 
 
289 
library ieee;
290 
use IEEE.std_logic_1164.all;
291 
use work.tech_fs90_sim.all;
292 
 
293 
entity SA108019 is      -- 128x25
294 
   port (A0, A1, A2, A3, A4, A5, A6, DI0, DI1, DI2, DI3, DI4, DI5,
295 
         DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16,
296 
         DI17, DI18, DI19, DI20, DI21, DI22, DI23, DI24, CK, CS, OE,
297 
         WEB : in std_logic;
298 
         DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10,
299 
         DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21,
300 
         DO22, DO23, DO24: out std_logic
301 
        );
302 
end;
303 
 
304 
architecture behavioral of SA108019 is
305 
signal din, dout : std_logic_vector(24 downto 0);
306 
signal addr : std_logic_vector(6 downto 0);
307 
begin
308 
  addr <= a6&a5&a4&a3&a2&a1&a0;
309 
  din  <= di24&di23&di22&di21&di20&di19&di18&di17&di16&di15&di14&di13&di12&
310 
          di11&di10&di9&di8&di7&di6&di5&di4&di3&di2&di1&di0;
311 
  do24 <= dout(24); do23 <= dout(23); do22 <= dout(22); do21 <= dout(21);
312 
  do20 <= dout(20); do19 <= dout(19); do18 <= dout(18); do17 <= dout(17);
313 
  do16 <= dout(16); do15 <= dout(15); do14 <= dout(14); do13 <= dout(13);
314 
  do12 <= dout(12); do11 <= dout(11); do10 <= dout(10); do9 <= dout(9);
315 
  do8 <= dout(8); do7 <= dout(7); do6 <= dout(6); do5 <= dout(5);
316 
  do4 <= dout(4); do3 <= dout(3); do2 <= dout(2); do1 <= dout(1);
317 
  do0 <= dout(0);
318 
  syncram0 : fs90_syncram_sim generic map ( abits => 7, dbits => 25)
319 
    port map ( addr, ck, din, dout, cs, oe, web);
320 
end behavioral;
321 
 
322 
library ieee;
323 
use IEEE.std_logic_1164.all;
324 
use work.tech_fs90_sim.all;
325 
 
326 
entity SU004020 is -- 512x32
327 
   port (A0, A1, A2, A3, A4, A5, A6, A7, A8, DI0, DI1, DI2, DI3, DI4, DI5,
328 
         DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16,
329 
         DI17, DI18, DI19, DI20, DI21, DI22, DI23, DI24, DI25, DI26, DI27,
330 
         DI28, DI29, DI30, DI31, CK, CS, OE, WEB : in std_logic;
331 
         DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10,
332 
         DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21,
333 
         DO22, DO23, DO24, DO25, DO26, DO27, DO28, DO29, DO30, DO31: out std_logic
334 
        );
335 
end;
336 
 
337 
architecture behavioral of SU004020 is
338 
signal din, dout : std_logic_vector(31 downto 0);
339 
signal addr : std_logic_vector(8 downto 0);
340 
begin
341 
  addr <= a8&a7&a6&a5&a4&a3&a2&a1&a0;
342 
  din  <= di31&di30&di29&di28&di27&di26&di25&di24&di23&di22&di21&di20&di19&
343 
          di18&di17&di16&di15&di14&di13&di12&di11&di10&di9&di8&di7&di6&di5&
344 
          di4&di3&di2&di1&di0;
345 
  do31 <= dout(31); do30 <= dout(30); do29 <= dout(29); do28 <= dout(28);
346 
  do27 <= dout(27); do26 <= dout(26); do25 <= dout(25); do24 <= dout(24);
347 
  do23 <= dout(23); do22 <= dout(22); do21 <= dout(21); do20 <= dout(20);
348 
  do19 <= dout(19); do18 <= dout(18); do17 <= dout(17); do16 <= dout(16);
349 
  do15 <= dout(15); do14 <= dout(14); do13 <= dout(13); do12 <= dout(12);
350 
  do11 <= dout(11); do10 <= dout(10); do9 <= dout(9); do8 <= dout(8);
351 
  do7 <= dout(7); do6 <= dout(6); do5 <= dout(5); do4 <= dout(4);
352 
  do3 <= dout(3); do2 <= dout(2); do1 <= dout(1); do0 <= dout(0);
353 
  syncram0 : fs90_syncram_sim generic map ( abits => 9, dbits => 32)
354 
    port map ( addr, ck, din, dout, cs, oe, web);
355 
end behavioral;
356 
 
357 
 
358 
library ieee;
359 
use IEEE.std_logic_1164.all;
360 
use work.tech_fs90_sim.all;
361 
entity SW204420 is
362 
   port (A0, A1, A2, A3, A4, A5, A6, A7, B0, B1, B2, B3, B4, B5, B6,
363 
         B7, DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10,
364 
         DI11, DI12, DI13, DI14, DI15, DI16, DI17, DI18, DI19, DI20, DI21,
365 
         DI22, DI23, DI24, DI25, DI26, DI27, DI28, DI29, DI30, DI31,
366 
         CKA, CKB, CSA, CSB, OE,
367 
         WEB : in std_logic;
368 
         DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10,
369 
         DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21,
370 
         DO22, DO23, DO24, DO25, DO26, DO27, DO28, DO29, DO30, DO31: out std_logic
371 
        );
372 
end;
373 
architecture behavioral of SW204420 is
374 
signal din, dout : std_logic_vector(31 downto 0);
375 
signal addra, addrb : std_logic_vector(7 downto 0);
376 
begin
377 
  addra <= a7&a6&a5&a4&a3&a2&a1&a0;
378 
  addrb <= b7&b6&b5&b4&b3&b2&b1&b0;
379 
  din  <= di31&di30&di29&di28&di27&di26&di25&di24&di23&di22&di21&di20&di19&
380 
          di18&di17&di16&di15&di14&di13&di12&di11&di10&di9&di8&di7&di6&di5&
381 
          di4&di3&di2&di1&di0;
382 
  do31 <= dout(31); do30 <= dout(30); do29 <= dout(29); do28 <= dout(28);
383 
  do27 <= dout(27); do26 <= dout(26); do25 <= dout(25); do24 <= dout(24);
384 
  do23 <= dout(23); do22 <= dout(22); do21 <= dout(21); do20 <= dout(20);
385 
  do19 <= dout(19); do18 <= dout(18); do17 <= dout(17); do16 <= dout(16);
386 
  do15 <= dout(15); do14 <= dout(14); do13 <= dout(13); do12 <= dout(12);
387 
  do11 <= dout(11); do10 <= dout(10); do9 <= dout(9); do8 <= dout(8);
388 
  do7 <= dout(7); do6 <= dout(6); do5 <= dout(5); do4 <= dout(4);
389 
  do3 <= dout(3); do2 <= dout(2); do1 <= dout(1); do0 <= dout(0);
390 
  dpram0 : fs90_dpram_ss generic map ( abits => 8, dbits => 32)
391 
    port map ( din, addra, addrb, web, cka, ckb, csa, csb, oe, dout);
392 
end;
393 
 
394 
-- pragma translate_on
395 
 
396 
-- component declarations from true tech library
397 
LIBRARY ieee;
398 
use IEEE.std_logic_1164.all;
399 
package tech_fs90_syn is
400 
-- 128x25 sync ram
401 
component SA108019
402 
   port (A0, A1, A2, A3, A4, A5, A6, DI0, DI1, DI2, DI3, DI4, DI5,
403 
         DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16,
404 
         DI17, DI18, DI19, DI20, DI21, DI22, DI23, DI24, CK, CS, OE,
405 
         WEB : in std_logic;
406 
         DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10,
407 
         DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21,
408 
         DO22, DO23, DO24: out std_logic
409 
        );
410 
end component;
411 
-- 512x32 sync ram
412 
component SU004020
413 
   port (A0, A1, A2, A3, A4, A5, A6, A7, A8, DI0, DI1, DI2, DI3, DI4, DI5,
414 
         DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16,
415 
         DI17, DI18, DI19, DI20, DI21, DI22, DI23, DI24, DI25, DI26, DI27,
416 
         DI28, DI29, DI30, DI31, CK, CS, OE, WEB : in std_logic;
417 
         DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10,
418 
         DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21,
419 
         DO22, DO23, DO24, DO25, DO26, DO27, DO28, DO29, DO30, DO31: out std_logic
420 
        );
421 
end component;
422 
-- 2-port sync ram
423 
component SW204420
424 
   port (A0, A1, A2, A3, A4, A5, A6, A7, B0, B1, B2, B3, B4, B5, B6,
425 
         B7, DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10,
426 
         DI11, DI12, DI13, DI14, DI15, DI16, DI17, DI18, DI19, DI20, DI21,
427 
         DI22, DI23, DI24, DI25, DI26, DI27, DI28, DI29, DI30, DI31,
428 
         CKA, CKB, CSA, CSB, OE,
429 
         WEB : in std_logic;
430 
         DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10,
431 
         DO11, DO12, DO13, DO14, DO15, DO16, DO17, DO18, DO19, DO20, DO21,
432 
         DO22, DO23, DO24, DO25, DO26, DO27, DO28, DO29, DO30, DO31: out std_logic
433 
        );
434 
end component;
435 
 
436 
-- in-pad
437 
component uyfaa port (
438 
  o   : out std_logic;
439 
  i   : in std_logic;
440 
  pu  : in std_logic;
441 
  pd  : in std_logic;
442 
  smt : in std_logic);
443 
end component;
444 
-- out-pad
445 
component vyfa2gsa port (
446 
  o   : out  std_logic;
447 
  i   : in  std_logic;
448 
  e   : in  std_logic;
449 
  e2  : in  std_logic;
450 
  e4  : in  std_logic;
451 
  e8  : in  std_logic;
452 
  sr  : in  std_logic);
453 
end component;
454 
-- io-pad
455 
component wyfa2gsa port (
456 
  o   : out  std_logic;
457 
  i   : in  std_logic;
458 
  io  : inout  std_logic;
459 
  e   : in  std_logic;
460 
  e2  : in  std_logic;
461 
  e4  : in  std_logic;
462 
  e8  : in  std_logic;
463 
  sr  : in  std_logic;
464 
  pu  : in std_logic;
465 
  pd  : in std_logic;
466 
  smt : in std_logic);
467 
end component;
468 
 
469 
end;
470 
 
471 
------------------------------------------------------------------
472 
-- sync ram generator --------------------------------------------
473 
------------------------------------------------------------------
474 
 
475 
library IEEE;
476 
use IEEE.std_logic_1164.all;
477 
use work.tech_fs90_syn.all;
478 
 
479 
entity fs90_syncram is
480 
  generic ( abits : integer := 10; dbits : integer := 8 );
481 
  port (
482 
    address  : in std_logic_vector(abits -1 downto 0);
483 
    clk      : in std_logic;
484 
    datain   : in std_logic_vector(dbits -1 downto 0);
485 
    dataout  : out std_logic_vector(dbits -1 downto 0);
486 
    enable  : in std_logic;
487 
    write    : in std_logic
488 
  );
489 
end;
490 
 
491 
architecture rtl of fs90_syncram is
492 
  signal wr   : std_logic;
493 
  signal a    : std_logic_vector(19 downto 0);
494 
  signal d, o : std_logic_vector(34 downto 0);
495 
  constant synopsys_bug : std_logic_vector(37 downto 0) := (others => '0');
496 
  signal we, vcc : std_logic;
497 
begin
498 
 
499 
  vcc <= '1';
500 
  wr <= not write;
501 
  a(abits -1 downto 0) <= address;
502 
  a(abits+1 downto abits) <= synopsys_bug(abits+1 downto abits);
503 
  d(dbits -1 downto 0) <= datain;
504 
  d(dbits+1 downto dbits) <= synopsys_bug(dbits+1 downto dbits);
505 
 
506 
  dataout <= o(dbits -1 downto 0);
507 
 
508 
  a7d25 : if (abits <= 7) and (dbits <= 25) generate
509 
    id0 : SA108019 port map (
510 
      a(0), a(1), a(2), a(3), a(4), a(5), a(6),
511 
      d(0), d(1), d(2), d(3), d(4), d(5), d(6), d(7), d(8),
512 
      d(9), d(10), d(11), d(12), d(13), d(14), d(15), d(16),
513 
      d(17), d(18), d(19), d(20), d(21), d(22), d(23), d(24),
514 
      clk, enable, vcc, wr,
515 
      o(0), o(1), o(2), o(3), o(4), o(5), o(6), o(7), o(8),
516 
      o(9), o(10), o(11), o(12), o(13), o(14), o(15), o(16),
517 
      o(17), o(18), o(19), o(20), o(21), o(22), o(23), o(24));
518 
  end generate;
519 
  a9d32 : if (abits = 9) and (dbits = 32) generate
520 
    id0 : SU004020 port map (
521 
      a(0), a(1), a(2), a(3), a(4), a(5), a(6), a(7), a(8),
522 
      d(0), d(1), d(2), d(3), d(4), d(5), d(6), d(7), d(8),
523 
      d(9), d(10), d(11), d(12), d(13), d(14), d(15), d(16),
524 
      d(17), d(18), d(19), d(20), d(21), d(22), d(23), d(24),
525 
      d(25), d(26), d(27), d(28), d(29), d(30), d(31),
526 
      clk, enable, vcc, wr,
527 
      o(0), o(1), o(2), o(3), o(4), o(5), o(6), o(7), o(8),
528 
      o(9), o(10), o(11), o(12), o(13), o(14), o(15), o(16),
529 
      o(17), o(18), o(19), o(20), o(21), o(22), o(23), o(24),
530 
      o(25), o(26), o(27), o(28), o(29), o(30), o(31));
531 
  end generate;
532 
end rtl;
533 
 
534 
------------------------------------------------------------------
535 
-- regfile generator  --------------------------------------------
536 
------------------------------------------------------------------
537 
 
538 
LIBRARY ieee;
539 
use IEEE.std_logic_1164.all;
540 
use IEEE.std_logic_arith.all;
541 
use work.leon_config.all;
542 
use work.leon_iface.all;
543 
use work.tech_fs90_syn.all;
544 
 
545 
entity fs90_regfile is
546 
  generic (
547 
    abits : integer := 8;
548 
    dbits : integer := 32;
549 
    words : integer := 128
550 
  );
551 
  port (
552 
    rst      : in std_logic;
553 
    clk      : in clk_type;
554 
    clkn     : in clk_type;
555 
    rfi      : in rf_in_type;
556 
    rfo      : out rf_out_type);
557 
end;
558 
 
559 
architecture rtl of fs90_regfile is
560 
signal d, q1, q2 : std_logic_vector(39 downto 0);
561 
signal vcc, wen : std_logic;
562 
signal ra1, ra2, wa : std_logic_vector(12 downto 0);
563 
begin
564 
  wen <= not rfi.wren; vcc <= '1';
565 
  ra1(abits-1 downto 0) <= rfi.rd1addr;
566 
  ra1(12 downto abits) <= (others => '0');
567 
  ra2(abits-1 downto 0) <= rfi.rd2addr;
568 
  ra2(12 downto abits) <= (others => '0');
569 
  wa(abits-1 downto 0) <= rfi.wraddr;
570 
  wa(12 downto abits) <= (others => '0');
571 
  rfo.data1 <= q1(dbits-1 downto 0);
572 
  rfo.data2 <= q2(dbits-1 downto 0);
573 
  d(RDBITS-1 downto 0) <= rfi.wrdata;
574 
 
575 
  dp136x32 : if (words = 136) and (dbits = 32) generate
576 
    u0: SW204420 port map (
577 
      ra1(0), ra1(1), ra1(2), ra1(3), ra1(4), ra1(5), ra1(6), ra1(7),
578 
      wa(0), wa(1), wa(2), wa(3), wa(4), wa(5), wa(6), wa(7),
579 
      d(0), d(1), d(2), d(3), d(4), d(5), d(6), d(7), d(8),
580 
      d(9), d(10), d(11), d(12), d(13), d(14), d(15), d(16),
581 
      d(17), d(18), d(19), d(20), d(21), d(22), d(23), d(24),
582 
      d(25), d(26), d(27), d(28), d(29), d(30), d(31),
583 
 
584 
      clkn, clkn, rfi.ren1, rfi.wren, vcc, wen,
585 
 
586 
      q1(0), q1(1), q1(2), q1(3), q1(4), q1(5), q1(6), q1(7), q1(8),
587 
      q1(9), q1(10), q1(11), q1(12), q1(13), q1(14), q1(15), q1(16),
588 
      q1(17), q1(18), q1(19), q1(20), q1(21), q1(22), q1(23), q1(24),
589 
      q1(25), q1(26), q1(27), q1(28), q1(29), q1(30), q1(31));
590 
    u1: SW204420 port map (
591 
      ra2(0), ra2(1), ra2(2), ra2(3), ra2(4), ra2(5), ra2(6), ra2(7),
592 
      wa(0), wa(1), wa(2), wa(3), wa(4), wa(5), wa(6), wa(7),
593 
      d(0), d(1), d(2), d(3), d(4), d(5), d(6), d(7), d(8),
594 
      d(9), d(10), d(11), d(12), d(13), d(14), d(15), d(16),
595 
      d(17), d(18), d(19), d(20), d(21), d(22), d(23), d(24),
596 
      d(25), d(26), d(27), d(28), d(29), d(30), d(31),
597 
 
598 
      clkn, clkn, rfi.ren2, rfi.wren, vcc, wen,
599 
 
600 
      q2(0), q2(1), q2(2), q2(3), q2(4), q2(5), q2(6), q2(7), q2(8),
601 
      q2(9), q2(10), q2(11), q2(12), q2(13), q2(14), q2(15), q2(16),
602 
      q2(17), q2(18), q2(19), q2(20), q2(21), q2(22), q2(23), q2(24),
603 
      q2(25), q2(26), q2(27), q2(28), q2(29), q2(30), q2(31));
604 
  end generate;
605 
 
606 
end;
607 
 
608 
------------------------------------------------------------------
609 
-- mapping generic pads on tech pads ---------------------------------
610 
------------------------------------------------------------------
611 
 
612 
-- input pad
613 
library IEEE;
614 
use IEEE.std_logic_1164.all;
615 
use work.tech_fs90_syn.all;
616 
entity fs90_inpad is
617 
  port (pad : in std_logic; q : out std_logic);
618 
end;
619 
architecture syn of fs90_inpad is
620 
signal gnd : std_logic;
621 
begin
622 
  gnd <= '0';
623 
  i0 : uyfaa port map (q, pad, gnd, gnd, gnd);
624 
end;
625 
 
626 
-- input schmitt pad
627 
library IEEE;
628 
use IEEE.std_logic_1164.all;
629 
use work.tech_fs90_syn.all;
630 
entity fs90_smpad is port (pad : in std_logic; q : out std_logic); end;
631 
architecture syn of fs90_smpad is
632 
signal gnd, vcc : std_logic;
633 
begin
634 
  gnd <= '0'; vcc <= '1';
635 
  i0 : uyfaa port map (q, pad, gnd, gnd, vcc);
636 
end;
637 
 
638 
-- output pads
639 
library IEEE;
640 
use IEEE.std_logic_1164.all;
641 
use work.tech_fs90_syn.all;
642 
entity fs90_outpad is
643 
  generic (drive : integer := 1);
644 
  port (d : in std_logic; pad : out std_logic);
645 
end;
646 
architecture syn of fs90_outpad is
647 
signal gnd, vcc : std_logic;
648 
begin
649 
  gnd <= '0'; vcc <= '1';
650 
  d1 : if drive = 1 generate
651 
    u0 : vyfa2gsa port map (pad, d, vcc, vcc, gnd, gnd, gnd);
652 
  end generate;
653 
  d2 : if drive = 2 generate
654 
    u0 : vyfa2gsa port map (pad, d, vcc, gnd, vcc, gnd, gnd);
655 
  end generate;
656 
  d3 : if drive = 3 generate
657 
    u0 : vyfa2gsa port map (pad, d, vcc, gnd, gnd, vcc, gnd);
658 
  end generate;
659 
  d4 : if drive > 3 generate
660 
    u0 : vyfa2gsa port map (pad, d, vcc, gnd, vcc, vcc, gnd);
661 
  end generate;
662 
end;
663 
 
664 
-- tri-state output pads with pull-up
665 
library IEEE;
666 
use IEEE.std_logic_1164.all;
667 
use work.tech_fs90_syn.all;
668 
entity fs90_toutpadu is
669 
  generic (drive : integer := 1);
670 
  port (d, en : in  std_logic; pad : out  std_logic);
671 
end;
672 
architecture syn of fs90_toutpadu is
673 
signal gnd, vcc, q, ipad, eni : std_logic;
674 
begin
675 
  gnd <= '0'; vcc <= '1'; pad <= ipad; eni <= not en;
676 
  d1 : if drive = 1 generate
677 
    u0 : wyfa2gsa port map (q, d, ipad, eni, vcc, gnd, gnd, gnd, vcc, gnd, gnd);
678 
  end generate;
679 
  d2 : if drive = 2 generate
680 
    u0 : wyfa2gsa port map (q, d, ipad, eni, gnd, vcc, gnd, gnd, vcc, gnd, gnd);
681 
  end generate;
682 
  d3 : if drive = 3 generate
683 
    u0 : wyfa2gsa port map (q, d, ipad, eni, gnd, gnd, vcc, gnd, vcc, gnd, gnd);
684 
  end generate;
685 
  d4 : if drive > 3 generate
686 
    u0 : wyfa2gsa port map (q, d, ipad, eni, gnd, vcc, vcc, gnd, vcc, gnd, gnd);
687 
  end generate;
688 
end;
689 
 
690 
-- bidirectional pad
691 
library IEEE;
692 
use IEEE.std_logic_1164.all;
693 
use work.tech_fs90_syn.all;
694 
entity fs90_iopad is
695 
  generic (drive : integer := 1);
696 
  port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
697 
end;
698 
architecture syn of fs90_iopad is
699 
signal gnd, vcc, eni : std_logic;
700 
begin
701 
  gnd <= '0'; vcc <= '1'; eni <= not en;
702 
  d1 : if drive = 1 generate
703 
    u0 : wyfa2gsa port map (q, d, pad, eni, vcc, gnd, gnd, gnd, gnd, gnd, gnd);
704 
  end generate;
705 
  d2 : if drive = 2 generate
706 
    u0 : wyfa2gsa port map (q, d, pad, eni, gnd, vcc, gnd, gnd, gnd, gnd, gnd);
707 
  end generate;
708 
  d3 : if drive = 3 generate
709 
    u0 : wyfa2gsa port map (q, d, pad, eni, gnd, gnd, vcc, gnd, gnd, gnd, gnd);
710 
  end generate;
711 
  d4 : if drive > 3 generate
712 
    u0 : wyfa2gsa port map (q, d, pad, eni, gnd, vcc, vcc, gnd, gnd, gnd, gnd);
713 
  end generate;
714 
end;
715 
 
716 
-- bidirectional schmitt pad
717 
library IEEE;
718 
use IEEE.std_logic_1164.all;
719 
use work.tech_fs90_syn.all;
720 
entity fs90_smiopad is
721 
  generic (drive : integer := 1);
722 
  port ( d, en : in std_logic; q : out std_logic; pad : inout std_logic);
723 
end;
724 
architecture syn of fs90_smiopad is
725 
signal gnd, vcc, eni : std_logic;
726 
begin
727 
  gnd <= '0'; vcc <= '1'; eni <= not en;
728 
  d1 : if drive = 1 generate
729 
    u0 : wyfa2gsa port map (q, d, pad, eni, vcc, gnd, gnd, gnd, gnd, gnd, vcc);
730 
  end generate;
731 
  d2 : if drive = 2 generate
732 
    u0 : wyfa2gsa port map (q, d, pad, eni, gnd, vcc, gnd, gnd, gnd, gnd, vcc);
733 
  end generate;
734 
  d3 : if drive = 3 generate
735 
    u0 : wyfa2gsa port map (q, d, pad, eni, gnd, gnd, vcc, gnd, gnd, gnd, vcc);
736 
  end generate;
737 
  d4 : if drive > 3 generate
738 
    u0 : wyfa2gsa port map (q, d, pad, eni, gnd, vcc, vcc, gnd, gnd, gnd, vcc);
739 
  end generate;
740 
end;
741 
 
742 
-- bidirectional pad with open-drain
743 
library IEEE;
744 
use IEEE.std_logic_1164.all;
745 
use work.tech_fs90_syn.all;
746 
entity fs90_iodpad is
747 
  generic (drive : integer := 1);
748 
  port ( d : in std_logic; q : out std_logic; pad : inout std_logic);
749 
end;
750 
architecture syn of fs90_iodpad is
751 
signal gnd, vcc, eni : std_logic;
752 
begin
753 
  gnd <= '0'; vcc <= '1'; eni <= not d;
754 
  d1 : if drive = 1 generate
755 
    u0 : wyfa2gsa port map (q, gnd, pad, eni, vcc, gnd, gnd, gnd, gnd, gnd, gnd);
756 
  end generate;
757 
  d2 : if drive = 2 generate
758 
    u0 : wyfa2gsa port map (q, gnd, pad, eni, gnd, vcc, gnd, gnd, gnd, gnd, gnd);
759 
  end generate;
760 
  d3 : if drive = 3 generate
761 
    u0 : wyfa2gsa port map (q, gnd, pad, eni, gnd, gnd, vcc, gnd, gnd, gnd, gnd);
762 
  end generate;
763 
  d4 : if drive > 3 generate
764 
    u0 : wyfa2gsa port map (q, gnd, pad, eni, gnd, vcc, vcc, gnd, gnd, gnd, gnd);
765 
  end generate;
766 
end;
767 
 
768 
-- output pad with open-drain
769 
library IEEE;
770 
use IEEE.std_logic_1164.all;
771 
use work.tech_fs90_syn.all;
772 
entity fs90_odpad is
773 
  generic (drive : integer := 1);
774 
  port (d : in std_logic; pad : out std_logic);
775 
end;
776 
architecture syn of fs90_odpad is
777 
signal gnd, vcc, eni : std_logic;
778 
begin
779 
  gnd <= '0'; vcc <= '1'; eni <= not d;
780 
  d1 : if drive = 1 generate
781 
    u0 : vyfa2gsa port map (pad, gnd, eni, vcc, gnd, gnd, gnd);
782 
  end generate;
783 
  d2 : if drive = 2 generate
784 
    u0 : vyfa2gsa port map (pad, gnd, eni, gnd, vcc, gnd, gnd);
785 
  end generate;
786 
  d3 : if drive = 3 generate
787 
    u0 : vyfa2gsa port map (pad, gnd, eni, gnd, gnd, vcc, gnd);
788 
  end generate;
789 
  d4 : if drive > 3 generate
790 
    u0 : vyfa2gsa port map (pad, gnd, eni, gnd, vcc, vcc, gnd);
791 
  end generate;
792 
end;

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