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[/] [core_arm/] [trunk/] [vhdl/] [tech/] [tech_virtex.vhd] - Blame information for rev 4

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1 2 tarookumic 
 
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3 
 
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5 
----------------------------------------------------------------------------
6 
--  This file is a part of the LEON VHDL model
7 
--  Copyright (C) 2003  Gaisler Research
8 
--
9 
--  This library is free software; you can redistribute it and/or
10 
--  modify it under the terms of the GNU Lesser General Public
11 
--  License as published by the Free Software Foundation; either
12 
--  version 2 of the License, or (at your option) any later version.
13 
--
14 
--  See the file COPYING.LGPL for the full details of the license.
15 
 
16 
 
17 
-----------------------------------------------------------------------------
18 
-- Package:     tech_virtex
19 
-- File:        tech_virtex.vhd
20 
-- Author:      Jiri Gaisler - Gaisler Research
21 
-- Description: Xilinx Virtex specific regfile and cache ram generators
22 
------------------------------------------------------------------------------
23 
 
24 
LIBRARY ieee;
25 
use IEEE.std_logic_1164.all;
26 
use work.leon_iface.all;
27 
 
28 
package tech_virtex is
29 
 
30 
component virtex_syncram
31 
  generic ( abits : integer := 10; dbits : integer := 8 );
32 
  port (
33 
    address  : in std_logic_vector((abits -1) downto 0);
34 
    clk      : in std_logic;
35 
    datain   : in std_logic_vector((dbits -1) downto 0);
36 
    dataout  : out std_logic_vector((dbits -1) downto 0);
37 
    enable   : in std_logic;
38 
    write    : in std_logic
39 
   );
40 
end component;
41 
 
42 
-- three-port regfile with sync read, sync write
43 
  component virtex_regfile
44 
  generic (
45 
    rftype : integer := 1;
46 
    abits : integer := 8; dbits : integer := 32; words : integer := 128
47 
  );
48 
  port (
49 
    rst      : in std_logic;
50 
    clk      : in std_logic;
51 
    clkn     : in std_logic;
52 
    rfi      : in rf_in_type;
53 
    rfo      : out rf_out_type);
54 
  end component;
55 
 
56 
  component virtex_regfile_cp
57 
  generic (
58 
    abits : integer := 4; dbits : integer := 32; words : integer := 16
59 
  );
60 
  port (
61 
    rst      : in std_logic;
62 
    clk      : in std_logic;
63 
    rfi      : in rf_cp_in_type;
64 
    rfo      : out rf_cp_out_type);
65 
  end component;
66 
 
67 
  component virtex_bprom
68 
  port (
69 
    clk       : in std_logic;
70 
    addr      : in std_logic_vector(29 downto 0);
71 
    data      : out std_logic_vector(31 downto 0)
72 
  );
73 
  end component;
74 
 
75 
component virtex_dpram
76 
  generic ( abits : integer := 10; dbits : integer := 8 );
77 
  port (
78 
    address1 : in std_logic_vector((abits -1) downto 0);
79 
    clk1     : in std_logic;
80 
    datain1  : in std_logic_vector((dbits -1) downto 0);
81 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
82 
    enable1  : in std_logic;
83 
    write1   : in std_logic;
84 
    address2 : in std_logic_vector((abits -1) downto 0);
85 
    clk2     : in std_logic;
86 
    datain2  : in std_logic_vector((dbits -1) downto 0);
87 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
88 
    enable2  : in std_logic;
89 
    write2   : in std_logic
90 
   );
91 
end component;
92 
 
93 
component virtex_clkgen
94 
generic ( clk_mul : integer := 1 ; clk_div : integer := 1);
95 
port (
96 
    clkin   : in  std_logic;
97 
    pciclkin: in  std_logic;
98 
    clk     : out std_logic;                    -- main clock
99 
    clkn    : out std_logic;                    -- inverted main clock
100 
    sdclk   : out std_logic;                    -- SDRAM clock
101 
    pciclk  : out std_logic;                    -- PCI clock
102 
    cgi     : in clkgen_in_type;
103 
    cgo     : out clkgen_out_type
104 
);
105 
end component;
106 
 
107 
component virtex_pciinpad port (q : out std_ulogic; pad : in std_logic); end component;
108 
component virtex_pcitoutpad port (d, en : in  std_logic; pad : out  std_logic); end component;
109 
component virtex_pcioutpad port (d : in  std_logic; pad : out  std_logic); end component;
110 
component virtex_pciiopad
111 
  port (d, en : in  std_logic; q : out std_ulogic; pad : inout  std_logic);
112 
end component;
113 
component virtex_pciiodpad
114 
  port (d : in  std_logic; q : out std_ulogic; pad : inout  std_logic);
115 
end component;
116 
 
117 
end;
118 
 
119 
-- xilinx pre-loaded cache
120 
 
121 
-- pragma translate_off
122 
-- boot prom
123 
 
124 
library IEEE;
125 
use IEEE.std_logic_1164.all;
126 
 
127 
entity virtex_prom256 is port (
128 
  addr: in  std_logic_vector(7 downto 0);
129 
  clk : in  std_logic;
130 
  do  : out std_logic_vector(31 downto 0));
131 
end;
132 
library IEEE;
133 
use IEEE.std_logic_1164.all;
134 
entity virtex_prom512 is port (
135 
  addr: in  std_logic_vector(8 downto 0);
136 
  clk : in  std_logic;
137 
  do  : out std_logic_vector(31 downto 0));
138 
end;
139 
library IEEE;
140 
use IEEE.std_logic_1164.all;
141 
entity virtex_prom1024 is port (
142 
  addr: in  std_logic_vector(9 downto 0);
143 
  clk : in  std_logic;
144 
  do  : out std_logic_vector(31 downto 0));
145 
end;
146 
library IEEE;
147 
use IEEE.std_logic_1164.all;
148 
entity virtex_prom2048 is port (
149 
  addr: in  std_logic_vector(10 downto 0);
150 
  clk : in  std_logic;
151 
  do  : out std_logic_vector(31 downto 0));
152 
end;
153 
-- pragma translate_on
154 
 
155 
library IEEE;
156 
use IEEE.std_logic_1164.all;
157 
use work.leon_config.all;
158 
 
159 
entity virtex_bprom is
160 
  port (
161 
    clk       : in std_logic;
162 
    addr      : in std_logic_vector(29 downto 0);
163 
    data      : out std_logic_vector(31 downto 0)
164 
  );
165 
end;
166 
 
167 
architecture rtl of virtex_bprom is
168 
component virtex_prom256 port (
169 
  addr: in  std_logic_vector(7 downto 0);
170 
  clk : in  std_logic;
171 
  do  : out std_logic_vector(31 downto 0));
172 
end component;
173 
component virtex_prom512 port (
174 
  addr: in  std_logic_vector(8 downto 0);
175 
  clk : in  std_logic;
176 
  do  : out std_logic_vector(31 downto 0));
177 
end component;
178 
component virtex_prom1024 port (
179 
  addr: in  std_logic_vector(9 downto 0);
180 
  clk : in  std_logic;
181 
  do  : out std_logic_vector(31 downto 0));
182 
end component;
183 
component virtex_prom2048 port (
184 
  addr: in  std_logic_vector(10 downto 0);
185 
  clk : in  std_logic;
186 
  do  : out std_logic_vector(31 downto 0));
187 
end component;
188 
begin
189 
 
190 
  p256 : if PABITS = 8 generate
191 
    dt0 : virtex_prom256 port map (
192 
          addr => addr(7 downto 0), clk => clk, do => data(31 downto 0));
193 
  end generate;
194 
  p512 : if PABITS = 9 generate
195 
    dt0 : virtex_prom512 port map (
196 
          addr => addr(8 downto 0), clk => clk, do => data(31 downto 0));
197 
  end generate;
198 
  p1024 : if PABITS = 10 generate
199 
    dt0 : virtex_prom1024 port map (
200 
          addr => addr(9 downto 0), clk => clk, do => data(31 downto 0));
201 
  end generate;
202 
  p2048 : if PABITS = 11 generate
203 
    dt0 : virtex_prom2048 port map (
204 
          addr => addr(10 downto 0), clk => clk, do => data(31 downto 0));
205 
  end generate;
206 
end;
207 
 
208 
-- pragma translate_off
209 
 
210 
-- simulation models for select-rams
211 
 
212 
LIBRARY ieee;
213 
use IEEE.std_logic_1164.all;
214 
use work.tech_generic.all;
215 
 
216 
entity RAMB4_S16 is
217 
  port (DI     : in std_logic_vector (15 downto 0);
218 
        EN     : in std_logic;
219 
        WE     : in std_logic;
220 
        RST    : in std_logic;
221 
        CLK    : in std_logic;
222 
        ADDR   : in std_logic_vector (7 downto 0);
223 
        DO     : out std_logic_vector (15 downto 0)
224 
       );
225 
end;
226 
architecture behav of RAMB4_S16 is
227 
begin x : generic_syncram generic map (8,16)
228 
          port map (addr, clk, di, do, en, we);
229 
end;
230 
 
231 
LIBRARY ieee;
232 
use IEEE.std_logic_1164.all;
233 
use work.tech_generic.all;
234 
 
235 
entity RAMB4_S8 is
236 
  port (DI     : in std_logic_vector (7 downto 0);
237 
        EN     : in std_logic;
238 
        WE     : in std_logic;
239 
        RST    : in std_logic;
240 
        CLK    : in std_logic;
241 
        ADDR   : in std_logic_vector (8 downto 0);
242 
        DO     : out std_logic_vector (7 downto 0)
243 
       );
244 
end;
245 
architecture behav of RAMB4_S8 is
246 
begin x : generic_syncram generic map (9,8)
247 
          port map (addr, clk, di, do, en, we);
248 
end;
249 
 
250 
LIBRARY ieee;
251 
use IEEE.std_logic_1164.all;
252 
use work.tech_generic.all;
253 
 
254 
entity RAMB4_S4 is
255 
  port (DI     : in std_logic_vector (3 downto 0);
256 
        EN     : in std_logic;
257 
        WE     : in std_logic;
258 
        RST    : in std_logic;
259 
        CLK    : in std_logic;
260 
        ADDR   : in std_logic_vector (9 downto 0);
261 
        DO     : out std_logic_vector (3 downto 0)
262 
       );
263 
end;
264 
architecture behav of RAMB4_S4 is
265 
begin x : generic_syncram generic map (10,4)
266 
          port map (addr, clk, di, do, en, we);
267 
end;
268 
 
269 
LIBRARY ieee;
270 
use IEEE.std_logic_1164.all;
271 
use work.tech_generic.all;
272 
 
273 
entity RAMB4_S2 is
274 
  port (DI     : in std_logic_vector (1 downto 0);
275 
        EN     : in std_logic;
276 
        WE     : in std_logic;
277 
        RST    : in std_logic;
278 
        CLK    : in std_logic;
279 
        ADDR   : in std_logic_vector (10 downto 0);
280 
        DO     : out std_logic_vector (1 downto 0)
281 
       );
282 
end;
283 
architecture behav of RAMB4_S2 is
284 
begin x : generic_syncram generic map (11,2)
285 
          port map (addr, clk, di, do, en, we);
286 
end;
287 
 
288 
LIBRARY ieee;
289 
use IEEE.std_logic_1164.all;
290 
use work.tech_generic.all;
291 
 
292 
entity RAMB4_S1 is
293 
  port (DI     : in std_logic_vector (0 downto 0);
294 
        EN     : in std_logic;
295 
        WE     : in std_logic;
296 
        RST    : in std_logic;
297 
        CLK    : in std_logic;
298 
        ADDR   : in std_logic_vector (11 downto 0);
299 
        DO     : out std_logic_vector (0 downto 0)
300 
       );
301 
end;
302 
architecture behav of RAMB4_S1 is
303 
begin x : generic_syncram generic map (12,1)
304 
          port map (addr, clk, di, do, en, we);
305 
end;
306 
 
307 
LIBRARY ieee;
308 
use IEEE.std_logic_1164.all;
309 
use IEEE.std_logic_arith.all;
310 
use work.tech_generic.all;
311 
 
312 
entity RAMB4_S1_S1 is
313 
  port (DIA    : in std_logic_vector (0 downto 0);
314 
        DIB    : in std_logic_vector (0 downto 0);
315 
        ENA    : in std_logic;
316 
        ENB    : in std_logic;
317 
        WEA    : in std_logic;
318 
        WEB    : in std_logic;
319 
        RSTA   : in std_logic;
320 
        RSTB   : in std_logic;
321 
        CLKA   : in std_logic;
322 
        CLKB   : in std_logic;
323 
        ADDRA  : in std_logic_vector (11 downto 0);
324 
        ADDRB  : in std_logic_vector (11 downto 0);
325 
        DOA    : out std_logic_vector (0 downto 0);
326 
        DOB    : out std_logic_vector (0 downto 0)
327 
       );
328 
end;
329 
architecture behav of RAMB4_S1_S1 is
330 
begin
331 
  rp : process(clka, clkb)
332 
  subtype dword is std_logic_vector(0 downto 0);
333 
  type dregtype is array (0 to 4095) of DWord;
334 
  variable rfd : dregtype;
335 
  begin
336 
    if rising_edge(clka) and not is_x (addra) then
337 
      if ena = '1' then
338 
        doa <= rfd(conv_integer(unsigned(addra)));
339 
        if wea = '1' then
340 
          rfd(conv_integer(unsigned(addra))) := dia;
341 
        end if;
342 
      end if;
343 
    end if;
344 
    if rising_edge(clkb) and not is_x (addrb) then
345 
      if enb = '1' then
346 
        dob <= rfd(conv_integer(unsigned(addrb)));
347 
        if web = '1' then
348 
          rfd(conv_integer(unsigned(addrb))) := dib;
349 
        end if;
350 
      end if;
351 
    end if;
352 
  end process;
353 
end;
354 
 
355 
LIBRARY ieee;
356 
use IEEE.std_logic_1164.all;
357 
use IEEE.std_logic_arith.all;
358 
use work.tech_generic.all;
359 
 
360 
entity RAMB4_S2_S2 is
361 
  port (DIA    : in std_logic_vector (1 downto 0);
362 
        DIB    : in std_logic_vector (1 downto 0);
363 
        ENA    : in std_logic;
364 
        ENB    : in std_logic;
365 
        WEA    : in std_logic;
366 
        WEB    : in std_logic;
367 
        RSTA   : in std_logic;
368 
        RSTB   : in std_logic;
369 
        CLKA   : in std_logic;
370 
        CLKB   : in std_logic;
371 
        ADDRA  : in std_logic_vector (10 downto 0);
372 
        ADDRB  : in std_logic_vector (10 downto 0);
373 
        DOA    : out std_logic_vector (1 downto 0);
374 
        DOB    : out std_logic_vector (1 downto 0)
375 
       );
376 
end;
377 
architecture behav of RAMB4_S2_S2 is
378 
begin
379 
  rp : process(clka, clkb)
380 
  subtype dword is std_logic_vector(1 downto 0);
381 
  type dregtype is array (0 to 2047) of DWord;
382 
  variable rfd : dregtype;
383 
  begin
384 
    if rising_edge(clka) and not is_x (addra) then
385 
      if ena = '1' then
386 
        doa <= rfd(conv_integer(unsigned(addra)));
387 
        if wea = '1' then
388 
          rfd(conv_integer(unsigned(addra))) := dia;
389 
        end if;
390 
      end if;
391 
    end if;
392 
    if rising_edge(clkb) and not is_x (addrb) then
393 
      if enb = '1' then
394 
        dob <= rfd(conv_integer(unsigned(addrb)));
395 
        if web = '1' then
396 
          rfd(conv_integer(unsigned(addrb))) := dib;
397 
        end if;
398 
      end if;
399 
    end if;
400 
  end process;
401 
end;
402 
 
403 
LIBRARY ieee;
404 
use IEEE.std_logic_1164.all;
405 
use IEEE.std_logic_arith.all;
406 
use work.tech_generic.all;
407 
 
408 
entity RAMB4_S8_S8 is
409 
  port (DIA    : in std_logic_vector (7 downto 0);
410 
        DIB    : in std_logic_vector (7 downto 0);
411 
        ENA    : in std_logic;
412 
        ENB    : in std_logic;
413 
        WEA    : in std_logic;
414 
        WEB    : in std_logic;
415 
        RSTA   : in std_logic;
416 
        RSTB   : in std_logic;
417 
        CLKA   : in std_logic;
418 
        CLKB   : in std_logic;
419 
        ADDRA  : in std_logic_vector (8 downto 0);
420 
        ADDRB  : in std_logic_vector (8 downto 0);
421 
        DOA    : out std_logic_vector (7 downto 0);
422 
        DOB    : out std_logic_vector (7 downto 0)
423 
       );
424 
end;
425 
 
426 
architecture behav of RAMB4_S8_S8 is
427 
begin
428 
  rp : process(clka, clkb)
429 
  subtype dword is std_logic_vector(7 downto 0);
430 
  type dregtype is array (0 to 511) of DWord;
431 
  variable rfd : dregtype;
432 
  begin
433 
    if rising_edge(clka) and not is_x (addra) then
434 
      if ena = '1' then
435 
        doa <= rfd(conv_integer(unsigned(addra)));
436 
        if wea = '1' then
437 
          rfd(conv_integer(unsigned(addra))) := dia;
438 
        end if;
439 
      end if;
440 
    end if;
441 
    if rising_edge(clkb) and not is_x (addrb) then
442 
      if enb = '1' then
443 
        dob <= rfd(conv_integer(unsigned(addrb)));
444 
        if web = '1' then
445 
          rfd(conv_integer(unsigned(addrb))) := dib;
446 
        end if;
447 
      end if;
448 
    end if;
449 
  end process;
450 
end;
451 
 
452 
LIBRARY ieee;
453 
use IEEE.std_logic_1164.all;
454 
use IEEE.std_logic_arith.all;
455 
use work.tech_generic.all;
456 
 
457 
entity RAMB4_S4_S4 is
458 
  port (DIA    : in std_logic_vector (3 downto 0);
459 
        DIB    : in std_logic_vector (3 downto 0);
460 
        ENA    : in std_logic;
461 
        ENB    : in std_logic;
462 
        WEA    : in std_logic;
463 
        WEB    : in std_logic;
464 
        RSTA   : in std_logic;
465 
        RSTB   : in std_logic;
466 
        CLKA   : in std_logic;
467 
        CLKB   : in std_logic;
468 
        ADDRA  : in std_logic_vector (9 downto 0);
469 
        ADDRB  : in std_logic_vector (9 downto 0);
470 
        DOA    : out std_logic_vector (3 downto 0);
471 
        DOB    : out std_logic_vector (3 downto 0)
472 
       );
473 
end;
474 
architecture behav of RAMB4_S4_S4 is
475 
begin
476 
  rp : process(clka, clkb)
477 
  subtype dword is std_logic_vector(3 downto 0);
478 
  type dregtype is array (0 to 1023) of DWord;
479 
  variable rfd : dregtype;
480 
  begin
481 
    if rising_edge(clka) and not is_x (addra) then
482 
      if ena = '1' then
483 
        doa <= rfd(conv_integer(unsigned(addra)));
484 
        if wea = '1' then
485 
          rfd(conv_integer(unsigned(addra))) := dia;
486 
        end if;
487 
      end if;
488 
    end if;
489 
    if rising_edge(clkb) and not is_x (addrb) then
490 
      if enb = '1' then
491 
        dob <= rfd(conv_integer(unsigned(addrb)));
492 
        if web = '1' then
493 
          rfd(conv_integer(unsigned(addrb))) := dib;
494 
        end if;
495 
      end if;
496 
    end if;
497 
  end process;
498 
end;
499 
 
500 
LIBRARY ieee;
501 
use IEEE.std_logic_1164.all;
502 
use IEEE.std_logic_arith.all;
503 
use work.tech_generic.all;
504 
 
505 
entity RAMB4_S16_S16 is
506 
  port (DIA    : in std_logic_vector (15 downto 0);
507 
        DIB    : in std_logic_vector (15 downto 0);
508 
        ENA    : in std_logic;
509 
        ENB    : in std_logic;
510 
        WEA    : in std_logic;
511 
        WEB    : in std_logic;
512 
        RSTA   : in std_logic;
513 
        RSTB   : in std_logic;
514 
        CLKA   : in std_logic;
515 
        CLKB   : in std_logic;
516 
        ADDRA  : in std_logic_vector (7 downto 0);
517 
        ADDRB  : in std_logic_vector (7 downto 0);
518 
        DOA    : out std_logic_vector (15 downto 0);
519 
        DOB    : out std_logic_vector (15 downto 0)
520 
       );
521 
end;
522 
architecture behav of RAMB4_S16_S16 is
523 
begin
524 
  rp : process(clka, clkb)
525 
  subtype dword is std_logic_vector(15 downto 0);
526 
  type dregtype is array (0 to 255) of DWord;
527 
  variable rfd : dregtype;
528 
  begin
529 
    if rising_edge(clka) and not is_x (addra) then
530 
      if ena = '1' then
531 
        doa <= rfd(conv_integer(unsigned(addra)));
532 
        if wea = '1' then
533 
          rfd(conv_integer(unsigned(addra))) := dia;
534 
        end if;
535 
      end if;
536 
    end if;
537 
    if rising_edge(clkb) and not is_x (addrb) then
538 
      if enb = '1' then
539 
        dob <= rfd(conv_integer(unsigned(addrb)));
540 
        if web = '1' then
541 
          rfd(conv_integer(unsigned(addrb))) := dib;
542 
        end if;
543 
      end if;
544 
    end if;
545 
  end process;
546 
end;
547 
 
548 
LIBRARY ieee;
549 
use IEEE.std_logic_1164.all;
550 
entity IBUF_PCI33_3 is
551 
    port (O : out std_ulogic; I : in std_ulogic);
552 
end;
553 
architecture beh of IBUF_PCI33_3 is begin
554 
  O <= to_X01(I) after 2 ns;
555 
end;
556 
 
557 
LIBRARY ieee;
558 
use IEEE.std_logic_1164.all;
559 
entity OBUF_PCI33_3 is
560 
    port (O : out std_ulogic; I : in std_ulogic);
561 
end;
562 
architecture beh of OBUF_PCI33_3 is begin O <= I after 7 ns; end;
563 
 
564 
LIBRARY ieee;
565 
use IEEE.std_logic_1164.all;
566 
entity IOBUF_PCI33_3 is
567 
    port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic);
568 
end;
569 
architecture beh of IOBUF_PCI33_3 is begin
570 
  O <= to_X01(IO) after 2 ns;
571 
  IO <= I after 7 ns when T = '0' else 'Z' after 7 ns;
572 
end;
573 
 
574 
LIBRARY ieee;
575 
use IEEE.std_logic_1164.all;
576 
entity OBUFT_PCI33_3 is
577 
    port (O : out std_ulogic; I, T : in std_ulogic);
578 
end;
579 
architecture beh of OBUFT_PCI33_3 is begin
580 
  O <= I after 7 ns when T = '0' else 'Z' after 7 ns;
581 
end;
582 
 
583 
-- pragma translate_on
584 
 
585 
-- package with virtex select-ram component declarations
586 
library IEEE;
587 
use IEEE.std_logic_1164.all;
588 
 
589 
package virtex_complib is
590 
  component RAMB4_S16
591 
  port (DI     : in std_logic_vector (15 downto 0);
592 
        EN     : in std_logic;
593 
        WE     : in std_logic;
594 
        RST    : in std_logic;
595 
        CLK    : in std_logic;
596 
        ADDR   : in std_logic_vector (7 downto 0);
597 
        DO     : out std_logic_vector (15 downto 0)
598 
       );
599 
  end component;
600 
  component RAMB4_S8
601 
  port (DI     : in std_logic_vector (7 downto 0);
602 
        EN     : in std_logic;
603 
        WE     : in std_logic;
604 
        RST    : in std_logic;
605 
        CLK    : in std_logic;
606 
        ADDR   : in std_logic_vector (8 downto 0);
607 
        DO     : out std_logic_vector (7 downto 0)
608 
       );
609 
  end component;
610 
  component RAMB4_S4
611 
  port (DI     : in std_logic_vector (3 downto 0);
612 
        EN     : in std_logic;
613 
        WE     : in std_logic;
614 
        RST    : in std_logic;
615 
        CLK    : in std_logic;
616 
        ADDR   : in std_logic_vector (9 downto 0);
617 
        DO     : out std_logic_vector (3 downto 0)
618 
       );
619 
  end component;
620 
  component RAMB4_S2
621 
  port (DI     : in std_logic_vector (1 downto 0);
622 
        EN     : in std_logic;
623 
        WE     : in std_logic;
624 
        RST    : in std_logic;
625 
        CLK    : in std_logic;
626 
        ADDR   : in std_logic_vector (10 downto 0);
627 
        DO     : out std_logic_vector (1 downto 0)
628 
       );
629 
  end component;
630 
  component RAMB4_S1
631 
  port (DI     : in std_logic_vector (0 downto 0);
632 
        EN     : in std_logic;
633 
        WE     : in std_logic;
634 
        RST    : in std_logic;
635 
        CLK    : in std_logic;
636 
        ADDR   : in std_logic_vector (11 downto 0);
637 
        DO     : out std_logic_vector (0 downto 0)
638 
       );
639 
  end component;
640 
  component RAMB4_S1_S1
641 
  port (DIA    : in std_logic_vector (0 downto 0);
642 
        DIB    : in std_logic_vector (0 downto 0);
643 
        ENA    : in std_logic;
644 
        ENB    : in std_logic;
645 
        WEA    : in std_logic;
646 
        WEB    : in std_logic;
647 
        RSTA   : in std_logic;
648 
        RSTB   : in std_logic;
649 
        CLKA   : in std_logic;
650 
        CLKB   : in std_logic;
651 
        ADDRA  : in std_logic_vector (11 downto 0);
652 
        ADDRB  : in std_logic_vector (11 downto 0);
653 
        DOA    : out std_logic_vector (0 downto 0);
654 
        DOB    : out std_logic_vector (0 downto 0)
655 
       );
656 
  end component;
657 
  component RAMB4_S2_S2
658 
  port (DIA    : in std_logic_vector (1 downto 0);
659 
        DIB    : in std_logic_vector (1 downto 0);
660 
        ENA    : in std_logic;
661 
        ENB    : in std_logic;
662 
        WEA    : in std_logic;
663 
        WEB    : in std_logic;
664 
        RSTA   : in std_logic;
665 
        RSTB   : in std_logic;
666 
        CLKA   : in std_logic;
667 
        CLKB   : in std_logic;
668 
        ADDRA  : in std_logic_vector (10 downto 0);
669 
        ADDRB  : in std_logic_vector (10 downto 0);
670 
        DOA    : out std_logic_vector (1 downto 0);
671 
        DOB    : out std_logic_vector (1 downto 0)
672 
       );
673 
  end component;
674 
  component RAMB4_S4_S4
675 
  port (DIA    : in std_logic_vector (3 downto 0);
676 
        DIB    : in std_logic_vector (3 downto 0);
677 
        ENA    : in std_logic;
678 
        ENB    : in std_logic;
679 
        WEA    : in std_logic;
680 
        WEB    : in std_logic;
681 
        RSTA   : in std_logic;
682 
        RSTB   : in std_logic;
683 
        CLKA   : in std_logic;
684 
        CLKB   : in std_logic;
685 
        ADDRA  : in std_logic_vector (9 downto 0);
686 
        ADDRB  : in std_logic_vector (9 downto 0);
687 
        DOA    : out std_logic_vector (3 downto 0);
688 
        DOB    : out std_logic_vector (3 downto 0)
689 
       );
690 
  end component;
691 
  component RAMB4_S8_S8
692 
  port (DIA    : in std_logic_vector (7 downto 0);
693 
        DIB    : in std_logic_vector (7 downto 0);
694 
        ENA    : in std_logic;
695 
        ENB    : in std_logic;
696 
        WEA    : in std_logic;
697 
        WEB    : in std_logic;
698 
        RSTA   : in std_logic;
699 
        RSTB   : in std_logic;
700 
        CLKA   : in std_logic;
701 
        CLKB   : in std_logic;
702 
        ADDRA  : in std_logic_vector (8 downto 0);
703 
        ADDRB  : in std_logic_vector (8 downto 0);
704 
        DOA    : out std_logic_vector (7 downto 0);
705 
        DOB    : out std_logic_vector (7 downto 0)
706 
       );
707 
  end component;
708 
  component RAMB4_S16_S16
709 
  port (DIA    : in std_logic_vector (15 downto 0);
710 
        DIB    : in std_logic_vector (15 downto 0);
711 
        ENA    : in std_logic;
712 
        ENB    : in std_logic;
713 
        WEA    : in std_logic;
714 
        WEB    : in std_logic;
715 
        RSTA   : in std_logic;
716 
        RSTB   : in std_logic;
717 
        CLKA   : in std_logic;
718 
        CLKB   : in std_logic;
719 
        ADDRA  : in std_logic_vector (7 downto 0);
720 
        ADDRB  : in std_logic_vector (7 downto 0);
721 
        DOA    : out std_logic_vector (15 downto 0);
722 
        DOB    : out std_logic_vector (15 downto 0)
723 
       );
724 
  end component;
725 
  component IBUF_PCI33_3
726 
    port (O : out std_ulogic; I : in std_ulogic);
727 
  end component;
728 
  component OBUF_PCI33_3
729 
    port (O : out std_ulogic; I : in std_ulogic);
730 
  end component;
731 
  component IOBUF_PCI33_3
732 
    port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic);
733 
  end component;
734 
  component OBUFT_PCI33_3
735 
    port (O : out std_ulogic; I, T : in std_ulogic);
736 
  end component;
737 
 
738 
end;
739 
 
740 
-- parametrisable sync ram generator using virtex select rams
741 
-- max size: 4096x128 bits
742 
 
743 
LIBRARY ieee;
744 
use IEEE.std_logic_1164.all;
745 
use work.virtex_complib.all;
746 
 
747 
entity virtex_syncram is
748 
  generic ( abits : integer := 8; dbits : integer := 32);
749 
  port (
750 
    address : in std_logic_vector (abits -1 downto 0);
751 
    clk     : in std_logic;
752 
    datain  : in std_logic_vector (dbits -1 downto 0);
753 
    dataout : out std_logic_vector (dbits -1 downto 0);
754 
    enable  : in std_logic;
755 
    write   : in std_logic
756 
  );
757 
end;
758 
 
759 
architecture behav of virtex_syncram is
760 
signal gnd : std_logic;
761 
signal do, di : std_logic_vector(129 downto 0);
762 
signal xa, ya : std_logic_vector(19 downto 0);
763 
begin
764 
  gnd <= '0';
765 
  dataout <= do(dbits-1 downto 0);
766 
  di(dbits-1 downto 0) <= datain; di(129 downto dbits) <= (others => '0');
767 
  xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
768 
  ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
769 
 
770 
  a7 : if (abits <= 7) and (dbits <= 32) generate
771 
    r0 : RAMB4_S16_S16 port map ( di(31 downto 16), di(15 downto 0),
772 
        enable, enable, write, write, gnd, gnd, clk, clk, xa(7 downto 0),
773 
        ya(7 downto 0), do(31 downto 16), do(15 downto 0));
774 
  end generate;
775 
  a8 : if ((abits <= 7) and (dbits > 32)) or (abits = 8) generate
776 
    x : for i in 0 to ((dbits-1)/16) generate
777 
      r : RAMB4_S16 port map ( di (((i+1)*16)-1 downto i*16),
778 
          enable, write, gnd, clk, xa(7 downto 0),
779 
          do (((i+1)*16)-1 downto i*16));
780 
    end generate;
781 
  end generate;
782 
  a9 : if abits = 9 generate
783 
    x : for i in 0 to ((dbits-1)/8) generate
784 
      r : RAMB4_S8 port map ( di (((i+1)*8)-1 downto i*8),
785 
          enable, write, gnd, clk, xa(8 downto 0),
786 
          do (((i+1)*8)-1 downto i*8));
787 
    end generate;
788 
  end generate;
789 
  a10 : if abits = 10 generate
790 
    x : for i in 0 to ((dbits-1)/4) generate
791 
      r : RAMB4_S4 port map ( di (((i+1)*4)-1 downto i*4),
792 
          enable, write, gnd, clk, xa(9 downto 0),
793 
          do (((i+1)*4)-1 downto i*4));
794 
    end generate;
795 
  end generate;
796 
  a11 : if abits = 11 generate
797 
    x : for i in 0 to ((dbits-1)/2) generate
798 
      r : RAMB4_S2 port map ( di (((i+1)*2)-1 downto i*2),
799 
          enable, write, gnd, clk, xa(10 downto 0),
800 
          do (((i+1)*2)-1 downto i*2));
801 
    end generate;
802 
  end generate;
803 
  a12 : if abits = 12 generate
804 
    x : for i in 0 to (dbits-1) generate
805 
      r : RAMB4_S1 port map ( di(i downto i),
806 
          enable, write, gnd, clk, xa(11 downto 0),
807 
          do (i downto i));
808 
    end generate;
809 
  end generate;
810 
end;
811 
 
812 
LIBRARY ieee;
813 
use IEEE.std_logic_1164.all;
814 
use work.leon_iface.all;
815 
use work.virtex_complib.all;
816 
 
817 
entity virtex_dpram is
818 
  generic (
819 
    abits : integer := 4; dbits : integer := 32
820 
  );
821 
  port (
822 
    address1 : in std_logic_vector((abits -1) downto 0);
823 
    clk1     : in std_logic;
824 
    datain1  : in std_logic_vector((dbits -1) downto 0);
825 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
826 
    enable1  : in std_logic;
827 
    write1   : in std_logic;
828 
    address2 : in std_logic_vector((abits -1) downto 0);
829 
    clk2     : in std_logic;
830 
    datain2  : in std_logic_vector((dbits -1) downto 0);
831 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
832 
    enable2  : in std_logic;
833 
    write2   : in std_logic);
834 
end;
835 
 
836 
architecture behav of virtex_dpram is
837 
 
838 
signal gnd, vcc : std_logic;
839 
signal do1, do2, di1, di2 : std_logic_vector(129 downto 0);
840 
signal addr1, addr2 : std_logic_vector(19 downto 0);
841 
begin
842 
  gnd <= '0'; vcc <= '1';
843 
  dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
844 
  di1(dbits-1 downto 0) <= datain1; di1(129 downto dbits) <= (others => '0');
845 
  di2(dbits-1 downto 0) <= datain2; di2(129 downto dbits) <= (others => '0');
846 
  addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
847 
  addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
848 
 
849 
  a8 : if abits <= 8 generate
850 
    x : for i in 0 to ((dbits-1)/16) generate
851 
      r0 : RAMB4_S16_S16 port map (
852 
        di1(((i+1)*16)-1 downto i*16), di2(((i+1)*16)-1 downto i*16),
853 
        enable1, enable2, write1, write2, gnd, gnd, clk1, clk2,
854 
        addr1(7 downto 0), addr2(7 downto 0),
855 
        do1(((i+1)*16)-1 downto i*16), do2(((i+1)*16)-1 downto i*16));
856 
    end generate;
857 
  end generate;
858 
 
859 
  a9 : if abits = 9 generate
860 
    x : for i in 0 to ((dbits-1)/8) generate
861 
      r0 : RAMB4_S8_S8 port map (
862 
        di1(((i+1)*8)-1 downto i*8), di2(((i+1)*8)-1 downto i*8),
863 
        enable1, enable2, write1, write2, gnd, gnd, clk1, clk2,
864 
        addr1(8 downto 0), addr2(8 downto 0),
865 
        do1(((i+1)*8)-1 downto i*8), do2(((i+1)*8)-1 downto i*8));
866 
    end generate;
867 
  end generate;
868 
 
869 
  a10: if abits = 10 generate
870 
    x : for i in 0 to ((dbits-1)/4) generate
871 
      r0 : RAMB4_S4_S4 port map (
872 
        di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
873 
        enable1, enable2, write1, write2, gnd, gnd, clk1, clk2,
874 
        addr1(9 downto 0), addr2(9 downto 0),
875 
        do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4));
876 
    end generate;
877 
  end generate;
878 
 
879 
  a11: if abits = 11 generate
880 
    x : for i in 0 to ((dbits-1)/2) generate
881 
      r0 : RAMB4_S2_S2 port map (
882 
        di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
883 
        enable1, enable2, write1, write2, gnd, gnd, clk1, clk2,
884 
        addr1(10 downto 0), addr2(10 downto 0),
885 
        do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2));
886 
    end generate;
887 
  end generate;
888 
 
889 
  a12: if abits = 12 generate
890 
    x : for i in 0 to ((dbits-1)/1) generate
891 
      r0 : RAMB4_S1_S1 port map (
892 
        di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
893 
        enable1, enable2, write1, write2, gnd, gnd, clk1, clk2,
894 
        addr1(11 downto 0), addr2(11 downto 0),
895 
        do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1));
896 
    end generate;
897 
  end generate;
898 
 
899 
end;
900 
 
901 
LIBRARY ieee;
902 
use IEEE.std_logic_1164.all;
903 
use work.leon_iface.all;
904 
use work.tech_virtex.all;
905 
 
906 
entity virtex_regfile is
907 
  generic (
908 
    rftype : integer := 1;
909 
    abits : integer := 8; dbits : integer := 32; words : integer := 128
910 
  );
911 
  port (
912 
    rst      : in std_logic;
913 
    clk      : in std_logic;
914 
    clkn     : in std_logic;
915 
    rfi      : in rf_in_type;
916 
    rfo      : out rf_out_type);
917 
end;
918 
 
919 
architecture behav of virtex_regfile is
920 
 
921 
signal vcc : std_logic;
922 
signal gnd : std_logic_vector(127 downto 0);
923 
begin
924 
  vcc <= '1'; gnd <= (others => '0');
925 
 
926 
  rf0 : if rftype = 1 generate
927 
    r0 : virtex_dpram generic map (abits, dbits)
928 
      port map (
929 
        rfi.rd1addr((abits -1) downto 0), clkn, gnd((dbits -1) downto 0),
930 
        rfo.data1((dbits -1) downto 0), vcc, gnd(0),
931 
        rfi.wraddr((abits -1) downto 0), clkn, rfi.wrdata((dbits -1) downto 0),
932 
        open, rfi.wren, rfi.wren);
933 
    r1 : virtex_dpram generic map (abits, dbits)
934 
      port map (
935 
        rfi.rd2addr((abits -1) downto 0), clkn, gnd((dbits -1) downto 0),
936 
        rfo.data2((dbits -1) downto 0), vcc, gnd(0),
937 
        rfi.wraddr((abits -1) downto 0), clkn, rfi.wrdata((dbits -1) downto 0),
938 
        open, rfi.wren, rfi.wren);
939 
  end generate;
940 
 
941 
  rf1 : if rftype = 2 generate
942 
    r0 : virtex_dpram generic map (abits, dbits)
943 
      port map (
944 
        rfi.rd1addr((abits -1) downto 0), clkn, gnd((dbits -1) downto 0),
945 
        rfo.data1((dbits -1) downto 0), vcc, gnd(0),
946 
        rfi.wraddr((abits -1) downto 0), clk, rfi.wrdata((dbits -1) downto 0),
947 
        open, rfi.wren, rfi.wren);
948 
    r1 : virtex_dpram generic map (abits, dbits)
949 
      port map (
950 
        rfi.rd2addr((abits -1) downto 0), clkn, gnd((dbits -1) downto 0),
951 
        rfo.data2((dbits -1) downto 0), vcc, gnd(0),
952 
        rfi.wraddr((abits -1) downto 0), clk, rfi.wrdata((dbits -1) downto 0),
953 
        open, rfi.wren, rfi.wren);
954 
  end generate;
955 
 
956 
end;
957 
 
958 
LIBRARY ieee;
959 
use IEEE.std_logic_1164.all;
960 
use work.leon_iface.all;
961 
use work.virtex_complib.all;
962 
 
963 
entity virtex_regfile_cp is
964 
  generic (
965 
    abits : integer := 4; dbits : integer := 32; words : integer := 16
966 
  );
967 
  port (
968 
    rst      : in std_logic;
969 
    clk      : in std_logic;
970 
    rfi      : in rf_cp_in_type;
971 
    rfo      : out rf_cp_out_type);
972 
end;
973 
 
974 
architecture behav of virtex_regfile_cp is
975 
 
976 
signal gnd, vcc : std_logic;
977 
signal do1, do2, di1, di2 : std_logic_vector(129 downto 0);
978 
signal ra1, ra2, wa : std_logic_vector(19 downto 0);
979 
signal gnd16 : std_logic_vector(15 downto 0);
980 
begin
981 
  gnd <= '0'; vcc <= '1'; gnd16 <= (others => '0');
982 
  rfo.data1 <= do1(dbits-1 downto 0); rfo.data2 <= do2(dbits-1 downto 0);
983 
  di1(dbits-1 downto 0) <= rfi.wrdata; di1(129 downto dbits) <= (others => '0');
984 
  di2(129 downto 0) <= (others => '0');
985 
  ra1(abits-1 downto 0) <= rfi.rd1addr; ra1(19 downto abits) <= (others => '0');
986 
  ra2(abits-1 downto 0) <= rfi.rd2addr; ra2(19 downto abits) <= (others => '0');
987 
  wa(abits-1 downto 0) <= rfi.wraddr; wa(19 downto abits) <= (others => '0');
988 
 
989 
  a8 : if abits <= 8 generate
990 
    x : for i in 0 to ((dbits-1)/16) generate
991 
      r0 : RAMB4_S16_S16 port map (
992 
        di1(((i+1)*16)-1 downto i*16), gnd16,
993 
        vcc, vcc, rfi.wren, gnd, gnd, gnd, clk, clk, wa(7 downto 0),
994 
        ra1(7 downto 0), open, do1(((i+1)*16)-1 downto i*16));
995 
      r1 : RAMB4_S16_S16 port map (
996 
        di1(((i+1)*16)-1 downto i*16), gnd16,
997 
        vcc, vcc, rfi.wren, gnd, gnd, gnd, clk, clk, wa(7 downto 0),
998 
        ra2(7 downto 0), open, do2(((i+1)*16)-1 downto i*16));
999 
    end generate;
1000 
  end generate;
1001 
end;
1002 
 
1003 
-- input PCI pad
1004 
library IEEE;
1005 
use IEEE.std_logic_1164.all;
1006 
use work.virtex_complib.all;
1007 
entity virtex_pciinpad is port (q : out std_ulogic; pad : in std_logic); end;
1008 
architecture rtl of virtex_pciinpad is
1009 
begin op : IBUF_PCI33_3 port map (O => q, I => pad); end;
1010 
 
1011 
-- output PCI pad
1012 
library IEEE;
1013 
use IEEE.std_logic_1164.all;
1014 
use work.virtex_complib.all;
1015 
 
1016 
entity virtex_pcioutpad is port (d : in  std_logic; pad : out  std_logic); end;
1017 
architecture rtl of virtex_pcioutpad is
1018 
begin op : OBUF_PCI33_3 port map (O => pad, I => d); end;
1019 
 
1020 
-- tri-state output PCI pad
1021 
library IEEE;
1022 
use IEEE.std_logic_1164.all;
1023 
use work.virtex_complib.all;
1024 
entity virtex_pcitoutpad is port (d, en : in  std_logic; pad : out  std_logic); end;
1025 
architecture rtl of virtex_pcitoutpad is
1026 
begin
1027 
  op : OBUFT_PCI33_3 port map (O => pad, I => d, T => en);
1028 
end;
1029 
 
1030 
-- bi-directional PCI pad
1031 
library IEEE;
1032 
use IEEE.std_logic_1164.all;
1033 
use work.virtex_complib.all;
1034 
entity virtex_pciiopad is
1035 
  port (d, en : in  std_logic; q : out std_ulogic; pad : inout  std_logic);
1036 
end;
1037 
architecture rtl of virtex_pciiopad is
1038 
begin
1039 
  op : IOBUF_PCI33_3
1040 
  port map (O => q, IO => pad, I => d, T => en);
1041 
end;
1042 
 
1043 
-- bi-directional open-drain PCI pad
1044 
library IEEE;
1045 
use IEEE.std_logic_1164.all;
1046 
use work.virtex_complib.all;
1047 
entity virtex_pciiodpad is
1048 
  port (d : in  std_logic; q : out std_ulogic; pad : inout  std_logic);
1049 
end;
1050 
architecture rtl of virtex_pciiodpad is
1051 
signal gnd : std_ulogic;
1052 
begin
1053 
  gnd <= '0';
1054 
  op : IOBUF_PCI33_3 port map (O => q, IO => pad, I => gnd, T => d);
1055 
end;
1056 
 
1057 
library IEEE;
1058 
use IEEE.std_logic_1164.all;
1059 
use work.leon_target.all;
1060 
use work.leon_iface.all;
1061 
use work.leon_config.all;
1062 
--library unisim;
1063 
--use unisim.vcomponents.all;
1064 
 
1065 
entity virtex_clkgen is
1066 
generic ( clk_mul : integer := 1 ; clk_div : integer := 1);
1067 
port (
1068 
    clkin   : in  std_logic;
1069 
    pciclkin: in  std_logic;
1070 
    clk     : out std_logic;                    -- main clock
1071 
    clkn    : out std_logic;                    -- inverted main clock
1072 
    sdclk   : out std_logic;                    -- SDRAM clock
1073 
    pciclk  : out std_logic;                    -- PCI clock
1074 
    cgi     : in clkgen_in_type;
1075 
    cgo     : out clkgen_out_type
1076 
);
1077 
end;
1078 
 
1079 
architecture rtl of virtex_clkgen is
1080 
  component CLKDLL
1081 
    port (
1082 
      CLK0    : out std_ulogic;
1083 
      CLK180  : out std_ulogic;
1084 
      CLK270  : out std_ulogic;
1085 
      CLK2X   : out std_ulogic;
1086 
      CLK90   : out std_ulogic;
1087 
      CLKDV   : out std_ulogic;
1088 
      LOCKED  : out std_ulogic;
1089 
      CLKFB   : in  std_ulogic;
1090 
      CLKIN   : in  std_ulogic;
1091 
      RST     : in  std_ulogic
1092 
      );
1093 
  end component;
1094 
  component IBUFG port ( O : out std_logic; I : in std_logic); end component;
1095 
  component BUFG port ( O : out std_logic; I : in std_logic); end component;
1096 
  component IBUFG_PCI33_3 port ( O : out std_logic; I : in std_logic); end component;
1097 
  component BUFGDLL port ( O : out std_logic; I : in std_logic); end component;
1098 
 
1099 
  signal gnd, Clk_i, Clk_j, Clk_k, dll0rst, dll0lock, dll1lock, dll1rst : std_logic;
1100 
  signal Clk0B, Clk_FB, Clkint, CLK2X, CLKDV, CLK180, pciclkint : std_logic;
1101 
 
1102 
begin
1103 
 
1104 
  gnd <= '0'; clk <= clk_i; clkn <= not clk_i;
1105 
  c0 : if not PCI_SYSCLK generate
1106 
    ibufg0 : IBUFG port map (I => Clkin, O => Clkint);
1107 
  end generate;
1108 
 
1109 
  c1 : if PCI_SYSCLK generate
1110 
    ibufg0 : IBUFG port map (I => pciclkin, O => Clkint);
1111 
  end generate;
1112 
 
1113 
  c2 : if PCIEN generate
1114 
    p0 : if PCI_CLKDLL generate
1115 
      u0 : IBUFG port map (I => pciclkin, O => pciclkint);
1116 
      u1 : BUFGDLL port map (O => pciclk, I => pciclkint);
1117 
    end generate;
1118 
    p1 : if not PCI_CLKDLL generate
1119 
      u0 : if not PCI_SYSCLK generate
1120 
        u1 : BUFG port map (I => pciclkin, O => pciclkint);
1121 
      end generate;
1122 
      pciclk <= clk_i when PCI_SYSCLK else pciclkint;
1123 
    end generate;
1124 
  end generate;
1125 
 
1126 
  c3 : if not PCIEN generate
1127 
    pciclk <= Clkint;
1128 
  end generate;
1129 
 
1130 
  bufg0 : BUFG port map (I => Clk0B, O => Clk_i);
1131 
  bufg1 : BUFG port map (I => Clk_j, O => Clk_k);
1132 
  ibufg1 : IBUFG port map (I => cgi.pllref, O => Clk_FB);
1133 
  dll0rst <= not cgi.pllrst;
1134 
  dll0 : CLKDLL
1135 
    port map (CLKIN => Clkint, CLKFB => Clk_k, CLK0 => Clk_j, CLK180 => CLK180,
1136 
    CLK2X => CLK2X, CLKDV => CLKDV, LOCKED => dll0lock, RST => dll0rst);
1137 
 
1138 
  Clk0B <= CLK2X when clk_mul = 2 else CLKDV when clk_div = 2 else Clk_j;
1139 
 
1140 
  sd0 : if SDRAMEN and not SDINVCLK generate
1141 
    dll1rst <= not dll0lock; cgo.clklock <= dll1lock;
1142 
    dll1 : CLKDLL
1143 
      port map (CLKIN => Clk_i, CLKFB => Clk_FB, RST => dll1rst, CLK0 => sdclk,
1144 
        LOCKED => dll1lock);
1145 
  end generate;
1146 
 
1147 
  sd1 : if not (SDRAMEN and not SDINVCLK) generate
1148 
    sdclk <= not clk_i; cgo.clklock <= dll0lock;
1149 
  end generate;
1150 
 
1151 
  cgo.pcilock <= '1';
1152 
 
1153 
end;
1154 
 

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