OpenCores
URL https://opencores.org/ocsvn/core_arm/core_arm/trunk

Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [vhdl/] [tech/] [tech_virtex2.vhd] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 tarookumic 
 
2 
 
3 
 
4 
 
5 
----------------------------------------------------------------------------
6 
--  This file is a part of the LEON VHDL model
7 
--  Copyright (C) 2003 Gaisler Research
8 
--
9 
--  This library is free software; you can redistribute it and/or
10 
--  modify it under the terms of the GNU Lesser General Public
11 
--  License as published by the Free Software Foundation; either
12 
--  version 2 of the License, or (at your option) any later version.
13 
--
14 
--  See the file COPYING.LGPL for the full details of the license.
15 
 
16 
 
17 
-----------------------------------------------------------------------------
18 
-- Package:     tech_virtex2
19 
-- File:        tech_virtex2.vhd
20 
-- Author:      Jiri Gaisler - Gaisler Research
21 
-- Author:      Richard Pender - Pender Electronic Design
22 
-- Description: Xilinx Virtex2 specific regfile and cache ram generators
23 
------------------------------------------------------------------------------
24 
 
25 
LIBRARY ieee;
26 
use IEEE.std_logic_1164.all;
27 
use work.leon_iface.all;
28 
 
29 
package tech_virtex2 is
30 
 
31 
component virtex2_syncram
32 
  generic ( abits : integer := 10; dbits : integer := 8 );
33 
  port (
34 
    address  : in std_logic_vector((abits -1) downto 0);
35 
    clk      : in std_logic;
36 
    datain   : in std_logic_vector((dbits -1) downto 0);
37 
    dataout  : out std_logic_vector((dbits -1) downto 0);
38 
    enable   : in std_logic;
39 
    write    : in std_logic
40 
   );
41 
end component;
42 
 
43 
-- three-port regfile with sync read, sync write
44 
  component virtex2_regfile
45 
  generic (
46 
    rftype : integer := 1;
47 
    abits : integer := 8; dbits : integer := 32; words : integer := 128
48 
  );
49 
  port (
50 
    rst      : in std_logic;
51 
    clk      : in std_logic;
52 
    clkn     : in std_logic;
53 
    rfi      : in rf_in_type;
54 
    rfo      : out rf_out_type);
55 
  end component;
56 
 
57 
  component virtex2_regfile_cp
58 
  generic (
59 
    abits : integer := 4; dbits : integer := 32; words : integer := 16
60 
  );
61 
  port (
62 
    rst      : in std_logic;
63 
    clk      : in std_logic;
64 
    rfi      : in rf_cp_in_type;
65 
    rfo      : out rf_cp_out_type);
66 
  end component;
67 
 
68 
component virtex2_dpram
69 
  generic ( abits : integer := 10; dbits : integer := 8 );
70 
  port (
71 
    address1 : in std_logic_vector((abits -1) downto 0);
72 
    clk1     : in std_logic;
73 
    datain1  : in std_logic_vector((dbits -1) downto 0);
74 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
75 
    enable1  : in std_logic;
76 
    write1   : in std_logic;
77 
    address2 : in std_logic_vector((abits -1) downto 0);
78 
    clk2     : in std_logic;
79 
    datain2  : in std_logic_vector((dbits -1) downto 0);
80 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
81 
    enable2  : in std_logic;
82 
    write2   : in std_logic
83 
   );
84 
end component;
85 
 
86 
component virtex2_clkgen
87 
  generic ( clk_mul : integer := 1 ; clk_div : integer := 1);
88 
  port (
89 
    clkin   : in  std_logic;
90 
    pciclkin: in  std_logic;
91 
    clk     : out std_logic;                    -- main clock
92 
    clkn    : out std_logic;                    -- inverted main clock
93 
    sdclk   : out std_logic;                    -- SDRAM clock
94 
    pciclk  : out std_logic;                    -- PCI clock
95 
    cgi     : in clkgen_in_type;
96 
    cgo     : out clkgen_out_type
97 
  );
98 
end component;
99 
 
100 
end;
101 
 
102 
-- package with virtex select-ram component declarations
103 
library IEEE;
104 
use IEEE.std_logic_1164.all;
105 
 
106 
package virtex2_complib is
107 
  component RAMB16_S1
108 
  port (
109 
    DO : out std_logic_vector (0 downto 0);
110 
    ADDR : in std_logic_vector (13 downto 0);
111 
    DI : in std_logic_vector (0 downto 0);
112 
    EN : in std_logic;
113 
    CLK : in std_logic;
114 
    WE : in std_logic;
115 
    SSR : in std_logic
116 
  );
117 
end component;
118 
 
119 
component RAMB16_S2
120 
 port (
121 
   DO : out std_logic_vector (1 downto 0);
122 
   ADDR : in std_logic_vector (12 downto 0);
123 
   DI : in std_logic_vector (1 downto 0);
124 
   EN : in std_logic;
125 
   CLK : in std_logic;
126 
   WE : in std_logic;
127 
   SSR : in std_logic
128 
 );
129 
end component;
130 
 
131 
component RAMB16_S4
132 
 port (
133 
   DO : out std_logic_vector (3 downto 0);
134 
   ADDR : in std_logic_vector (11 downto 0);
135 
   DI : in std_logic_vector (3 downto 0);
136 
   EN : in std_logic;
137 
   CLK : in std_logic;
138 
   WE : in std_logic;
139 
   SSR : in std_logic
140 
 );
141 
end component;
142 
 
143 
component RAMB16_S9
144 
 port (
145 
   DO : out std_logic_vector (7 downto 0);
146 
   DOP : out std_logic_vector (0 downto 0);
147 
   ADDR : in std_logic_vector (10 downto 0);
148 
   DI : in std_logic_vector (7 downto 0);
149 
   DIP : in std_logic_vector (0 downto 0);
150 
   EN : in std_logic;
151 
   CLK : in std_logic;
152 
   WE : in std_logic;
153 
   SSR : in std_logic
154 
 );
155 
end component;
156 
 
157 
  component RAMB16_S18
158 
  port (
159 
    DO : out std_logic_vector (15 downto 0);
160 
    DOP : out std_logic_vector (1 downto 0);
161 
    ADDR : in std_logic_vector (9 downto 0);
162 
    DI : in std_logic_vector (15 downto 0);
163 
    DIP : in std_logic_vector (1 downto 0);
164 
    EN : in std_logic;
165 
    CLK : in std_logic;
166 
    WE : in std_logic;
167 
    SSR : in std_logic
168 
  );
169 
end component;
170 
 
171 
component RAMB16_S36
172 
 port (
173 
   DO : out std_logic_vector (31 downto 0);
174 
   DOP : out std_logic_vector (3 downto 0);
175 
   ADDR : in std_logic_vector (8 downto 0);
176 
   DI : in std_logic_vector (31 downto 0);
177 
   DIP : in std_logic_vector (3 downto 0);
178 
   EN : in std_logic;
179 
   CLK : in std_logic;
180 
   WE : in std_logic;
181 
   SSR : in std_logic
182 
 );
183 
end component;
184 
 
185 
component RAMB16_S4_S4
186 
 port (
187 
   DOA : out std_logic_vector (3 downto 0);
188 
   DOB : out std_logic_vector (3 downto 0);
189 
   ADDRA : in std_logic_vector (11 downto 0);
190 
   CLKA : in std_logic;
191 
   DIA : in std_logic_vector (3 downto 0);
192 
   ENA : in std_logic;
193 
   SSRA : in std_logic;
194 
   WEA : in std_logic;
195 
   ADDRB : in std_logic_vector (11 downto 0);
196 
   CLKB : in std_logic;
197 
   DIB : in std_logic_vector (3 downto 0);
198 
   ENB : in std_logic;
199 
   SSRB : in std_logic;
200 
   WEB : in std_logic
201 
 );
202 
end component;
203 
 
204 
component RAMB16_S9_S9
205 
 port (
206 
   DOA : out std_logic_vector (7 downto 0);
207 
   DOPA : out std_logic_vector (0 downto 0);
208 
   DOB : out std_logic_vector (7 downto 0);
209 
   DOPB : out std_logic_vector (0 downto 0);
210 
   ADDRA : in std_logic_vector (10 downto 0);
211 
   CLKA : in std_logic;
212 
   DIA : in std_logic_vector (7 downto 0);
213 
   DIPA : in std_logic_vector (0 downto 0);
214 
   ENA : in std_logic;
215 
   SSRA : in std_logic;
216 
   WEA : in std_logic;
217 
   ADDRB : in std_logic_vector (10 downto 0);
218 
   CLKB : in std_logic;
219 
   DIB : in std_logic_vector (7 downto 0);
220 
   DIPB : in std_logic_vector (0 downto 0);
221 
   ENB : in std_logic;
222 
   SSRB : in std_logic;
223 
   WEB : in std_logic
224 
 );
225 
end component;
226 
 
227 
component RAMB16_S18_S18
228 
 port (
229 
   DOA : out std_logic_vector (15 downto 0);
230 
   DOPA : out std_logic_vector (1 downto 0);
231 
   DOB : out std_logic_vector (15 downto 0);
232 
   DOPB : out std_logic_vector (1 downto 0);
233 
   ADDRA : in std_logic_vector (9 downto 0);
234 
   CLKA : in std_logic;
235 
   DIA : in std_logic_vector (15 downto 0);
236 
   DIPA : in std_logic_vector (1 downto 0);
237 
   ENA : in std_logic;
238 
   SSRA : in std_logic;
239 
   WEA : in std_logic;
240 
   ADDRB : in std_logic_vector (9 downto 0);
241 
   CLKB : in std_logic;
242 
   DIB : in std_logic_vector (15 downto 0);
243 
   DIPB : in std_logic_vector (1 downto 0);
244 
   ENB : in std_logic;
245 
   SSRB : in std_logic;
246 
   WEB : in std_logic
247 
 );
248 
end component;
249 
 
250 
component RAMB16_S36_S36
251 
 port (
252 
   DOA : out std_logic_vector (31 downto 0);
253 
   DOPA : out std_logic_vector (3 downto 0);
254 
   DOB : out std_logic_vector (31 downto 0);
255 
   DOPB : out std_logic_vector (3 downto 0);
256 
   ADDRA : in std_logic_vector (8 downto 0);
257 
   CLKA : in std_logic;
258 
   DIA : in std_logic_vector (31 downto 0);
259 
   DIPA : in std_logic_vector (3 downto 0);
260 
   ENA : in std_logic;
261 
   SSRA : in std_logic;
262 
   WEA : in std_logic;
263 
   ADDRB : in std_logic_vector (8 downto 0);
264 
   CLKB : in std_logic;
265 
   DIB : in std_logic_vector (31 downto 0);
266 
   DIPB : in std_logic_vector (3 downto 0);
267 
   ENB : in std_logic;
268 
   SSRB : in std_logic;
269 
   WEB : in std_logic
270 
 );
271 
end component;
272 
 
273 
-- pragma translate_off
274 
component ram16_sx_sx
275 
  generic ( abits : integer := 10; dbits : integer := 8 );
276 
  port (
277 
   DOA : out std_logic_vector (dbits-1 downto 0);
278 
   DOB : out std_logic_vector (dbits-1 downto 0);
279 
   ADDRA : in std_logic_vector (abits-1 downto 0);
280 
   CLKA : in std_logic;
281 
   DIA : in std_logic_vector (dbits-1 downto 0);
282 
   ENA : in std_logic;
283 
   WEA : in std_logic;
284 
   ADDRB : in std_logic_vector (abits-1 downto 0);
285 
   CLKB : in std_logic;
286 
   DIB : in std_logic_vector (dbits-1 downto 0);
287 
   ENB : in std_logic;
288 
   WEB : in std_logic
289 
  );
290 
end component;
291 
-- pragma translate_on
292 
end;
293 
-- pragma translate_off
294 
 
295 
-- simulation models for select-rams
296 
 
297 
LIBRARY ieee;
298 
use IEEE.std_logic_1164.all;
299 
use work.tech_generic.all;
300 
 
301 
entity RAMB16_S1 is
302 
 port (
303 
   DO : out std_logic_vector (0 downto 0);
304 
   ADDR : in std_logic_vector (13 downto 0);
305 
   DI : in std_logic_vector (0 downto 0);
306 
   EN : in std_logic;
307 
   CLK : in std_logic;
308 
   WE : in std_logic;
309 
   SSR : in std_logic
310 
 );
311 
end;
312 
architecture behav of RAMB16_S1 is
313 
begin x : generic_syncram generic map (14,1)
314 
          port map (addr, clk, di, do, en, we);
315 
end;
316 
 
317 
LIBRARY ieee;
318 
use IEEE.std_logic_1164.all;
319 
use work.tech_generic.all;
320 
 
321 
entity RAMB16_S2 is
322 
 port (
323 
   DO : out std_logic_vector (1 downto 0);
324 
   ADDR : in std_logic_vector (12 downto 0);
325 
   DI : in std_logic_vector (1 downto 0);
326 
   EN : in std_logic;
327 
   CLK : in std_logic;
328 
   WE : in std_logic;
329 
   SSR : in std_logic
330 
 );
331 
end;
332 
architecture behav of RAMB16_S2 is
333 
begin x : generic_syncram generic map (13,2)
334 
          port map (addr, clk, di, do, en, we);
335 
end;
336 
 
337 
LIBRARY ieee;
338 
use IEEE.std_logic_1164.all;
339 
use work.tech_generic.all;
340 
 
341 
entity RAMB16_S4 is
342 
 port (
343 
   DO : out std_logic_vector (3 downto 0);
344 
   ADDR : in std_logic_vector (11 downto 0);
345 
   DI : in std_logic_vector (3 downto 0);
346 
   EN : in std_logic;
347 
   CLK : in std_logic;
348 
   WE : in std_logic;
349 
   SSR : in std_logic
350 
 );
351 
end;
352 
architecture behav of RAMB16_S4 is
353 
begin x : generic_syncram generic map (12,4)
354 
          port map (addr, clk, di, do, en, we);
355 
end;
356 
 
357 
LIBRARY ieee;
358 
use IEEE.std_logic_1164.all;
359 
use work.tech_generic.all;
360 
 
361 
entity RAMB16_S9 is
362 
 port (
363 
   DO : out std_logic_vector (7 downto 0);
364 
   DOP : out std_logic_vector (0 downto 0);
365 
   ADDR : in std_logic_vector (10 downto 0);
366 
   DI : in std_logic_vector (7 downto 0);
367 
   DIP : in std_logic_vector (0 downto 0);
368 
   EN : in std_logic;
369 
   CLK : in std_logic;
370 
   WE : in std_logic;
371 
   SSR : in std_logic
372 
 );
373 
end;
374 
architecture behav of RAMB16_S9 is
375 
signal dix, dox : std_logic_vector (8 downto 0);
376 
begin x : generic_syncram generic map (11,9)
377 
          port map (addr, clk, dix, dox, en, we);
378 
  dix <= dip & di; dop <= dox(8 downto 8); do <= dox(7 downto 0);
379 
end;
380 
 
381 
LIBRARY ieee;
382 
use IEEE.std_logic_1164.all;
383 
use work.tech_generic.all;
384 
 
385 
entity RAMB16_S18 is
386 
 port (
387 
   DO : out std_logic_vector (15 downto 0);
388 
   DOP : out std_logic_vector (1 downto 0);
389 
   ADDR : in std_logic_vector (9 downto 0);
390 
   DI : in std_logic_vector (15 downto 0);
391 
   DIP : in std_logic_vector (1 downto 0);
392 
   EN : in std_logic;
393 
   CLK : in std_logic;
394 
   WE : in std_logic;
395 
   SSR : in std_logic
396 
 );
397 
end;
398 
architecture behav of RAMB16_S18 is
399 
signal dix, dox : std_logic_vector (17 downto 0);
400 
begin x : generic_syncram generic map (10,18)
401 
          port map (addr, clk, dix, dox, en, we);
402 
  dix <= dip & di; dop <= dox(17 downto 16); do <= dox(15 downto 0);
403 
end;
404 
 
405 
LIBRARY ieee;
406 
use IEEE.std_logic_1164.all;
407 
use work.tech_generic.all;
408 
 
409 
entity RAMB16_S36 is
410 
 port (
411 
   DO : out std_logic_vector (31 downto 0);
412 
   DOP : out std_logic_vector (3 downto 0);
413 
   ADDR : in std_logic_vector (8 downto 0);
414 
   DI : in std_logic_vector (31 downto 0);
415 
   DIP : in std_logic_vector (3 downto 0);
416 
   EN : in std_logic;
417 
   CLK : in std_logic;
418 
   WE : in std_logic;
419 
   SSR : in std_logic
420 
 );
421 
end;
422 
architecture behav of RAMB16_S36 is
423 
signal dix, dox : std_logic_vector (35 downto 0);
424 
begin x : generic_syncram generic map (9, 36)
425 
          port map (addr, clk, dix, dox, en, we);
426 
  dix <= dip & di; dop <= dox(35 downto 32); do <= dox(31 downto 0);
427 
end;
428 
 
429 
LIBRARY ieee;
430 
use IEEE.std_logic_1164.all;
431 
use IEEE.std_logic_arith.all;
432 
 
433 
entity ram16_sx_sx is
434 
  generic ( abits : integer := 10; dbits : integer := 8 );
435 
  port (
436 
   DOA : out std_logic_vector (dbits-1 downto 0);
437 
   DOB : out std_logic_vector (dbits-1 downto 0);
438 
   ADDRA : in std_logic_vector (abits-1 downto 0);
439 
   CLKA : in std_logic;
440 
   DIA : in std_logic_vector (dbits-1 downto 0);
441 
   ENA : in std_logic;
442 
   WEA : in std_logic;
443 
   ADDRB : in std_logic_vector (abits-1 downto 0);
444 
   CLKB : in std_logic;
445 
   DIB : in std_logic_vector (dbits-1 downto 0);
446 
   ENB : in std_logic;
447 
   WEB : in std_logic
448 
  );
449 
end;
450 
architecture behav of ram16_sx_sx is
451 
begin
452 
  rp : process(clka, clkb)
453 
  subtype dword is std_logic_vector(dbits-1 downto 0);
454 
  type dregtype is array (0 to 2**abits -1) of DWord;
455 
  variable rfd : dregtype;
456 
  begin
457 
    if rising_edge(clka) and not is_x (addra) then
458 
      if ena = '1' then
459 
        doa <= rfd(conv_integer(unsigned(addra)));
460 
        if wea = '1' then rfd(conv_integer(unsigned(addra))) := dia; end if;
461 
      end if;
462 
    end if;
463 
    if rising_edge(clkb) and not is_x (addrb) then
464 
      if enb = '1' then
465 
        dob <= rfd(conv_integer(unsigned(addrb)));
466 
        if web = '1' then rfd(conv_integer(unsigned(addrb))) := dib; end if;
467 
      end if;
468 
    end if;
469 
  end process;
470 
end;
471 
 
472 
LIBRARY ieee;
473 
use IEEE.std_logic_1164.all;
474 
use IEEE.std_logic_arith.all;
475 
use work.virtex2_complib.all;
476 
 
477 
entity RAMB16_S4_S4 is
478 
  port (
479 
   DOA : out std_logic_vector (3 downto 0);
480 
   DOB : out std_logic_vector (3 downto 0);
481 
   ADDRA : in std_logic_vector (11 downto 0);
482 
   CLKA : in std_logic;
483 
   DIA : in std_logic_vector (3 downto 0);
484 
   ENA : in std_logic;
485 
   SSRA : in std_logic;
486 
   WEA : in std_logic;
487 
   ADDRB : in std_logic_vector (11 downto 0);
488 
   CLKB : in std_logic;
489 
   DIB : in std_logic_vector (3 downto 0);
490 
   ENB : in std_logic;
491 
   SSRB : in std_logic;
492 
   WEB : in std_logic
493 
  );
494 
end;
495 
architecture behav of RAMB16_S4_S4 is
496 
begin
497 
  x : ram16_sx_sx generic map (12, 4)
498 
  port map (doa, dob, addra, clka, dia, ena, wea, addrb, clkb, dib, enb, web);
499 
end;
500 
 
501 
LIBRARY ieee;
502 
use IEEE.std_logic_1164.all;
503 
use IEEE.std_logic_arith.all;
504 
use work.virtex2_complib.all;
505 
 
506 
entity RAMB16_S9_S9 is
507 
  port (
508 
   DOA : out std_logic_vector (7 downto 0);
509 
   DOPA : out std_logic_vector (0 downto 0);
510 
   DOB : out std_logic_vector (7 downto 0);
511 
   DOPB : out std_logic_vector (0 downto 0);
512 
   ADDRA : in std_logic_vector (10 downto 0);
513 
   CLKA : in std_logic;
514 
   DIA : in std_logic_vector (7 downto 0);
515 
   DIPA : in std_logic_vector (0 downto 0);
516 
   ENA : in std_logic;
517 
   SSRA : in std_logic;
518 
   WEA : in std_logic;
519 
   ADDRB : in std_logic_vector (10 downto 0);
520 
   CLKB : in std_logic;
521 
   DIB : in std_logic_vector (7 downto 0);
522 
   DIPB : in std_logic_vector (0 downto 0);
523 
   ENB : in std_logic;
524 
   SSRB : in std_logic;
525 
   WEB : in std_logic
526 
  );
527 
end;
528 
architecture behav of RAMB16_S9_S9 is
529 
signal diax, doax, dibx, dobx : std_logic_vector (8 downto 0);
530 
begin
531 
  x : ram16_sx_sx generic map (11, 9)
532 
  port map (doax, dobx, addra, clka, diax, ena, wea, addrb, clkb, dibx, enb, web);
533 
  diax <= dipa & dia; dopa <= doax(8 downto 8); doa <= doax(7 downto 0);
534 
  dibx <= dipb & dib; dopb <= dobx(8 downto 8); dob <= dobx(7 downto 0);
535 
end;
536 
 
537 
LIBRARY ieee;
538 
use IEEE.std_logic_1164.all;
539 
use IEEE.std_logic_arith.all;
540 
use work.virtex2_complib.all;
541 
 
542 
entity RAMB16_S18_S18 is
543 
  port (
544 
   DOA : out std_logic_vector (15 downto 0);
545 
   DOPA : out std_logic_vector (1 downto 0);
546 
   DOB : out std_logic_vector (15 downto 0);
547 
   DOPB : out std_logic_vector (1 downto 0);
548 
   ADDRA : in std_logic_vector (9 downto 0);
549 
   CLKA : in std_logic;
550 
   DIA : in std_logic_vector (15 downto 0);
551 
   DIPA : in std_logic_vector (1 downto 0);
552 
   ENA : in std_logic;
553 
   SSRA : in std_logic;
554 
   WEA : in std_logic;
555 
   ADDRB : in std_logic_vector (9 downto 0);
556 
   CLKB : in std_logic;
557 
   DIB : in std_logic_vector (15 downto 0);
558 
   DIPB : in std_logic_vector (1 downto 0);
559 
   ENB : in std_logic;
560 
   SSRB : in std_logic;
561 
   WEB : in std_logic
562 
  );
563 
end;
564 
architecture behav of RAMB16_S18_S18 is
565 
signal diax, doax, dibx, dobx : std_logic_vector (17 downto 0);
566 
begin
567 
  x : ram16_sx_sx generic map (10, 18)
568 
  port map (doax, dobx, addra, clka, diax, ena, wea, addrb, clkb, dibx, enb, web);
569 
  diax <= dipa & dia; dopa <= doax(17 downto 16); doa <= doax(15 downto 0);
570 
  dibx <= dipb & dib; dopb <= dobx(17 downto 16); dob <= dobx(15 downto 0);
571 
end;
572 
 
573 
LIBRARY ieee;
574 
use IEEE.std_logic_1164.all;
575 
use IEEE.std_logic_arith.all;
576 
use work.virtex2_complib.all;
577 
 
578 
entity RAMB16_S36_S36 is
579 
  port (
580 
   DOA : out std_logic_vector (31 downto 0);
581 
   DOPA : out std_logic_vector (3 downto 0);
582 
   DOB : out std_logic_vector (31 downto 0);
583 
   DOPB : out std_logic_vector (3 downto 0);
584 
   ADDRA : in std_logic_vector (8 downto 0);
585 
   CLKA : in std_logic;
586 
   DIA : in std_logic_vector (31 downto 0);
587 
   DIPA : in std_logic_vector (3 downto 0);
588 
   ENA : in std_logic;
589 
   SSRA : in std_logic;
590 
   WEA : in std_logic;
591 
   ADDRB : in std_logic_vector (8 downto 0);
592 
   CLKB : in std_logic;
593 
   DIB : in std_logic_vector (31 downto 0);
594 
   DIPB : in std_logic_vector (3 downto 0);
595 
   ENB : in std_logic;
596 
   SSRB : in std_logic;
597 
   WEB : in std_logic
598 
  );
599 
end;
600 
architecture behav of RAMB16_S36_S36 is
601 
signal diax, doax, dibx, dobx : std_logic_vector (35 downto 0);
602 
begin
603 
  x : ram16_sx_sx generic map (9, 36)
604 
  port map (doax, dobx, addra, clka, diax, ena, wea, addrb, clkb, dibx, enb, web);
605 
  diax <= dipa & dia; dopa <= doax(35 downto 32); doa <= doax(31 downto 0);
606 
  dibx <= dipb & dib; dopb <= dobx(35 downto 32); dob <= dobx(31 downto 0);
607 
end;
608 
 
609 
-- pragma translate_on
610 
-- parametrisable sync ram generator using virtex2 select rams
611 
 
612 
LIBRARY ieee;
613 
use IEEE.std_logic_1164.all;
614 
use work.virtex2_complib.all;
615 
 
616 
entity virtex2_syncram is
617 
  generic ( abits : integer := 9; dbits : integer := 32);
618 
  port (
619 
    address : in std_logic_vector (abits -1 downto 0);
620 
    clk     : in std_logic;
621 
    datain  : in std_logic_vector (dbits -1 downto 0);
622 
    dataout : out std_logic_vector (dbits -1 downto 0);
623 
    enable  : in std_logic;
624 
    write   : in std_logic
625 
  );
626 
end;
627 
 
628 
architecture behav of virtex2_syncram is
629 
signal gnd : std_logic;
630 
signal do, di : std_logic_vector(129 downto 0);
631 
signal xa, ya : std_logic_vector(19 downto 0);
632 
begin
633 
  gnd <= '0';
634 
  dataout <= do(dbits-1 downto 0);
635 
  di(dbits-1 downto 0) <= datain; di(129 downto dbits) <= (others => '0');
636 
  xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
637 
  ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
638 
 
639 
  a9 : if (abits <= 9) generate
640 
    x : for i in 0 to ((dbits-1)/36) generate
641 
      r : RAMB16_S36 port map ( do(((i+1)*36)-5 downto i*36),
642 
        do(((i+1)*36)-1 downto i*36+32), xa(8 downto 0),
643 
        di(((i+1)*36)-5 downto i*36), di(((i+1)*36)-1 downto i*36+32),
644 
        enable, clk, write, gnd);
645 
    end generate;
646 
  end generate;
647 
  a10 : if abits = 10 generate
648 
    x : for i in 0 to ((dbits-1)/18) generate
649 
      r : RAMB16_S18 port map ( do(((i+1)*18)-3 downto i*18),
650 
        do(((i+1)*18)-1 downto i*18+16), xa(9 downto 0),
651 
        di(((i+1)*18)-3 downto i*18), di(((i+1)*18)-1 downto i*18+16),
652 
        enable, clk, write, gnd);
653 
    end generate;
654 
  end generate;
655 
  a11 : if abits = 11 generate
656 
    x : for i in 0 to ((dbits-1)/9) generate
657 
      r : RAMB16_S9 port map ( do(((i+1)*9)-2 downto i*9),
658 
        do(((i+1)*9)-1 downto i*9+8), xa(10 downto 0),
659 
        di(((i+1)*9)-2 downto i*9), di(((i+1)*9)-1 downto i*9+8),
660 
        enable, clk, write, gnd);
661 
    end generate;
662 
  end generate;
663 
  a12 : if abits = 12 generate
664 
    x : for i in 0 to ((dbits-1)/4) generate
665 
      r : RAMB16_S4 port map ( do(((i+1)*4)-1 downto i*4), xa(11 downto 0),
666 
        di(((i+1)*4)-1 downto i*4), enable, clk, write, gnd);
667 
    end generate;
668 
  end generate;
669 
  a13 : if abits = 13 generate
670 
    x : for i in 0 to ((dbits-1)/2) generate
671 
      r : RAMB16_S2 port map ( do(((i+1)*2)-1 downto i*2), xa(12 downto 0),
672 
        di(((i+1)*2)-1 downto i*2), enable, clk, write, gnd);
673 
    end generate;
674 
  end generate;
675 
  a14 : if abits = 14 generate
676 
    x : for i in 0 to (dbits-1) generate
677 
      r : RAMB16_S1 port map ( do((i+1)-1 downto i), xa(13 downto 0),
678 
        di((i+1)-1 downto i), enable, clk, write, gnd);
679 
    end generate;
680 
  end generate;
681 
end;
682 
 
683 
LIBRARY ieee;
684 
use IEEE.std_logic_1164.all;
685 
use work.leon_iface.all;
686 
use work.virtex2_complib.all;
687 
 
688 
entity virtex2_dpram is
689 
  generic (
690 
    abits : integer := 4; dbits : integer := 32
691 
  );
692 
  port (
693 
    address1 : in std_logic_vector((abits -1) downto 0);
694 
    clk1     : in std_logic;
695 
    datain1  : in std_logic_vector((dbits -1) downto 0);
696 
    dataout1 : out std_logic_vector((dbits -1) downto 0);
697 
    enable1  : in std_logic;
698 
    write1   : in std_logic;
699 
    address2 : in std_logic_vector((abits -1) downto 0);
700 
    clk2     : in std_logic;
701 
    datain2  : in std_logic_vector((dbits -1) downto 0);
702 
    dataout2 : out std_logic_vector((dbits -1) downto 0);
703 
    enable2  : in std_logic;
704 
    write2   : in std_logic);
705 
end;
706 
 
707 
architecture behav of virtex2_dpram is
708 
 
709 
signal gnd, vcc : std_logic;
710 
signal do1, do2, di1, di2 : std_logic_vector(129 downto 0);
711 
signal addr1, addr2 : std_logic_vector(19 downto 0);
712 
begin
713 
  gnd <= '0'; vcc <= '1';
714 
  dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
715 
  di1(dbits-1 downto 0) <= datain1; di1(129 downto dbits) <= (others => '0');
716 
  di2(dbits-1 downto 0) <= datain2; di2(129 downto dbits) <= (others => '0');
717 
  addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
718 
  addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
719 
 
720 
  a9 : if abits <= 9 generate
721 
    x : for i in 0 to ((dbits-1)/36) generate
722 
      r0 : RAMB16_S36_S36 port map (
723 
          do1(((i+1)*36)-5 downto i*36), do1(((i+1)*36)-1 downto i*36+32),
724 
          do2(((i+1)*36)-5 downto i*36), do2(((i+1)*36)-1 downto i*36+32),
725 
          addr1(8 downto 0), clk1,
726 
          di1(((i+1)*36)-5 downto i*36), di1(((i+1)*36)-1 downto i*36+32),
727 
          enable1, gnd, write1, addr2(8 downto 0), clk2,
728 
          di2(((i+1)*36)-5 downto i*36), di2(((i+1)*36)-1 downto i*36+32),
729 
          enable2, gnd, write2);
730 
    end generate;
731 
  end generate;
732 
 
733 
  a10 : if abits = 10 generate
734 
    x : for i in 0 to ((dbits-1)/18) generate
735 
      r0 : RAMB16_S18_S18 port map (
736 
          do1(((i+1)*18)-3 downto i*18), do1(((i+1)*18)-1 downto i*18+16),
737 
          do2(((i+1)*18)-3 downto i*18), do2(((i+1)*18)-1 downto i*18+16),
738 
          addr1(9 downto 0), clk1,
739 
          di1(((i+1)*18)-3 downto i*18), di1(((i+1)*18)-1 downto i*18+16),
740 
          enable1, gnd, write1, addr2(9 downto 0), clk2,
741 
          di2(((i+1)*18)-3 downto i*18), di2(((i+1)*18)-1 downto i*18+16),
742 
          enable2, gnd, write2);
743 
    end generate;
744 
  end generate;
745 
 
746 
end;
747 
 
748 
LIBRARY ieee;
749 
use IEEE.std_logic_1164.all;
750 
use work.leon_iface.all;
751 
use work.tech_virtex2.all;
752 
 
753 
entity virtex2_regfile is
754 
  generic (
755 
    rftype : integer := 1;
756 
    abits : integer := 8; dbits : integer := 32; words : integer := 128
757 
  );
758 
  port (
759 
    rst      : in std_logic;
760 
    clk      : in std_logic;
761 
    clkn     : in std_logic;
762 
    rfi      : in rf_in_type;
763 
    rfo      : out rf_out_type);
764 
end;
765 
 
766 
architecture behav of virtex2_regfile is
767 
 
768 
signal vcc : std_logic;
769 
signal gnd : std_logic_vector(127 downto 0);
770 
begin
771 
  vcc <= '1'; gnd <= (others => '0');
772 
 
773 
  rf0 : if rftype = 1 generate
774 
    r0 : virtex2_dpram generic map (abits, dbits)
775 
      port map (
776 
        rfi.rd1addr((abits -1) downto 0), clkn, gnd((dbits -1) downto 0),
777 
        rfo.data1((dbits -1) downto 0), vcc, gnd(0),
778 
        rfi.wraddr((abits -1) downto 0), clkn, rfi.wrdata((dbits -1) downto 0),
779 
        open, rfi.wren, rfi.wren);
780 
    r1 : virtex2_dpram generic map (abits, dbits)
781 
      port map (
782 
        rfi.rd2addr((abits -1) downto 0), clkn, gnd((dbits -1) downto 0),
783 
        rfo.data2((dbits -1) downto 0), vcc, gnd(0),
784 
        rfi.wraddr((abits -1) downto 0), clkn, rfi.wrdata((dbits -1) downto 0),
785 
        open, rfi.wren, rfi.wren);
786 
  end generate;
787 
 
788 
  rf1 : if rftype = 2 generate
789 
    r0 : virtex2_dpram generic map (abits, dbits)
790 
      port map (
791 
        rfi.rd1addr((abits -1) downto 0), clkn, gnd((dbits -1) downto 0),
792 
        rfo.data1((dbits -1) downto 0), vcc, gnd(0),
793 
        rfi.wraddr((abits -1) downto 0), clk, rfi.wrdata((dbits -1) downto 0),
794 
        open, rfi.wren, rfi.wren);
795 
    r1 : virtex2_dpram generic map (abits, dbits)
796 
      port map (
797 
        rfi.rd2addr((abits -1) downto 0), clkn, gnd((dbits -1) downto 0),
798 
        rfo.data2((dbits -1) downto 0), vcc, gnd(0),
799 
        rfi.wraddr((abits -1) downto 0), clk, rfi.wrdata((dbits -1) downto 0),
800 
        open, rfi.wren, rfi.wren);
801 
  end generate;
802 
end;
803 
 
804 
LIBRARY ieee;
805 
use IEEE.std_logic_1164.all;
806 
use work.leon_iface.all;
807 
use work.virtex2_complib.all;
808 
 
809 
entity virtex2_regfile_cp is
810 
  generic (
811 
    abits : integer := 4; dbits : integer := 32; words : integer := 16
812 
  );
813 
  port (
814 
    rst      : in std_logic;
815 
    clk      : in std_logic;
816 
    rfi      : in rf_cp_in_type;
817 
    rfo      : out rf_cp_out_type);
818 
end;
819 
 
820 
architecture behav of virtex2_regfile_cp is
821 
 
822 
signal vcc : std_logic;
823 
signal do1, do2, di1, di2 : std_logic_vector(129 downto 0);
824 
signal ra1, ra2, wa : std_logic_vector(19 downto 0);
825 
signal gnd : std_logic_vector(31 downto 0);
826 
begin
827 
  vcc <= '1'; gnd <= (others => '0');
828 
  rfo.data1 <= do1(dbits-1 downto 0); rfo.data2 <= do2(dbits-1 downto 0);
829 
  di1(dbits-1 downto 0) <= rfi.wrdata; di1(129 downto dbits) <= (others => '0');
830 
  di2(129 downto 0) <= (others => '0');
831 
  ra1(abits-1 downto 0) <= rfi.rd1addr; ra1(19 downto abits) <= (others => '0');
832 
  ra2(abits-1 downto 0) <= rfi.rd2addr; ra2(19 downto abits) <= (others => '0');
833 
  wa(abits-1 downto 0) <= rfi.wraddr; wa(19 downto abits) <= (others => '0');
834 
 
835 
  a9 : if abits <= 9 generate
836 
      x : for i in 0 to ((dbits-1)/36) generate
837 
        r0 : RAMB16_S36_S36 port map ( do1(((i+1)*36)-5 downto i*36),
838 
          do1(((i+1)*36)-1 downto i*36+32), open, open, ra1(8 downto 0), clk,
839 
          gnd(31 downto 0), gnd(3 downto 0), vcc, gnd(0), gnd(0),
840 
          wa(8 downto 0), clk, di1(((i+1)*36)-5 downto i*36),
841 
          di1(((i+1)*36)-1 downto i*36+32), vcc, gnd(0), rfi.wren);
842 
        r1 : RAMB16_S36_S36 port map ( do2(((i+1)*36)-5 downto i*36),
843 
          do2(((i+1)*36)-1 downto i*36+32), open, open, ra2(8 downto 0), clk,
844 
          gnd(31 downto 0), gnd(3 downto 0), vcc, gnd(0), gnd(0),
845 
          wa(8 downto 0), clk, di1(((i+1)*36)-5 downto i*36),
846 
          di1(((i+1)*36)-1 downto i*36+32), vcc, gnd(0), rfi.wren);
847 
      end generate;
848 
  end generate;
849 
end;
850 
 
851 
------------------------------------------------------------------
852 
-- Virtex2 clock generator ---------------------------------------
853 
------------------------------------------------------------------
854 
 
855 
library IEEE;
856 
use IEEE.std_logic_1164.all;
857 
use work.leon_target.all;
858 
use work.leon_iface.all;
859 
use work.leon_config.all;
860 
--library unisim;
861 
--use unisim.vcomponents.all;
862 
 
863 
library IEEE;
864 
use IEEE.std_logic_1164.all;
865 
 
866 
entity virtex2_clkgen is
867 
  generic ( clk_mul : integer := 1 ; clk_div : integer := 1);
868 
  port (
869 
    clkin   : in  std_logic;
870 
    pciclkin: in  std_logic;
871 
    clk     : out std_logic;                    -- main clock
872 
    clkn    : out std_logic;                    -- inverted main clock
873 
    sdclk   : out std_logic;                    -- SDRAM clock
874 
    pciclk  : out std_logic;                    -- PCI clock
875 
    cgi     : in clkgen_in_type;
876 
    cgo     : out clkgen_out_type
877 
  );
878 
end;
879 
 
880 
architecture struct of virtex2_clkgen is
881 
 
882 
--  attribute CLKFX_MULTIPLY : string;
883 
--  attribute CLKFX_DIVIDE : string;
884 
  attribute CLKIN_PERIOD : string;
885 
--
886 
--  attribute CLKFX_MULTIPLY of dll0: label is "5";
887 
--  attribute CLKFX_DIVIDE of dll0: label is "4";
888 
  attribute CLKIN_PERIOD of dll0: label is "25";
889 
--
890 
--  attribute CLKFX_MULTIPLY of dll1: label is "4";
891 
--  attribute CLKFX_DIVIDE of dll1: label is "4";
892 
--  attribute CLKIN_PERIOD of dll1: label is "25";
893 
--
894 
 
895 
component DCM
896 
  generic (
897 
    CLKFX_MULTIPLY : integer := 1 ;
898 
    CLKFX_DIVIDE : integer := 1
899 
  );
900 
  port (
901 
    CLKFB    : in  std_logic;
902 
    CLKIN    : in  std_logic;
903 
    DSSEN    : in  std_logic;
904 
    PSCLK    : in  std_logic;
905 
    PSEN     : in  std_logic;
906 
    PSINCDEC : in  std_logic;
907 
    RST      : in  std_logic;
908 
    CLK0     : out std_logic;
909 
    CLK90    : out std_logic;
910 
    CLK180   : out std_logic;
911 
    CLK270   : out std_logic;
912 
    CLK2X    : out std_logic;
913 
    CLK2X180 : out std_logic;
914 
    CLKDV    : out std_logic;
915 
    CLKFX    : out std_logic;
916 
    CLKFX180 : out std_logic;
917 
    LOCKED   : out std_logic;
918 
    PSDONE   : out std_logic;
919 
    STATUS   : out std_logic_vector (7 downto 0));
920 
end component;
921 
 
922 
component IBUFG port ( O : out std_logic; I : in std_logic); end component;
923 
component BUFG port ( O : out std_logic; I : in std_logic); end component;
924 
component IBUFG_PCI33_3 port ( O : out std_logic; I : in std_logic); end component;
925 
component BUFGDLL port ( O : out std_logic; I : in std_logic); end component;
926 
component OBUF_F_12 port( O : out std_ulogic; I : in  std_ulogic ); end component;
927 
 
928 
signal gnd, Clk_i, Clk_j, Clk_k, Clk_l, Clk_m, dll0rst, dll0lock, dll1lock, dll1rst : std_logic;
929 
signal Clk0B, Clk_FB, Clkint, pciclkint, sdclki : std_logic;
930 
 
931 
begin
932 
 
933 
  gnd <= '0'; clk <= clk_i; clkn <= clk_m;
934 
 
935 
  c0 : if not PCI_SYSCLK generate
936 
    ibufg0 : IBUFG port map (I => Clkin, O => Clkint);
937 
  end generate;
938 
  c1 : if PCI_SYSCLK generate
939 
    ibufg0 : IBUFG port map (I => pciclkin, O => Clkint);
940 
  end generate;
941 
 
942 
  c2 : if PCIEN generate
943 
    p0 : if PCI_CLKDLL generate
944 
      u0 : IBUFG port map (I => pciclkin, O => pciclkint);
945 
      u1 : BUFGDLL port map (O => pciclk, I => pciclkint);
946 
    end generate;
947 
    p1 : if not PCI_CLKDLL generate
948 
      u0 : if not PCI_SYSCLK generate
949 
        u1 : BUFG port map (I => pciclkin, O => pciclkint);
950 
      end generate;
951 
      pciclk <= clk_i when PCI_SYSCLK else pciclkint;
952 
    end generate;
953 
  end generate;
954 
  c3 : if not PCIEN generate
955 
    pciclk <= Clkint;
956 
  end generate;
957 
 
958 
  bufg0 : BUFG port map (I => Clk0B, O => Clk_i);
959 
  bufg1 : BUFG port map (I => Clk_j, O => Clk_k);
960 
  bufg2 : BUFG port map (I => Clk_l, O => Clk_m);
961 
  ibufg1 : IBUFG port map (I => cgi.pllref, O => Clk_FB);
962 
  dll0rst <= not cgi.pllrst;
963 
  dll0 : DCM
964 
    generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
965 
    port map ( CLKIN => Clkint, CLKFB => Clk_k, DSSEN => gnd, PSCLK => gnd,
966 
    PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => Clk_j,
967 
    CLKFX => Clk0B, CLKFX180 => Clk_l, LOCKED => dll0lock);
968 
 
969 
  sd0 : if SDRAMEN and not SDINVCLK generate
970 
    dll1rst <= not dll0lock; cgo.clklock <= dll1lock;
971 
    dll1 : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
972 
      port map ( CLKIN => Clk_i, CLKFB => Clk_FB, DSSEN => gnd, PSCLK => gnd,
973 
      PSEN => gnd, PSINCDEC => gnd, RST => dll1rst, CLK0 => sdclki,
974 
      LOCKED => dll1lock);
975 
  end generate;
976 
 
977 
  sd1 : if not (SDRAMEN and not SDINVCLK) generate
978 
    sdclki <= not clk_i; cgo.clklock <= dll0lock;
979 
  end generate;
980 
 
981 
  sd2 : if SDRAMEN generate
982 
    sdbuf : OBUF_F_12 port map (I => sdclki, O => sdclk);
983 
  end generate;
984 
  sd3 : if not SDRAMEN generate sdclk <= sdclki; end generate;
985 
 
986 
  cgo.pcilock <= '1';
987 
 
988 
end;
989 
 
990 
 
991 
 
992 
 
993 
 
994 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.