OpenCores
URL https://opencores.org/ocsvn/core_arm/core_arm/trunk

Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [vsim/] [icache] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 tarookumic
onerror {resume}
2
quietly WaveActivateNextPane {} 0
3
add wave -noupdate -divider -height 50 ICACHE
4
add wave -noupdate -format Logic -label o.hold -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/o.hold
5
add wave -noupdate -format Literal -label r.state -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/r.state
6
add wave -noupdate -divider in
7
add wave -noupdate -format Literal -label t.pc_r -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/i.pc_r
8
add wave -noupdate -format Logic -label t.bra_r -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/i.bra_r
9
add wave -noupdate -format Logic -label i.annul -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/i.annul
10
add wave -noupdate -divider { }
11
add wave -noupdate -format Logic -label t.reqinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/cdbg.dbg.reqinsn
12
add wave -noupdate -format Logic -label t.hit -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/cdbg.dbg.hit
13
add wave -noupdate -format Logic -label t.valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/cdbg.dbg.valid
14
add wave -noupdate -divider out
15
add wave -noupdate -format Literal -label .data -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/o.dat_line_v.data
16
add wave -noupdate -format Logic -label .mstrobe -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/o.mstrobe
17
add wave -noupdate -divider { }
18
add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/rst
19
add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/clk
20
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/hold
21
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/i
22
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/o
23
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/ctrl
24
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/icmo
25
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/icmi
26
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/mcio
27
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/mcii
28
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/r
29
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/c
30
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/rdbg
31
add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/cache0/ic0/cdbg
32
add wave -noupdate -divider { }
33
TreeUpdate [SetDefaultTree]
34
WaveRestoreCursors {9240 ns}
35
WaveRestoreZoom {8215 ns} {9953 ns}
36
configure wave -namecolwidth 150
37
configure wave -valuecolwidth 100
38
configure wave -justifyvalue left
39
configure wave -signalnamewidth 0
40
configure wave -snapdistance 10
41
configure wave -datasetprefix 0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.