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URL https://opencores.org/ocsvn/core_arm/core_arm/trunk

Subversion Repositories core_arm

[/] [core_arm/] [trunk/] [vsim/] [sctrl] - Blame information for rev 4

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Line No. Rev Author Line
1 2 tarookumic
onerror {resume}
2
quietly WaveActivateNextPane {} 0
3
add wave -noupdate -divider -height 50 {SYSCTRL Coprocessor}
4
add wave -noupdate -format Logic -label i.fromprdr_nextinsn_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/i.fromprdr_nextinsn_v
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add wave -noupdate -divider FESTG
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add wave -noupdate -format Literal -label .decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.de.insn.decinsn
7
add wave -noupdate -format Logic -label .valid -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.de.insn.valid
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add wave -noupdate -divider lock
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add wave -noupdate -format Literal -label .r1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.regs.r1
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add wave -noupdate -format Logic -label r.lock.r1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.regslock(1)
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add wave -noupdate -format Literal -label .r2 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.regs.r2
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add wave -noupdate -format Logic -label r.lock.r2 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.regslock(2)
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add wave -noupdate -divider DESTG
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add wave -noupdate -format Literal -label r.decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.de.insn.decinsn
15
add wave -noupdate -format Literal -label r.cr1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.de.insn.cr1
16
add wave -noupdate -format Logic -label o.busy -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/o.cpde_prdr.busy
17
add wave -noupdate -format Logic -label o.last -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/o.cpde_prdr.last
18
add wave -noupdate -format Logic -label o.accept -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/o.cpde_prdr.accept
19
add wave -noupdate -format Logic -label o.active -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/o.cpde_prdr.active
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add wave -noupdate -divider EXSTG
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add wave -noupdate -format Literal -label r.decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.ex.insn.decinsn
22
add wave -noupdate -format Literal -label r.cr1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.ex.insn.cr1
23
add wave -noupdate -format Literal -label o.data -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/o.cpex_prrr.data
24
add wave -noupdate -format Logic -label o.lock -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/o.cpex_prrr.lock
25
add wave -noupdate -divider WRSTG
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add wave -noupdate -format Literal -label i.fromprwr_data_v -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/i.fromprwr_data_v
27
add wave -noupdate -format Literal -label .decinsn -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.wr(0).insn.decinsn
28
add wave -noupdate -format Literal -label .cr1 -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r.wr(0).insn.cr1
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add wave -noupdate -divider { }
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add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/rst
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add wave -noupdate -format Logic -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/clk
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add wave -noupdate -format Literal -radix hexadecimal -expand /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/i
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add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/o
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add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/r
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add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/c
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add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/rdbg
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add wave -noupdate -format Literal -radix hexadecimal /tbench_config/tb0/c0/carm0/socarm/arm0/arm0/cpsys0/cdbg
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {8860 ns}
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WaveRestoreZoom {0 ns} {2588 ns}
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 0
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configure wave -snapdistance 10
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configure wave -datasetprefix 0

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