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[/] [cortexi/] [trunk/] [CortexI.vhd] - Blame information for rev 3

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Line No. Rev Author Line
1 3 riedelx 
LIBRARY ieee;
2 
use IEEE.STD_LOGIC_1164.ALL;
3 
use IEEE.STD_LOGIC_ARITH.ALL;
4 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
5 
 
6 
use work.CortexIinclude.ALL;
7 
 
8 
Library UNISIM;
9 
use UNISIM.vcomponents.all;
10 
 
11 
ENTITY CortexI IS
12 
   PORT(
13 
     clk     : in  std_logic;
14 
     rst     : in  std_logic;
15 
     irq     : in  std_logic;
16 
     addr    : out std_logic_vector(31 downto 0);
17 
     wrl     : out std_logic;
18 
     wrh     : out std_logic;
19 
     datain  : in  std_logic_vector(15 downto 0);
20 
     dataout : out std_logic_vector(15 downto 0)
21 
   );
22 
END CortexI;
23 
 
24 
ARCHITECTURE behavior OF CortexI IS
25 
 
26 
  constant STATE_FETCH  : std_logic_vector(6 downto 0) := "0000000";
27 
  constant STATE_READ1  : std_logic_vector(6 downto 0) := "0000001";
28 
  constant STATE_READ2  : std_logic_vector(6 downto 0) := "0000010";
29 
  constant STATE_WRITE1 : std_logic_vector(6 downto 0) := "0000011";
30 
  constant STATE_WRITE2 : std_logic_vector(6 downto 0) := "0000100";
31 
  constant STATE_RD0L   : std_logic_vector(6 downto 0) := "0000101";
32 
  constant STATE_RD0H   : std_logic_vector(6 downto 0) := "0000110";
33 
  constant STATE_RD1L   : std_logic_vector(6 downto 0) := "0000111";
34 
  constant STATE_RD1H   : std_logic_vector(6 downto 0) := "0001000";
35 
  constant STATE_RD2L   : std_logic_vector(6 downto 0) := "0001001";
36 
  constant STATE_RD2H   : std_logic_vector(6 downto 0) := "0001010";
37 
  constant STATE_RD3L   : std_logic_vector(6 downto 0) := "0001011";
38 
  constant STATE_RD3H   : std_logic_vector(6 downto 0) := "0001100";
39 
  constant STATE_RD4L   : std_logic_vector(6 downto 0) := "0001101";
40 
  constant STATE_RD4H   : std_logic_vector(6 downto 0) := "0001110";
41 
  constant STATE_RD5L   : std_logic_vector(6 downto 0) := "0001111";
42 
  constant STATE_RD5H   : std_logic_vector(6 downto 0) := "0010000";
43 
  constant STATE_RD6L   : std_logic_vector(6 downto 0) := "0010001";
44 
  constant STATE_RD6H   : std_logic_vector(6 downto 0) := "0010010";
45 
  constant STATE_RD7L   : std_logic_vector(6 downto 0) := "0010011";
46 
  constant STATE_RD7H   : std_logic_vector(6 downto 0) := "0010100";
47 
  constant STATE_RDPL   : std_logic_vector(6 downto 0) := "0010101";
48 
  constant STATE_RDPH   : std_logic_vector(6 downto 0) := "0010110";
49 
  constant STATE_WR0L   : std_logic_vector(6 downto 0) := "0010111";
50 
  constant STATE_WR0H   : std_logic_vector(6 downto 0) := "0011000";
51 
  constant STATE_WR1L   : std_logic_vector(6 downto 0) := "0011001";
52 
  constant STATE_WR1H   : std_logic_vector(6 downto 0) := "0011010";
53 
  constant STATE_WR2L   : std_logic_vector(6 downto 0) := "0011011";
54 
  constant STATE_WR2H   : std_logic_vector(6 downto 0) := "0011100";
55 
  constant STATE_WR3L   : std_logic_vector(6 downto 0) := "0011101";
56 
  constant STATE_WR3H   : std_logic_vector(6 downto 0) := "0011110";
57 
  constant STATE_WR4L   : std_logic_vector(6 downto 0) := "0011111";
58 
  constant STATE_WR4H   : std_logic_vector(6 downto 0) := "0100000";
59 
  constant STATE_WR5L   : std_logic_vector(6 downto 0) := "0100001";
60 
  constant STATE_WR5H   : std_logic_vector(6 downto 0) := "0100010";
61 
  constant STATE_WR6L   : std_logic_vector(6 downto 0) := "0100011";
62 
  constant STATE_WR6H   : std_logic_vector(6 downto 0) := "0100100";
63 
  constant STATE_WR7L   : std_logic_vector(6 downto 0) := "0100101";
64 
  constant STATE_WR7H   : std_logic_vector(6 downto 0) := "0100110";
65 
  constant STATE_WRPL   : std_logic_vector(6 downto 0) := "0100111";
66 
  constant STATE_WRPH   : std_logic_vector(6 downto 0) := "0101000";
67 
  constant STATE_RESET0 : std_logic_vector(6 downto 0) := "0101001";
68 
  constant STATE_RESET1 : std_logic_vector(6 downto 0) := "0101010";
69 
  constant STATE_RESET2 : std_logic_vector(6 downto 0) := "0101011";
70 
  constant STATE_RESET3 : std_logic_vector(6 downto 0) := "0101100";
71 
  constant STATE_IRQ    : std_logic_vector(6 downto 0) := "0101101";
72 
  constant STATE_IRQ1   : std_logic_vector(6 downto 0) := "0101110";
73 
  constant STATE_IRQ2   : std_logic_vector(6 downto 0) := "0101111";
74 
  constant STATE_IRQ3   : std_logic_vector(6 downto 0) := "0110000";
75 
  constant STATE_IRQ4   : std_logic_vector(6 downto 0) := "0110001";
76 
  constant STATE_IRQ5   : std_logic_vector(6 downto 0) := "0110010";
77 
  constant STATE_IRQ6   : std_logic_vector(6 downto 0) := "0110011";
78 
  constant STATE_IRQ7   : std_logic_vector(6 downto 0) := "0110100";
79 
  constant STATE_IRQ8   : std_logic_vector(6 downto 0) := "0110101";
80 
  constant STATE_IRQ9   : std_logic_vector(6 downto 0) := "0110110";
81 
  constant STATE_IRQ10  : std_logic_vector(6 downto 0) := "0110111";
82 
  constant STATE_IRQ11  : std_logic_vector(6 downto 0) := "0111000";
83 
  constant STATE_IRQ12  : std_logic_vector(6 downto 0) := "0111001";
84 
  constant STATE_IRQ13  : std_logic_vector(6 downto 0) := "0111010";
85 
  constant STATE_IRQ14  : std_logic_vector(6 downto 0) := "0111011";
86 
  constant STATE_IRQ15  : std_logic_vector(6 downto 0) := "0111100";
87 
  constant STATE_IRQ16  : std_logic_vector(6 downto 0) := "0111101";
88 
  constant STATE_IRQ17  : std_logic_vector(6 downto 0) := "0111110";
89 
  constant STATE_RET    : std_logic_vector(6 downto 0) := "0111111";
90 
  constant STATE_RET1   : std_logic_vector(6 downto 0) := "1000000";
91 
  constant STATE_RET2   : std_logic_vector(6 downto 0) := "1000001";
92 
  constant STATE_RET3   : std_logic_vector(6 downto 0) := "1000010";
93 
  constant STATE_RET4   : std_logic_vector(6 downto 0) := "1000011";
94 
  constant STATE_RET5   : std_logic_vector(6 downto 0) := "1000100";
95 
  constant STATE_RET6   : std_logic_vector(6 downto 0) := "1000101";
96 
  constant STATE_RET7   : std_logic_vector(6 downto 0) := "1000110";
97 
  constant STATE_RET8   : std_logic_vector(6 downto 0) := "1000111";
98 
  constant STATE_RET9   : std_logic_vector(6 downto 0) := "1001000";
99 
  constant STATE_RET10  : std_logic_vector(6 downto 0) := "1001001";
100 
  constant STATE_RET11  : std_logic_vector(6 downto 0) := "1001010";
101 
  constant STATE_RET12  : std_logic_vector(6 downto 0) := "1001011";
102 
  constant STATE_RET13  : std_logic_vector(6 downto 0) := "1001100";
103 
  constant STATE_RET14  : std_logic_vector(6 downto 0) := "1001101";
104 
  constant STATE_RET15  : std_logic_vector(6 downto 0) := "1001110";
105 
  constant STATE_RET16  : std_logic_vector(6 downto 0) := "1001111";
106 
  constant STATE_RET17  : std_logic_vector(6 downto 0) := "1010000";
107 
 
108 
  constant CODE_LSL1   : std_logic_vector(6 downto 0) := "0000000";
109 
  constant CODE_LSR1   : std_logic_vector(6 downto 0) := "0000001";
110 
  constant CODE_ASR1   : std_logic_vector(6 downto 0) := "0000010";
111 
  constant CODE_ADD1   : std_logic_vector(6 downto 0) := "0000011";
112 
  constant CODE_SUB1   : std_logic_vector(6 downto 0) := "0000100";
113 
  constant CODE_ADD2   : std_logic_vector(6 downto 0) := "0000110";
114 
  constant CODE_SUB2   : std_logic_vector(6 downto 0) := "0000111";
115 
  constant CODE_MOV1   : std_logic_vector(6 downto 0) := "0001000";
116 
  constant CODE_CMP1   : std_logic_vector(6 downto 0) := "0001001";
117 
  constant CODE_ADD3   : std_logic_vector(6 downto 0) := "0001010";
118 
  constant CODE_SUB3   : std_logic_vector(6 downto 0) := "0001011";
119 
  constant CODE_AND1   : std_logic_vector(6 downto 0) := "0001100";
120 
  constant CODE_EOR1   : std_logic_vector(6 downto 0) := "0001101";
121 
  constant CODE_LSL2   : std_logic_vector(6 downto 0) := "0001110";
122 
  constant CODE_LSR2   : std_logic_vector(6 downto 0) := "0001111";
123 
  constant CODE_ASR2   : std_logic_vector(6 downto 0) := "0010000";
124 
  constant CODE_ADC1   : std_logic_vector(6 downto 0) := "0010001";
125 
  constant CODE_SBC1   : std_logic_vector(6 downto 0) := "0010010";
126 
  constant CODE_ROR1   : std_logic_vector(6 downto 0) := "0010011";
127 
  constant CODE_TST1   : std_logic_vector(6 downto 0) := "0010100";
128 
  constant CODE_NEG1   : std_logic_vector(6 downto 0) := "0010101";
129 
  constant CODE_CMP2   : std_logic_vector(6 downto 0) := "0010110";
130 
  constant CODE_CMN1   : std_logic_vector(6 downto 0) := "0010111";
131 
  constant CODE_ORR1   : std_logic_vector(6 downto 0) := "0011000";
132 
  constant CODE_MUL1   : std_logic_vector(6 downto 0) := "0011001";
133 
  constant CODE_BIC1   : std_logic_vector(6 downto 0) := "0011010";
134 
  constant CODE_MVN1   : std_logic_vector(6 downto 0) := "0011011";
135 
  constant CODE_ADD4   : std_logic_vector(6 downto 0) := "0011100";
136 
  constant CODE_CMP3   : std_logic_vector(6 downto 0) := "0011101";
137 
  constant CODE_CPY1   : std_logic_vector(6 downto 0) := "0011110";
138 
  constant CODE_BX1    : std_logic_vector(6 downto 0) := "0011111";
139 
  constant CODE_LDR1   : std_logic_vector(6 downto 0) := "0100000";
140 
  constant CODE_STR1   : std_logic_vector(6 downto 0) := "0100001";
141 
  constant CODE_STRH1  : std_logic_vector(6 downto 0) := "0100010";
142 
  constant CODE_STRB1  : std_logic_vector(6 downto 0) := "0100011";
143 
  constant CODE_LDRSB1 : std_logic_vector(6 downto 0) := "0100100";
144 
  constant CODE_LDR2   : std_logic_vector(6 downto 0) := "0100101";
145 
  constant CODE_LDRH1  : std_logic_vector(6 downto 0) := "0100110";
146 
  constant CODE_LDRB1  : std_logic_vector(6 downto 0) := "0100111";
147 
  constant CODE_LDRSH1 : std_logic_vector(6 downto 0) := "0101000";
148 
  constant CODE_STR2   : std_logic_vector(6 downto 0) := "0101001";
149 
  constant CODE_LDR3   : std_logic_vector(6 downto 0) := "0101010";
150 
  constant CODE_STRB2  : std_logic_vector(6 downto 0) := "0101011";
151 
  constant CODE_LDRB2  : std_logic_vector(6 downto 0) := "0101100";
152 
  constant CODE_STRH2  : std_logic_vector(6 downto 0) := "0101101";
153 
  constant CODE_LDRH2  : std_logic_vector(6 downto 0) := "0101110";
154 
  constant CODE_STR3   : std_logic_vector(6 downto 0) := "0101111";
155 
  constant CODE_LDR4   : std_logic_vector(6 downto 0) := "0110000";
156 
  constant CODE_ADD5   : std_logic_vector(6 downto 0) := "0110001";
157 
  constant CODE_ADD6   : std_logic_vector(6 downto 0) := "0110010";
158 
  constant CODE_ADD7   : std_logic_vector(6 downto 0) := "0110011";
159 
  constant CODE_SUB4   : std_logic_vector(6 downto 0) := "0110100";
160 
  constant CODE_SXTH1  : std_logic_vector(6 downto 0) := "0110101";
161 
  constant CODE_SXTB1  : std_logic_vector(6 downto 0) := "0110110";
162 
  constant CODE_UXTH1  : std_logic_vector(6 downto 0) := "0110111";
163 
  constant CODE_UXTB1  : std_logic_vector(6 downto 0) := "0111000";
164 
  constant CODE_PUSH1  : std_logic_vector(6 downto 0) := "0111001";
165 
  constant CODE_POP1   : std_logic_vector(6 downto 0) := "0111010";
166 
  constant CODE_STMIA1 : std_logic_vector(6 downto 0) := "0111011";
167 
  constant CODE_LDMIA1 : std_logic_vector(6 downto 0) := "0111100";
168 
  constant CODE_BCC1   : std_logic_vector(6 downto 0) := "0111101";
169 
  constant CODE_SWI1   : std_logic_vector(6 downto 0) := "0111110";
170 
  constant CODE_B1     : std_logic_vector(6 downto 0) := "0111111";
171 
  constant CODE_BLX1   : std_logic_vector(6 downto 0) := "1000000";
172 
  constant CODE_BLX2   : std_logic_vector(6 downto 0) := "1000001";
173 
  constant CODE_BL1    : std_logic_vector(6 downto 0) := "1000010";
174 
  constant CODE_NOP    : std_logic_vector(6 downto 0) := "1000011";
175 
  constant CODE_XXX    : std_logic_vector(6 downto 0) := "1111111";
176 
 
177 
  constant N_FLAG : integer := 31;
178 
  constant Z_FLAG : integer := 30;
179 
  constant C_FLAG : integer := 29;
180 
  constant V_FLAG : integer := 28;
181 
 
182 
  constant WRITE_B_LOW   : std_logic_vector(3 downto 0) := "0000";
183 
  constant WRITE_B_HIGH  : std_logic_vector(3 downto 0) := "0001";
184 
  constant WRITE_H_BOTH  : std_logic_vector(3 downto 0) := "0010";
185 
  constant WRITE_H_LOW   : std_logic_vector(3 downto 0) := "0011";
186 
  constant WRITE_H_HIGH  : std_logic_vector(3 downto 0) := "0100";
187 
  constant WRITE_W_LOW   : std_logic_vector(3 downto 0) := "0101";
188 
  constant WRITE_W_HIGH  : std_logic_vector(3 downto 0) := "0110";
189 
  constant WRITE_W_LOWB  : std_logic_vector(3 downto 0) := "0111";
190 
  constant WRITE_W_MID   : std_logic_vector(3 downto 0) := "1000";
191 
  constant WRITE_W_HIGHB : std_logic_vector(3 downto 0) := "1001";
192 
 
193 
  constant ADDR_PC : std_logic_vector(1 downto 0) := "00";
194 
  constant ADDR_SP : std_logic_vector(1 downto 0) := "01";
195 
  constant ADDR_RS : std_logic_vector(1 downto 0) := "10";
196 
  constant ADDR_RT : std_logic_vector(1 downto 0) := "11";
197 
 
198 
 
199 
  type typeRegisters is array (0 to 15) of std_logic_vector(31 downto 0);
200 
 
201 
  signal theRegisters : typeRegisters;
202 
  signal cpsrRegister : std_logic_Vector(31 downto  0);
203 
  signal cpuState     : std_logic_vector( 6 downto  0);
204 
  signal opcode       : std_logic_vector(15 downto  0);
205 
  signal addrMux      : std_logic_vector( 1 downto  0);
206 
  signal address      : std_logic_vector(31 downto  0);
207 
  signal irq_d        : std_logic;
208 
  signal irqRequest   : std_logic;
209 
  signal writeL       : std_logic;
210 
  signal writeH       : std_logic;
211 
  signal shiftResult  : std_logic_vector(31 downto  0);
212 
  signal cyShiftOut   : std_logic;
213 
  signal shiftMode    : std_logic_vector( 2 downto  0);
214 
  signal shiftCount   : std_logic_vector( 4 downto  0);
215 
  signal shiftIn      : std_logic_vector(31 downto  0);
216 
  signal LDMread      : std_logic_vector( 7 downto  0);
217 
 
218 
  signal unitControl  : std_logic_vector( 6 downto  0);
219 
  signal unitControl2 : std_logic_vector( 6 downto  0);
220 
 
221 
  signal factor1      : std_logic_vector(31 downto  0);
222 
  signal factor2      : std_logic_vector(31 downto  0);
223 
  signal product      : std_logic_vector(63 downto  0);
224 
 
225 
  signal branch       : std_logic;
226 
 
227 
  signal datain20  : integer range 0 to 15;
228 
  signal datain53  : integer range 0 to 15;
229 
  signal datain86  : integer range 0 to 15;
230 
  signal datain108 : integer range 0 to 15;
231 
 
232 
  signal opcode20  : integer range 0 to 15;
233 
  signal opcode53  : integer range 0 to 15;
234 
  signal opcode86  : integer range 0 to 15;
235 
  signal opcode108 : integer range 0 to 15;
236 
 
237 
  component bshifter Port (
238 
           din   : in  std_logic_vector(31 downto 0);
239 
           size  : in  std_logic_vector( 1 downto 0);
240 
           mode  : in  std_logic_vector( 2 downto 0);
241 
           count : in  std_logic_vector( 4 downto 0);
242 
           cyOut : out std_logic;
243 
           dout  : out std_logic_vector(31 downto 0)
244 
         );
245 
  end component;
246 
 
247 
  component Multiplier   -- 32 x 32 = 64 bit unsigned product multiplier
248 
    port(a    : in  std_logic_vector(31 downto 0);  -- multiplicand
249 
         b    : in  std_logic_vector(31 downto 0);  -- multiplier
250 
         p    : out std_logic_vector(63 downto 0)); -- product
251 
  end component;
252 
 
253 
begin
254 
 
255 
  datain20  <= conv_integer("0" & datain( 2 downto 0));
256 
  datain53  <= conv_integer("0" & datain( 5 downto 3));
257 
  datain86  <= conv_integer("0" & datain( 8 downto 6));
258 
  datain108 <= conv_integer("0" & datain(10 downto 8));
259 
  opcode20  <= conv_integer("0" & opcode( 2 downto 0));
260 
  opcode53  <= conv_integer("0" & opcode( 5 downto 3));
261 
  opcode86  <= conv_integer("0" & opcode( 8 downto 6));
262 
  opcode108 <= conv_integer("0" & opcode(10 downto 8));
263 
 
264 
--#################################################################
265 
--  barrel shifter
266 
  shiftMode <= BS_LSL when (unitControl = CODE_LSL1) or (unitControl = CODE_LSL2) else
267 
               BS_LSR when (unitControl = CODE_LSR1) or (unitControl = CODE_LSR2) else
268 
               BS_ASR when (unitControl = CODE_ASR1) or (unitControl = CODE_ASR2) else
269 
               BS_ROR;
270 
  shiftCount <= datain(10 downto 6)
271 
       when (unitControl = CODE_LSL1) or (unitControl = CODE_LSR1) or (unitControl = CODE_ASR1) else
272 
            theRegisters(datain53)(4 downto 0);
273 
  shiftIn <= theRegisters(datain53)
274 
       when (unitControl = CODE_LSL1) or (unitControl = CODE_LSR1) or (unitControl = CODE_ASR1) else
275 
            theRegisters(datain20);
276 
  barrelShifter :  bshifter Port map(
277 
           din   => shiftIn,     --: in  std_logic_vector(31 downto 0);
278 
           size  => SIZE_32BIT,  --: in  std_logic_vector( 1 downto 0);
279 
           mode  => shiftMode,   --: in  std_logic_vector( 2 downto 0);
280 
           count => shiftCount,  --: in  std_logic_vector( 4 downto 0);
281 
           cyOut => cyShiftOut,  --: out std_logic;
282 
           dout  => shiftResult  --: out std_logic_vector(31 downto 0)
283 
         );
284 
 
285 
--#################################################################
286 
--  multiplier
287 
  multip : Multiplier Port map(
288 
           a => factor1,
289 
           b => factor2,
290 
           p => product
291 
         );
292 
  factor1 <= theRegisters(datain20);
293 
  factor2 <= theRegisters(datain53);
294 
 
295 
--#################################################################
296 
-- decodes instruction bits to control bits for other ARMT units
297 
  process(datain)
298 
  begin
299 
    case datain(15 downto 11) is
300 
      when "00000" =>    unitControl <= CODE_LSL1;
301 
      when "00001" =>    unitControl <= CODE_LSR1;
302 
      when "00010" =>    unitControl <= CODE_ASR1;
303 
      when "00011" =>
304 
        case datain(10 downto 9) is
305 
          when "00" =>   unitControl <= CODE_ADD1;
306 
          when "01" =>   unitControl <= CODE_SUB1;
307 
          when "10" =>   unitControl <= CODE_ADD2;
308 
          when "11" =>   unitControl <= CODE_SUB2;
309 
          when others => unitControl <= CODE_XXX;
310 
        end case;
311 
      when "00100" =>    unitControl <= CODE_MOV1;
312 
      when "00101" =>    unitControl <= CODE_CMP1;
313 
      when "00110" =>    unitControl <= CODE_ADD3;
314 
      when "00111" =>    unitControl <= CODE_SUB3;
315 
      when "01000" =>
316 
        if datain(10) = '0' then
317 
          case datain(9 downto 6) is
318 
            when "0000" => unitControl <= CODE_AND1;
319 
            when "0001" => unitControl <= CODE_EOR1;
320 
            when "0010" => unitControl <= CODE_LSL2;
321 
            when "0011" => unitControl <= CODE_LSR2;
322 
            when "0100" => unitControl <= CODE_ASR2;
323 
            when "0101" => unitControl <= CODE_ADC1;
324 
            when "0110" => unitControl <= CODE_SBC1;
325 
            when "0111" => unitControl <= CODE_ROR1;
326 
            when "1000" => unitControl <= CODE_TST1;
327 
            when "1001" => unitControl <= CODE_NEG1;
328 
            when "1010" => unitControl <= CODE_CMP2;
329 
            when "1011" => unitControl <= CODE_CMN1;
330 
            when "1100" => unitControl <= CODE_ORR1;
331 
            when "1101" => unitControl <= CODE_MUL1;
332 
            when "1110" => unitControl <= CODE_BIC1;
333 
            when "1111" => unitControl <= CODE_MVN1;
334 
            when others => unitControl <= CODE_XXX;
335 
          end case;
336 
        else
337 
          case datain(9 downto 8) is
338 
            when "00" => unitControl <= CODE_ADD4;
339 
            when "01" => unitControl <= CODE_CMP3;
340 
            when "10" => unitControl <= CODE_CPY1; -- MOV
341 
            when "11" => unitControl <= CODE_BX1;
342 
            when others => unitControl <= CODE_XXX;
343 
          end case;
344 
        end if;
345 
      when "01001" =>    unitControl <= CODE_LDR1;
346 
      when "01010" =>
347 
        case datain(10 downto 9) is
348 
          when "00" => unitControl <= CODE_STR1;
349 
          when "01" => unitControl <= CODE_STRH1;
350 
          when "10" => unitControl <= CODE_STRB1;
351 
          when "11" => unitControl <= CODE_LDRSB1;
352 
          when others =>     unitControl <= CODE_XXX;
353 
        end case;
354 
      when "01011" =>
355 
        case datain(10 downto 9) is
356 
          when "00" => unitControl <= CODE_LDR2;
357 
          when "01" => unitControl <= CODE_LDRH1;
358 
          when "10" => unitControl <= CODE_LDRB1;
359 
          when "11" => unitControl <= CODE_LDRSH1;
360 
          when others =>     unitControl <= CODE_XXX;
361 
        end case;
362 
      when "01100" =>    unitControl <= CODE_STR2;
363 
      when "01101" =>    unitControl <= CODE_LDR3;
364 
      when "01110" =>    unitControl <= CODE_STRB2;
365 
      when "01111" =>    unitControl <= CODE_LDRB2;
366 
      when "10000" =>    unitControl <= CODE_STRH2;
367 
      when "10001" =>    unitControl <= CODE_LDRH2;
368 
      when "10010" =>    unitControl <= CODE_STR3;
369 
      when "10011" =>    unitControl <= CODE_LDR4;
370 
      when "10100" =>    unitControl <= CODE_ADD5;
371 
      when "10101" =>    unitControl <= CODE_ADD6;
372 
      when "10110" =>
373 
        case datain(10 downto 7) is
374 
          when "0000" => unitControl <= CODE_ADD7;
375 
          when "0001" => unitControl <= CODE_SUB4;
376 
          when "0100" =>
377 
            if datain(6) = '0' then
378 
                         unitControl <= CODE_SXTH1;
379 
            else
380 
                         unitControl <= CODE_SXTB1;
381 
            end if;
382 
          when "0101" =>
383 
            if datain(6) = '0' then
384 
                         unitControl <= CODE_UXTH1;
385 
            else
386 
                         unitControl <= CODE_UXTB1;
387 
            end if;
388 
          when "1000" | "1001" | "1010" | "1011" =>
389 
                         unitControl <= CODE_PUSH1;
390 
          when others => unitControl <= CODE_XXX;
391 
        end case;
392 
      when "10111" =>
393 
        if datain(10 downto 8) = "100" or datain(10 downto 8) = "101" then
394 
                         unitControl <= CODE_POP1;
395 
        else
396 
                         unitControl <= CODE_NOP;
397 
        end if;
398 
      when "11000" =>    unitControl <= CODE_STMIA1;
399 
      when "11001" =>    unitControl <= CODE_LDMIA1;
400 
      when "11010" | "11011" =>
401 
--        if datain(11 downto 8) = "1111" then
402 
--                         unitControl <= CODE_SWI1;
403 
--        else
404 
                         unitControl <= CODE_BCC1;
405 
--        end if;
406 
      when "11100" =>    unitControl <= CODE_B1;
407 
      when "11101" =>    unitControl <= CODE_BLX1;
408 
      when "11110" =>    unitControl <= CODE_BLX2;
409 
      when "11111" =>    unitControl <= CODE_BL1;
410 
      when others =>     unitControl <= CODE_XXX;
411 
    end case; -- datain(15 downto 11)
412 
  end process;
413 
 
414 
  wrl  <= writeL;
415 
  wrH  <= writeH;
416 
--#################################################################
417 
--      address bus multiplexer
418 
  addr <= theRegisters(15) when addrMux = ADDR_PC else
419 
          theRegisters(13) when addrMux = ADDR_SP else
420 
          address;
421 
 
422 
--#################################################################
423 
--      check flags for branch
424 
  process(datain, cpsrRegister)
425 
  begin
426 
    case datain(11 downto 8) is
427 
      when "0000" => -- EQ
428 
        if cpsrRegister(Z_FLAG) = '1' then
429 
          branch <= '1';
430 
        else
431 
          branch <= '0';
432 
        end if;
433 
      when "0001" => -- NE
434 
        if cpsrRegister(Z_FLAG) = '0' then
435 
          branch <= '1';
436 
        else
437 
          branch <= '0';
438 
        end if;
439 
      when "0010" => -- CS
440 
        if cpsrRegister(C_FLAG) = '1' then
441 
          branch <= '1';
442 
        else
443 
          branch <= '0';
444 
        end if;
445 
      when "0011" => -- CC
446 
        if cpsrRegister(C_FLAG) = '0' then
447 
          branch <= '1';
448 
        else
449 
          branch <= '0';
450 
        end if;
451 
      when "0100" => -- MI
452 
        if cpsrRegister(N_FLAG) = '1' then
453 
          branch <= '1';
454 
        else
455 
          branch <= '0';
456 
        end if;
457 
      when "0101" => -- PL
458 
        if cpsrRegister(N_FLAG) = '0' then
459 
          branch <= '1';
460 
        else
461 
          branch <= '0';
462 
        end if;
463 
      when "0110" => -- VS
464 
        if cpsrRegister(V_FLAG) = '1' then
465 
          branch <= '1';
466 
        else
467 
          branch <= '0';
468 
        end if;
469 
      when "0111" => -- VC
470 
        if cpsrRegister(V_FLAG) = '0' then
471 
          branch <= '1';
472 
        else
473 
          branch <= '0';
474 
        end if;
475 
      when "1000" => -- HI
476 
        if cpsrRegister(C_FLAG) = '1' and cpsrRegister(Z_FLAG) = '0' then
477 
          branch <= '1';
478 
        else
479 
          branch <= '0';
480 
        end if;
481 
      when "1001" => -- LS
482 
        if cpsrRegister(C_FLAG) = '0' or cpsrRegister(Z_FLAG) = '1' then
483 
          branch <= '1';
484 
        else
485 
          branch <= '0';
486 
        end if;
487 
      when "1010" => -- GE
488 
        if cpsrRegister(N_FLAG) = cpsrRegister(V_FLAG) then
489 
          branch <= '1';
490 
        else
491 
          branch <= '0';
492 
        end if;
493 
      when "1011" => -- LT
494 
        if cpsrRegister(N_FLAG) /= cpsrRegister(V_FLAG) then
495 
          branch <= '1';
496 
        else
497 
          branch <= '0';
498 
        end if;
499 
      when "1100" => -- GT
500 
        if cpsrRegister(Z_FLAG) = '0' and (cpsrRegister(N_FLAG) = cpsrRegister(V_FLAG)) then
501 
          branch <= '1';
502 
        else
503 
          branch <= '0';
504 
        end if;
505 
      when "1101" => -- LE
506 
        if cpsrRegister(Z_FLAG) = '1' or (cpsrRegister(N_FLAG) /= cpsrRegister(V_FLAG)) then
507 
          branch <= '1';
508 
        else
509 
          branch <= '0';
510 
        end if;
511 
      when "1110" => -- AL
512 
        branch <= '1';
513 
      when others =>
514 
        branch <= '0';
515 
    end case; -- datain(11 downto 8)
516 
  end process;
517 
 
518 
--#################################################################
519 
-- ARMT cpu main state machine
520 
  process(rst, clk)
521 
    variable tres : std_logic_vector(32 downto 0);
522 
    variable tsum : std_logic_vector(31 downto 0);
523 
    variable op1  : std_logic;
524 
    variable op2  : std_logic;
525 
    variable opr  : std_logic;
526 
  begin
527 
    if rising_edge(clk) then
528 
      if rst = '0' then
529 
        theRegisters( 0) <= x"00000000";
530 
        theRegisters( 1) <= x"00000000";
531 
        theRegisters( 2) <= x"00000000";
532 
        theRegisters( 3) <= x"00000000";
533 
        theRegisters( 4) <= x"00000000";
534 
        theRegisters( 5) <= x"00000000";
535 
        theRegisters( 6) <= x"00000000";
536 
        theRegisters( 7) <= x"00000000";
537 
        theRegisters( 8) <= x"00000000";
538 
        theRegisters( 9) <= x"00000000";
539 
        theRegisters(10) <= x"00000000";
540 
        theRegisters(11) <= x"00000000";
541 
        theRegisters(12) <= x"00000000";
542 
        theRegisters(13) <= x"00000000"; -- SP
543 
        theRegisters(14) <= x"00000000"; -- LR
544 
        theRegisters(15) <= x"00000000"; -- PC
545 
        cpsrRegister     <= x"00000000";
546 
        cpuState <= STATE_RESET0;
547 
        writeL   <= '1';
548 
        writeH   <= '1';
549 
        LDMread  <= x"00";
550 
        addrMux  <= ADDR_PC;
551 
        address  <= x"00000000";
552 
        irq_d    <= '1';
553 
        irqRequest <= '0';
554 
        unitControl2 <= "0000000";
555 
      else
556 
        irq_d <= irq;
557 
        if (irq = '0') and (irq_d = '1') then --and (flagI = '0') then -- irq falling edge ?
558 
          irqRequest <= '1';
559 
        end if;
560 
        case cpuState is
561 
          when STATE_RESET0 => -- ##################################################
562 
            theRegisters(13)(15 downto 0) <= datain;  -- STACK low
563 
            theRegisters(15) <= theRegisters(15) + 2;
564 
            cpuState <= STATE_RESET1;
565 
          when STATE_RESET1 => -- ##################################################
566 
            theRegisters(13)(31 downto 16) <= datain; -- STACK high
567 
            theRegisters(15) <= theRegisters(15) + 2;
568 
            cpuState <= STATE_RESET2;
569 
          when STATE_RESET2 => -- ##################################################
570 
            address(15 downto 0) <= datain and x"FFFE"; -- PC low make even address
571 
            theRegisters(15) <= theRegisters(15) + 2;
572 
            cpuState <= STATE_RESET3;
573 
          when STATE_RESET3 => -- ##################################################
574 
            theRegisters(15) <= datain & address(15 downto 0); -- PC high
575 
            cpuState <= STATE_FETCH;
576 
          when STATE_IRQ =>  -- ####################################################
577 
            theRegisters(13) <= theRegisters(13) - 2;
578 
            dataout  <= cpsrRegister(15 downto 0);
579 
            cpuState <= STATE_IRQ1;
580 
          when STATE_IRQ1 =>  -- ####################################################
581 
            theRegisters(13) <= theRegisters(13) - 2;
582 
            dataout  <= theRegisters(15)(31 downto 16);
583 
            cpuState <= STATE_IRQ2;
584 
          when STATE_IRQ2 =>  -- ####################################################
585 
            theRegisters(13) <= theRegisters(13) - 2;
586 
            dataout  <= theRegisters(15)(15 downto 0);
587 
            cpuState <= STATE_IRQ3;
588 
          when STATE_IRQ3 =>  -- ####################################################
589 
            theRegisters(13) <= theRegisters(13) - 2;
590 
            dataout  <= theRegisters(14)(31 downto 16); -- ??? FFFFFFF9
591 
            cpuState <= STATE_IRQ4;
592 
          when STATE_IRQ4 =>  -- ####################################################
593 
            theRegisters(13) <= theRegisters(13) - 2;
594 
            dataout  <= theRegisters(14)(15 downto 0); -- ??? FFFFFFF9
595 
            cpuState <= STATE_IRQ5;
596 
          when STATE_IRQ5 =>  -- ####################################################
597 
            theRegisters(13) <= theRegisters(13) - 2;
598 
            dataout  <= theRegisters(12)(31 downto 16);
599 
            cpuState <= STATE_IRQ6;
600 
          when STATE_IRQ6 =>  -- ####################################################
601 
            theRegisters(13) <= theRegisters(13) - 2;
602 
            dataout  <= theRegisters(12)(15 downto 0);
603 
            cpuState <= STATE_IRQ7;
604 
          when STATE_IRQ7 =>  -- ####################################################
605 
            theRegisters(13) <= theRegisters(13) - 2;
606 
            dataout  <= theRegisters(3)(31 downto 16);
607 
            cpuState <= STATE_IRQ8;
608 
          when STATE_IRQ8 =>  -- ####################################################
609 
            theRegisters(13) <= theRegisters(13) - 2;
610 
            dataout  <= theRegisters(3)(15 downto 0);
611 
            cpuState <= STATE_IRQ9;
612 
          when STATE_IRQ9 =>  -- ####################################################
613 
            theRegisters(13) <= theRegisters(13) - 2;
614 
            dataout  <= theRegisters(2)(31 downto 16);
615 
            cpuState <= STATE_IRQ10;
616 
          when STATE_IRQ10 =>  -- ####################################################
617 
            theRegisters(13) <= theRegisters(13) - 2;
618 
            dataout  <= theRegisters(2)(15 downto 0);
619 
            cpuState <= STATE_IRQ11;
620 
          when STATE_IRQ11 =>  -- ####################################################
621 
            theRegisters(13) <= theRegisters(13) - 2;
622 
            dataout  <= theRegisters(1)(31 downto 16);
623 
            cpuState <= STATE_IRQ12;
624 
          when STATE_IRQ12 =>  -- ####################################################
625 
            theRegisters(13) <= theRegisters(13) - 2;
626 
            dataout  <= theRegisters(1)(15 downto 0);
627 
            cpuState <= STATE_IRQ13;
628 
          when STATE_IRQ13 =>  -- ####################################################
629 
            theRegisters(13) <= theRegisters(13) - 2;
630 
            dataout  <= theRegisters(0)(31 downto 16);
631 
            cpuState <= STATE_IRQ14;
632 
          when STATE_IRQ14 =>  -- ####################################################
633 
            theRegisters(13) <= theRegisters(13) - 2;
634 
            dataout  <= theRegisters(0)(15 downto 0);
635 
            cpuState <= STATE_IRQ15;
636 
          when STATE_IRQ15 =>  -- ####################################################
637 
            writeL <= '1';
638 
            writeH <= '1';
639 
            theRegisters(14) <= x"FFFFFFF9"; -- exception return value
640 
            address <= x"00000008";  -- NMI vector
641 
            addrMux <= ADDR_RS;
642 
            cpuState <= STATE_IRQ16;
643 
          when STATE_IRQ16 =>  -- ###################################################
644 
            theRegisters(15)(15 downto 0) <= datain and x"FFFE";
645 
            address <= address + 2;
646 
            cpuState <= STATE_IRQ17;
647 
          when STATE_IRQ17 =>  -- ###################################################
648 
            theRegisters(15)(31 downto 16) <= datain;
649 
            addrMux <= ADDR_PC;
650 
            cpuState <= STATE_FETCH;
651 
          when STATE_RET =>  -- #####################################################
652 
            addrMux <= ADDR_SP;
653 
            cpuState <= STATE_RET1;
654 
          when STATE_RET1 => -- #####################################################
655 
            theRegisters(0)(15 downto 0) <= datain;
656 
            theRegisters(13) <= theRegisters(13) + 2;
657 
            cpuState <= STATE_RET2;
658 
          when STATE_RET2 => -- #####################################################
659 
            theRegisters(0)(31 downto 16) <= datain;
660 
            theRegisters(13) <= theRegisters(13) + 2;
661 
            cpuState <= STATE_RET3;
662 
          when STATE_RET3 => -- #####################################################
663 
            theRegisters(1)(15 downto 0) <= datain;
664 
            theRegisters(13) <= theRegisters(13) + 2;
665 
            cpuState <= STATE_RET4;
666 
          when STATE_RET4 => -- #####################################################
667 
            theRegisters(1)(31 downto 16) <= datain;
668 
            theRegisters(13) <= theRegisters(13) + 2;
669 
            cpuState <= STATE_RET5;
670 
          when STATE_RET5 => -- #####################################################
671 
            theRegisters(2)(15 downto 0) <= datain;
672 
            theRegisters(13) <= theRegisters(13) + 2;
673 
            cpuState <= STATE_RET6;
674 
          when STATE_RET6 => -- #####################################################
675 
            theRegisters(2)(31 downto 16) <= datain;
676 
            theRegisters(13) <= theRegisters(13) + 2;
677 
            cpuState <= STATE_RET7;
678 
          when STATE_RET7 => -- #####################################################
679 
            theRegisters(3)(15 downto 0) <= datain;
680 
            theRegisters(13) <= theRegisters(13) + 2;
681 
            cpuState <= STATE_RET8;
682 
          when STATE_RET8 => -- #####################################################
683 
            theRegisters(3)(31 downto 16) <= datain;
684 
            theRegisters(13) <= theRegisters(13) + 2;
685 
            cpuState <= STATE_RET9;
686 
          when STATE_RET9 => -- #####################################################
687 
            theRegisters(12)(15 downto 0) <= datain;
688 
            theRegisters(13) <= theRegisters(13) + 2;
689 
            cpuState <= STATE_RET10;
690 
          when STATE_RET10 => -- #####################################################
691 
            theRegisters(12)(31 downto 16) <= datain;
692 
            theRegisters(13) <= theRegisters(13) + 2;
693 
            cpuState <= STATE_RET11;
694 
          when STATE_RET11 => -- #####################################################
695 
            theRegisters(14)(15 downto 0) <= datain;
696 
            theRegisters(13) <= theRegisters(13) + 2;
697 
            cpuState <= STATE_RET12;
698 
          when STATE_RET12 => -- #####################################################
699 
            theRegisters(14)(31 downto 16) <= datain;
700 
            theRegisters(13) <= theRegisters(13) + 2;
701 
            cpuState <= STATE_RET13;
702 
          when STATE_RET13 => -- #####################################################
703 
            theRegisters(15)(15 downto 0) <= datain;
704 
            theRegisters(13) <= theRegisters(13) + 2;
705 
            cpuState <= STATE_RET14;
706 
          when STATE_RET14 => -- #####################################################
707 
            theRegisters(15)(31 downto 16) <= datain;
708 
            theRegisters(13) <= theRegisters(13) + 2;
709 
            cpuState <= STATE_RET15;
710 
          when STATE_RET15 => -- #####################################################
711 
            cpsrRegister(15 downto 0) <= datain;
712 
            theRegisters(13) <= theRegisters(13) + 2;
713 
            cpuState <= STATE_RET16;
714 
          when STATE_RET16 => -- #####################################################
715 
            cpsrRegister(31 downto 16) <= datain;
716 
            theRegisters(13) <= theRegisters(13) + 2;
717 
            addrMux  <= ADDR_PC;
718 
            cpuState <= STATE_FETCH;
719 
          when STATE_FETCH => -- ###################################################
720 
            unitControl2 <= unitControl;
721 
            opcode       <= datain;
722 
            if irqrequest = '1' then -- irq ???
723 
              irqrequest <= '0';
724 
              cpuState <= STATE_IRQ;
725 
              theRegisters(13) <= theRegisters(13) - 2;
726 
             -- theRegisters(15) <= theRegisters(15) + 2;
727 
              addrMux  <= ADDR_SP;
728 
              dataout  <= cpsrRegister(31 downto 16);
729 
              writeL   <= '0';
730 
              writeH   <= '0';
731 
            else
732 
              case unitControl is
733 
                when CODE_LSL1 | CODE_LSR1 | CODE_ASR1 |
734 
                     CODE_LSL2 | CODE_LSR2 | CODE_ASR2 |
735 
                     CODE_ROR1 =>
736 
                  theRegisters(datain20) <= shiftResult;
737 
                  cpsrRegister(N_FLAG) <= shiftResult(31);
738 
                  if shiftResult = 0 then
739 
                    cpsrRegister(Z_FLAG) <= '1';
740 
                  else
741 
                    cpsrRegister(Z_FLAG) <= '0';
742 
                  end if;
743 
                  cpsrRegister(C_FLAG) <= cyShiftOut;
744 
                  theRegisters(15) <= theRegisters(15) + 2;
745 
                when CODE_CPY1 => -- Rd = Rm
746 
                  if (datain(7) & datain(2 downto 0) = "1111") then
747 
                    theRegisters(conv_integer(datain(7) & datain(2 downto 0))) <=
748 
                    theRegisters(conv_integer(datain(6 downto 3)));
749 
                  else
750 
                    theRegisters(conv_integer(datain(7) & datain(2 downto 0))) <=
751 
                    theRegisters(conv_integer(datain(6 downto 3)));
752 
                    theRegisters(15) <= theRegisters(15) + 2;
753 
                  end if;
754 
                when CODE_ADD4 => -- Rd = Rd + Rm
755 
                  if (datain(7) & datain(2 downto 0) = "1111") then
756 
                    theRegisters(conv_integer(datain(7) & datain(2 downto 0))) <=
757 
                                theRegisters(conv_integer(datain(7) & datain(2 downto 0))) +
758 
                                theRegisters(conv_integer(datain(6 downto 3)));
759 
                  else
760 
                    theRegisters(conv_integer(datain(7) & datain(2 downto 0))) <=
761 
                                theRegisters(conv_integer(datain(7) & datain(2 downto 0))) +
762 
                                theRegisters(conv_integer(datain(6 downto 3)));
763 
                    theRegisters(15) <= theRegisters(15) + 2;
764 
                  end if;
765 
                when CODE_ADD6 => -- Rn = SP + imm
766 
                  theRegisters(datain108) <=
767 
                                theRegisters(13) +
768 
                                (x"00000" & "00" & datain(7 downto 0) & "00");
769 
                  theRegisters(15) <= theRegisters(15) + 2;
770 
                when CODE_ADD7 => -- SP = SP + imm
771 
                  theRegisters(13) <= theRegisters(13) +
772 
                                    (x"00000" & "000" & datain(6 downto 0) & "00");
773 
                  theRegisters(15) <= theRegisters(15) + 2;
774 
                when CODE_SUB4 => -- SP = SP - imm
775 
                  theRegisters(13) <= theRegisters(13) -
776 
                                    (x"00000" & "000" & datain(6 downto 0) & "00");
777 
                  theRegisters(15) <= theRegisters(15) + 2;
778 
                when CODE_ADD1 =>
779 
                  tres := ("0" & theRegisters(datain53)) +
780 
                          ("0" & theRegisters(datain86));
781 
                  theRegisters(datain20) <=
782 
                          theRegisters(datain53) +
783 
                          theRegisters(datain86);
784 
                  cpsrRegister(C_FLAG) <= tres(32);
785 
                  cpsrRegister(N_FLAG) <= tres(31);
786 
                  if tres(31 downto 0) = 0 then
787 
                    cpsrRegister(Z_FLAG) <= '1';
788 
                  else
789 
                    cpsrRegister(Z_FLAG) <= '0';
790 
                  end if;
791 
                  op1 := theRegisters(datain53)(31);
792 
                  op2 := theRegisters(datain86)(31);
793 
                  opr := tres(31);
794 
                  cpsrRegister(V_FLAG) <= (op1 and op2 and not opr) or
795 
                                          (not op1 and not op2 and opr);
796 
                  theRegisters(15) <= theRegisters(15) + 2;
797 
                when CODE_SUB1 =>
798 
                  tres := ("0" & theRegisters(datain53)) -
799 
                          ("0" & theRegisters(datain86));
800 
                  theRegisters(datain20) <=
801 
                          theRegisters(datain53) -
802 
                          theRegisters(datain86);
803 
                  cpsrRegister(C_FLAG) <= not tres(32);
804 
                  cpsrRegister(N_FLAG) <= tres(31);
805 
                  if tres(31 downto 0) = 0 then
806 
                    cpsrRegister(Z_FLAG) <= '1';
807 
                  else
808 
                    cpsrRegister(Z_FLAG) <= '0';
809 
                  end if;
810 
                  op1 := theRegisters(datain53)(31);
811 
                  op2 := theRegisters(datain86)(31);
812 
                  opr := tres(31);
813 
                  cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
814 
                                          (not op1 and op2 and opr);
815 
                  theRegisters(15) <= theRegisters(15) + 2;
816 
                when CODE_ADD2 =>
817 
                  tres := ("0" & theRegisters(datain53)) +
818 
                          ("0" & x"0000000" & "0" & datain(8 downto 6));
819 
                  theRegisters(datain20) <=
820 
                          theRegisters(datain53) +
821 
                          (x"0000000" & "0" & datain(8 downto 6));
822 
                  cpsrRegister(C_FLAG) <= tres(32);
823 
                  cpsrRegister(N_FLAG) <= tres(31);
824 
                  if tres(31 downto 0) = 0 then
825 
                    cpsrRegister(Z_FLAG) <= '1';
826 
                  else
827 
                    cpsrRegister(Z_FLAG) <= '0';
828 
                  end if;
829 
                  op1 := theRegisters(datain53)(31);
830 
                  op2 := '0';
831 
                  opr := tres(31);
832 
                  cpsrRegister(V_FLAG) <= (op1 and op2 and not opr) or
833 
                                          (not op1 and not op2 and opr);
834 
                  theRegisters(15) <= theRegisters(15) + 2;
835 
                when CODE_SUB2 =>
836 
                  tres := ("0" & theRegisters(datain53)) -
837 
                          ("0" & x"0000000" & "0" & datain(8 downto 6));
838 
                  theRegisters(datain20) <=
839 
                          theRegisters(datain53) -
840 
                          (x"0000000" & "0" & datain(8 downto 6));
841 
                  cpsrRegister(C_FLAG) <= not tres(32);
842 
                  cpsrRegister(N_FLAG) <= tres(31);
843 
                  if tres(31 downto 0) = 0 then
844 
                    cpsrRegister(Z_FLAG) <= '1';
845 
                  else
846 
                    cpsrRegister(Z_FLAG) <= '0';
847 
                  end if;
848 
                  op1 := theRegisters(datain53)(31);
849 
                  op2 := '0';
850 
                  opr := tres(31);
851 
                  cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
852 
                                          (not op1 and op2 and opr);
853 
                  theRegisters(15) <= theRegisters(15) + 2;
854 
                when CODE_MOV1 =>
855 
                  tres := "0" & x"000000" & datain(7 downto 0);
856 
                  theRegisters(datain108) <= x"000000" & datain(7 downto 0);
857 
                  cpsrRegister(N_FLAG) <= tres(31);
858 
                  if tres(31 downto 0) = 0 then
859 
                    cpsrRegister(Z_FLAG) <= '1';
860 
                  else
861 
                    cpsrRegister(Z_FLAG) <= '0';
862 
                  end if;
863 
                  theRegisters(15) <= theRegisters(15) + 2;
864 
                when CODE_CMP1 =>
865 
                  tres := ("0" & theRegisters(datain108)) -
866 
                          ("0" & x"000000" & datain(7 downto 0));
867 
                  cpsrRegister(C_FLAG) <= not tres(32);
868 
                  cpsrRegister(N_FLAG) <= tres(31);
869 
                  if tres(31 downto 0) = 0 then
870 
                    cpsrRegister(Z_FLAG) <= '1';
871 
                  else
872 
                    cpsrRegister(Z_FLAG) <= '0';
873 
                  end if;
874 
                  op1 := theRegisters(datain108)(31);
875 
                  op2 := '0';
876 
                  opr := tres(31);
877 
                  cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
878 
                                          (not op1 and op2 and opr);
879 
                  theRegisters(15) <= theRegisters(15) + 2;
880 
                when CODE_ADD3 =>
881 
                  tres := ("0" & theRegisters(datain108)) +
882 
                          ("0" & x"000000" & datain(7 downto 0));
883 
                  theRegisters(datain108) <=
884 
                          theRegisters(datain108) +
885 
                          (x"000000" & datain(7 downto 0));
886 
                  cpsrRegister(C_FLAG) <= tres(32);
887 
                  cpsrRegister(N_FLAG) <= tres(31);
888 
                  if tres(31 downto 0) = 0 then
889 
                    cpsrRegister(Z_FLAG) <= '1';
890 
                  else
891 
                    cpsrRegister(Z_FLAG) <= '0';
892 
                  end if;
893 
                  op1 := theRegisters(datain108)(31);
894 
                  op2 := '0';
895 
                  opr := tres(31);
896 
                  cpsrRegister(V_FLAG) <= (op1 and op2 and not opr) or
897 
                                          (not op1 and not op2 and opr);
898 
                  theRegisters(15) <= theRegisters(15) + 2;
899 
                when CODE_SUB3 =>
900 
                  tres := ("0" & theRegisters(datain108)) -
901 
                          ("0" & x"000000" & datain(7 downto 0));
902 
                  theRegisters(datain108) <=
903 
                          theRegisters(datain108) -
904 
                          (x"000000" & datain(7 downto 0));
905 
                  cpsrRegister(C_FLAG) <= not tres(32);
906 
                  cpsrRegister(N_FLAG) <= tres(31);
907 
                  if tres(31 downto 0) = 0 then
908 
                    cpsrRegister(Z_FLAG) <= '1';
909 
                  else
910 
                    cpsrRegister(Z_FLAG) <= '0';
911 
                  end if;
912 
                  op1 := theRegisters(datain108)(31);
913 
                  op2 := '0';
914 
                  opr := tres(31);
915 
                  cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
916 
                                          (not op1 and op2 and opr);
917 
                  theRegisters(15) <= theRegisters(15) + 2;
918 
                when CODE_AND1 =>
919 
                  tres := ("0" & theRegisters(datain20)) and
920 
                          ("0" & theRegisters(datain53));
921 
                  theRegisters(datain20) <=
922 
                          theRegisters(datain20) and
923 
                          theRegisters(datain53);
924 
                  cpsrRegister(N_FLAG) <= tres(31);
925 
                  if tres(31 downto 0) = 0 then
926 
                    cpsrRegister(Z_FLAG) <= '1';
927 
                  else
928 
                    cpsrRegister(Z_FLAG) <= '0';
929 
                  end if;
930 
                  theRegisters(15) <= theRegisters(15) + 2;
931 
                when CODE_EOR1 =>
932 
                  tres := ("0" & theRegisters(datain20)) xor
933 
                          ("0" & theRegisters(datain53));
934 
                  theRegisters(datain20) <=
935 
                          theRegisters(datain20) xor
936 
                          theRegisters(datain53);
937 
                  cpsrRegister(N_FLAG) <= tres(31);
938 
                  if tres(31 downto 0) = 0 then
939 
                    cpsrRegister(Z_FLAG) <= '1';
940 
                  else
941 
                    cpsrRegister(Z_FLAG) <= '0';
942 
                  end if;
943 
                  theRegisters(15) <= theRegisters(15) + 2;
944 
                when CODE_ADC1 =>
945 
                  tres := ("0" & theRegisters(datain20)) +
946 
                          ("0" & theRegisters(datain53)) +
947 
                          (x"00000000" & cpsrRegister(C_FLAG));
948 
                  theRegisters(datain20) <=
949 
                          theRegisters(datain20) +
950 
                          theRegisters(datain53) +
951 
                          ("000" & x"0000000" & cpsrRegister(C_FLAG));
952 
                  cpsrRegister(C_FLAG) <= tres(32);
953 
                  cpsrRegister(N_FLAG) <= tres(31);
954 
                  if tres(31 downto 0) = 0 then
955 
                    cpsrRegister(Z_FLAG) <= '1';
956 
                  else
957 
                    cpsrRegister(Z_FLAG) <= '0';
958 
                  end if;
959 
                  op1 := theRegisters(datain20)(31);
960 
                  op2 := theRegisters(datain53)(31);
961 
                  opr := tres(31);
962 
                  cpsrRegister(V_FLAG) <= (op1 and op2 and not opr) or
963 
                                          (not op1 and not op2 and opr);
964 
                  theRegisters(15) <= theRegisters(15) + 2;
965 
                when CODE_SBC1 =>
966 
                  tres := ("0" & theRegisters(datain20)) -
967 
                          ("0" & theRegisters(datain53)) -
968 
                          ("000" & x"0000000" & (not cpsrRegister(C_FLAG)));
969 
                  theRegisters(datain20) <=
970 
                          theRegisters(datain20) -
971 
                          theRegisters(datain53) -
972 
                          ("000" & x"0000000" & (not cpsrRegister(C_FLAG)));
973 
                  cpsrRegister(C_FLAG) <= not tres(32);
974 
                  cpsrRegister(N_FLAG) <= tres(31);
975 
                  if tres(31 downto 0) = 0 then
976 
                    cpsrRegister(Z_FLAG) <= '1';
977 
                  else
978 
                    cpsrRegister(Z_FLAG) <= '0';
979 
                  end if;
980 
                  op1 := theRegisters(datain20)(31);
981 
                  op2 := theRegisters(datain53)(31);
982 
                  opr := tres(31);
983 
                  cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
984 
                                          (not op1 and op2 and opr);
985 
                  theRegisters(15) <= theRegisters(15) + 2;
986 
                when CODE_TST1 =>
987 
                  tres := ("0" & theRegisters(datain20)) and
988 
                          ("0" & theRegisters(datain53));
989 
                  cpsrRegister(N_FLAG) <= tres(31);
990 
                  if tres(31 downto 0) = 0 then
991 
                    cpsrRegister(Z_FLAG) <= '1';
992 
                  else
993 
                    cpsrRegister(Z_FLAG) <= '0';
994 
                  end if;
995 
                  theRegisters(15) <= theRegisters(15) + 2;
996 
                when CODE_NEG1 =>
997 
                  tres := ("0" & x"00000000") -
998 
                          ("0" & theRegisters(datain53));
999 
                  theRegisters(datain20) <=
1000 
                          x"00000000" -
1001 
                          theRegisters(datain53);
1002 
                  cpsrRegister(C_FLAG) <= not tres(32);
1003 
                  cpsrRegister(N_FLAG) <= tres(31);
1004 
                  if tres(31 downto 0) = 0 then
1005 
                    cpsrRegister(Z_FLAG) <= '1';
1006 
                  else
1007 
                    cpsrRegister(Z_FLAG) <= '0';
1008 
                  end if;
1009 
                  op1 := theRegisters(datain20)(31);
1010 
                  op2 := theRegisters(datain53)(31);
1011 
                  opr := tres(31);
1012 
                  cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
1013 
                                          (not op1 and op2 and opr);
1014 
                  theRegisters(15) <= theRegisters(15) + 2;
1015 
                when CODE_CMP2 =>
1016 
                  tres := ("0" & theRegisters(datain20)) -
1017 
                          ("0" & theRegisters(datain53));
1018 
                  cpsrRegister(C_FLAG) <= not tres(32);
1019 
                  cpsrRegister(N_FLAG) <= tres(31);
1020 
                  if tres(31 downto 0) = 0 then
1021 
                    cpsrRegister(Z_FLAG) <= '1';
1022 
                  else
1023 
                    cpsrRegister(Z_FLAG) <= '0';
1024 
                  end if;
1025 
                  op1 := theRegisters(datain20)(31);
1026 
                  op2 := theRegisters(datain53)(31);
1027 
                  opr := tres(31);
1028 
                  cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
1029 
                                          (not op1 and op2 and opr);
1030 
                  theRegisters(15) <= theRegisters(15) + 2;
1031 
                when CODE_CMN1 =>
1032 
                  tres := ("0" & theRegisters(datain20)) +
1033 
                          ("0" & theRegisters(datain53));
1034 
                  cpsrRegister(C_FLAG) <= tres(32);
1035 
                  cpsrRegister(N_FLAG) <= tres(31);
1036 
                  if tres(31 downto 0) = 0 then
1037 
                    cpsrRegister(Z_FLAG) <= '1';
1038 
                  else
1039 
                    cpsrRegister(Z_FLAG) <= '0';
1040 
                  end if;
1041 
                  op1 := theRegisters(datain20)(31);
1042 
                  op2 := theRegisters(datain53)(31);
1043 
                  opr := tres(31);
1044 
                  cpsrRegister(V_FLAG) <= (op1 and op2 and not opr) or
1045 
                                          (not op1 and not op2 and opr);
1046 
                  theRegisters(15) <= theRegisters(15) + 2;
1047 
                when CODE_ORR1 =>
1048 
                  tres := ("0" & theRegisters(datain20)) or
1049 
                          ("0" & theRegisters(datain53));
1050 
                  theRegisters(datain20) <=
1051 
                          theRegisters(datain20) or
1052 
                          theRegisters(datain53);
1053 
                  cpsrRegister(N_FLAG) <= tres(31);
1054 
                  if tres(31 downto 0) = 0 then
1055 
                    cpsrRegister(Z_FLAG) <= '1';
1056 
                  else
1057 
                    cpsrRegister(Z_FLAG) <= '0';
1058 
                  end if;
1059 
                  theRegisters(15) <= theRegisters(15) + 2;
1060 
                when CODE_MUL1 =>
1061 
                  theRegisters(datain20) <= product(31 downto 0);
1062 
                  cpsrRegister(N_FLAG) <= product(31);
1063 
                  if product(31 downto 0) = 0 then
1064 
                    cpsrRegister(Z_FLAG) <= '1';
1065 
                  else
1066 
                    cpsrRegister(Z_FLAG) <= '0';
1067 
                  end if;
1068 
                  theRegisters(15) <= theRegisters(15) + 2;
1069 
                when CODE_BIC1 =>
1070 
                  tres := ("0" & theRegisters(datain20)) and
1071 
                          not ("0" & theRegisters(datain53));
1072 
                  theRegisters(datain20) <=
1073 
                          theRegisters(datain20) and
1074 
                          not theRegisters(datain53);
1075 
                  cpsrRegister(N_FLAG) <= tres(31);
1076 
                  if tres(31 downto 0) = 0 then
1077 
                    cpsrRegister(Z_FLAG) <= '1';
1078 
                  else
1079 
                    cpsrRegister(Z_FLAG) <= '0';
1080 
                  end if;
1081 
                  theRegisters(15) <= theRegisters(15) + 2;
1082 
                when CODE_MVN1 =>
1083 
                  tres := not ("0" & theRegisters(datain53));
1084 
                  theRegisters(datain20) <=
1085 
                          not theRegisters(datain53);
1086 
                  cpsrRegister(N_FLAG) <= tres(31);
1087 
                  if tres(31 downto 0) = 0 then
1088 
                    cpsrRegister(Z_FLAG) <= '1';
1089 
                  else
1090 
                    cpsrRegister(Z_FLAG) <= '0';
1091 
                  end if;
1092 
                  theRegisters(15) <= theRegisters(15) + 2;
1093 
                when CODE_CMP3 =>
1094 
                  tres := ("0" & theRegisters(conv_integer(datain(7) & datain(2 downto 0)))) -
1095 
                          ("0" & theRegisters(conv_integer(datain(6) & datain(5 downto 3))));
1096 
                  cpsrRegister(C_FLAG) <= not tres(32);
1097 
                  cpsrRegister(N_FLAG) <= tres(31);
1098 
                  if tres(31 downto 0) = 0 then
1099 
                    cpsrRegister(Z_FLAG) <= '1';
1100 
                  else
1101 
                    cpsrRegister(Z_FLAG) <= '0';
1102 
                  end if;
1103 
                  op1 := theRegisters(conv_integer(datain(7) & datain(2 downto 0)))(31);
1104 
                  op2 := theRegisters(conv_integer(datain(6) & datain(5 downto 3)))(31);
1105 
                  opr := tres(31);
1106 
                  cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
1107 
                                          (not op1 and op2 and opr);
1108 
                  theRegisters(15) <= theRegisters(15) + 2;
1109 
                when CODE_BX1 =>
1110 
                  if theRegisters(14) = x"FFFFFFF9" then  -- EXC_RETURN ?
1111 
                    if datain(6 downto 3) = "1110" then
1112 
                      cpuState <= STATE_RET;
1113 
                    else
1114 
                      theRegisters(15) <= theRegisters(conv_integer(datain(6 downto 3)))(31 downto 1) & "0";
1115 
                      theRegisters(14) <= theRegisters(15) + 2;
1116 
                    end if;
1117 
                  else
1118 
                    theRegisters(15) <= theRegisters(conv_integer(datain(6 downto 3)))(31 downto 1) & "0";
1119 
                    if datain(6 downto 3) /= "1110" then
1120 
                      theRegisters(14) <= theRegisters(15) + 2;
1121 
                    end if;
1122 
                  end if;
1123 
                when CODE_LDR1 =>
1124 
                  address  <= (theRegisters(15) and x"FFFFFFFC") +
1125 
                              (x"00000" & "00" & datain(7 downto 0) & "00") + x"00000004";
1126 
                  addrMux  <= ADDR_RS;
1127 
                  theRegisters(15) <= theRegisters(15) + 2;
1128 
                  cpuState <= STATE_READ1;
1129 
                when CODE_LDR4 =>
1130 
                  address  <= theRegisters(13) +
1131 
                              (x"00000" & "00" & datain(7 downto 0) & "00");
1132 
                  addrMux  <= ADDR_RS;
1133 
                  theRegisters(15) <= theRegisters(15) + 2;
1134 
                  cpuState <= STATE_READ1;
1135 
                when CODE_STR1 | CODE_STRH1 =>
1136 
                  address  <= theRegisters(datain53) +
1137 
                              theRegisters(datain86);
1138 
                  addrMux  <= ADDR_RS;
1139 
                  writeL   <= '0';
1140 
                  writeH   <= '0';
1141 
                  dataout  <= theRegisters(datain20)(15 downto 0);
1142 
                  theRegisters(15) <= theRegisters(15) + 2;
1143 
                  cpuState <= STATE_WRITE1;
1144 
                when CODE_STRB1 =>
1145 
                  address  <= theRegisters(datain53) +
1146 
                              theRegisters(datain86);
1147 
                  tsum     := theRegisters(datain53) +
1148 
                              theRegisters(datain86);
1149 
                  addrMux  <= ADDR_RS;
1150 
                  if tsum(0) = '0' then
1151 
                    writeL   <= '0';
1152 
                    writeH   <= '1';
1153 
                  else
1154 
                    writeL   <= '1';
1155 
                    writeH   <= '0';
1156 
                  end if;
1157 
                  dataout  <= theRegisters(datain20)(7 downto 0) &
1158 
                              theRegisters(datain20)(7 downto 0);
1159 
                  theRegisters(15) <= theRegisters(15) + 2;
1160 
                  cpuState <= STATE_WRITE1;
1161 
                when CODE_LDRSB1 | CODE_LDR2 | CODE_LDRH1 | CODE_LDRB1 | CODE_LDRSH1 =>
1162 
                  address  <= theRegisters(datain53) +
1163 
                              theRegisters(datain86);
1164 
                  addrMux  <= ADDR_RS;
1165 
                  theRegisters(15) <= theRegisters(15) + 2;
1166 
                  cpuState <= STATE_READ1;
1167 
                when CODE_STR2 =>
1168 
                  address  <= theRegisters(datain53) +
1169 
                              (x"000000" & "0" & datain(10 downto 6) & "00");
1170 
                  addrMux  <= ADDR_RS;
1171 
                  writeL   <= '0';
1172 
                  writeH   <= '0';
1173 
                  dataout  <= theRegisters(datain20)(15 downto 0);
1174 
                  theRegisters(15) <= theRegisters(15) + 2;
1175 
                  cpuState <= STATE_WRITE1;
1176 
                when CODE_LDR3 =>
1177 
                  address  <= theRegisters(datain53) +
1178 
                              (x"000000" & "0" & datain(10 downto 6) & "00");
1179 
                  addrMux  <= ADDR_RS;
1180 
                  theRegisters(15) <= theRegisters(15) + 2;
1181 
                  cpuState <= STATE_READ1;
1182 
                when CODE_STRB2 =>
1183 
                  address  <= theRegisters(datain53) +
1184 
                              (x"000000" & "000" & datain(10 downto 6));
1185 
                  tsum     := theRegisters(datain53) +
1186 
                              (x"000000" & "000" & datain(10 downto 6));
1187 
                  addrMux  <= ADDR_RS;
1188 
                  if tsum(0) = '0' then
1189 
                    writeL   <= '0';
1190 
                    writeH   <= '1';
1191 
                  else
1192 
                    writeL   <= '1';
1193 
                    writeH   <= '0';
1194 
                  end if;
1195 
                  dataout  <= theRegisters(datain20)(7 downto 0) &
1196 
                              theRegisters(datain20)(7 downto 0);
1197 
                  theRegisters(15) <= theRegisters(15) + 2;
1198 
                  cpuState <= STATE_WRITE1;
1199 
                when CODE_LDRB2 =>
1200 
                  address  <= theRegisters(datain53) +
1201 
                              (x"000000" & "000" & datain(10 downto 6));
1202 
                  addrMux  <= ADDR_RS;
1203 
                  theRegisters(15) <= theRegisters(15) + 2;
1204 
                  cpuState <= STATE_READ1;
1205 
                when CODE_LDRH2 =>
1206 
                  address  <= theRegisters(datain53) +
1207 
                              (x"000000" & "00" & datain(10 downto 6) & "0");
1208 
                  addrMux  <= ADDR_RS;
1209 
                  theRegisters(15) <= theRegisters(15) + 2;
1210 
                  cpuState <= STATE_READ1;
1211 
                when CODE_STRH2 =>
1212 
                  address  <= theRegisters(datain53) +
1213 
                              (x"000000" & "00" & datain(10 downto 6) & "0");
1214 
                  addrMux  <= ADDR_RS;
1215 
                  writeL   <= '0';
1216 
                  writeH   <= '0';
1217 
                  dataout  <= theRegisters(datain20)(15 downto 0);
1218 
                  theRegisters(15) <= theRegisters(15) + 2;
1219 
                  cpuState <= STATE_WRITE1;
1220 
                when CODE_STR3 =>
1221 
                  address  <= theRegisters(13) +
1222 
                              (x"00000" & "00" & datain(7 downto 0) & "00");
1223 
                  addrMux  <= ADDR_RS;
1224 
                  writeL   <= '0';
1225 
                  writeH   <= '0';
1226 
                  dataout  <= theRegisters(datain108)(15 downto 0);
1227 
                  theRegisters(15) <= theRegisters(15) + 2;
1228 
                  cpuState <= STATE_WRITE1;
1229 
                when CODE_ADD5 =>
1230 
                  theRegisters(datain108) <=
1231 
                      theRegisters(15) + (x"00000" & "00" & datain(7 downto 0) & "00");
1232 
                  theRegisters(15) <= theRegisters(15) + 2;
1233 
                  cpuState <= STATE_FETCH;
1234 
                when CODE_SXTH1 =>
1235 
                  theRegisters(datain20) <=
1236 
                      theRegisters(datain53)(15) &
1237 
                      theRegisters(datain53)(15) &
1238 
                      theRegisters(datain53)(15) &
1239 
                      theRegisters(datain53)(15) &
1240 
                      theRegisters(datain53)(15) &
1241 
                      theRegisters(datain53)(15) &
1242 
                      theRegisters(datain53)(15) &
1243 
                      theRegisters(datain53)(15) &
1244 
                      theRegisters(datain53)(15) &
1245 
                      theRegisters(datain53)(15) &
1246 
                      theRegisters(datain53)(15) &
1247 
                      theRegisters(datain53)(15) &
1248 
                      theRegisters(datain53)(15) &
1249 
                      theRegisters(datain53)(15) &
1250 
                      theRegisters(datain53)(15) &
1251 
                      theRegisters(datain53)(15) &
1252 
                      theRegisters(datain53)(15 downto 0);
1253 
                  theRegisters(15) <= theRegisters(15) + 2;
1254 
                  cpuState <= STATE_FETCH;
1255 
                when CODE_SXTB1 =>
1256 
                  theRegisters(datain20) <=
1257 
                      theRegisters(datain53)(7) &
1258 
                      theRegisters(datain53)(7) &
1259 
                      theRegisters(datain53)(7) &
1260 
                      theRegisters(datain53)(7) &
1261 
                      theRegisters(datain53)(7) &
1262 
                      theRegisters(datain53)(7) &
1263 
                      theRegisters(datain53)(7) &
1264 
                      theRegisters(datain53)(7) &
1265 
                      theRegisters(datain53)(7) &
1266 
                      theRegisters(datain53)(7) &
1267 
                      theRegisters(datain53)(7) &
1268 
                      theRegisters(datain53)(7) &
1269 
                      theRegisters(datain53)(7) &
1270 
                      theRegisters(datain53)(7) &
1271 
                      theRegisters(datain53)(7) &
1272 
                      theRegisters(datain53)(7) &
1273 
                      theRegisters(datain53)(7) &
1274 
                      theRegisters(datain53)(7) &
1275 
                      theRegisters(datain53)(7) &
1276 
                      theRegisters(datain53)(7) &
1277 
                      theRegisters(datain53)(7) &
1278 
                      theRegisters(datain53)(7) &
1279 
                      theRegisters(datain53)(7) &
1280 
                      theRegisters(datain53)(7) &
1281 
                      theRegisters(datain53)(7 downto 0);
1282 
                  theRegisters(15) <= theRegisters(15) + 2;
1283 
                  cpuState <= STATE_FETCH;
1284 
                when CODE_UXTH1 =>
1285 
                  theRegisters(datain20) <= x"0000" &
1286 
                      theRegisters(datain53)(15 downto 0);
1287 
                  theRegisters(15) <= theRegisters(15) + 2;
1288 
                  cpuState <= STATE_FETCH;
1289 
                when CODE_UXTB1 =>
1290 
                  theRegisters(datain20) <= x"000000" &
1291 
                      theRegisters(datain53)(7 downto 0);
1292 
                  theRegisters(15) <= theRegisters(15) + 2;
1293 
                  cpuState <= STATE_FETCH;
1294 
                when CODE_PUSH1 =>
1295 
                  theRegisters(15) <= theRegisters(15) + 2;
1296 
                  if datain(8 downto 0) = 0 then
1297 
                    cpuState <= STATE_FETCH;
1298 
                  else
1299 
                    theRegisters(13) <= theRegisters(13) - 2;
1300 
                    addrMux  <= ADDR_SP;
1301 
                    writeL   <= '0';
1302 
                    writeH   <= '0';
1303 
                    if datain(8) = '1' then
1304 
                      dataout <= theRegisters(14)(31 downto 16);
1305 
                      cpuState <= STATE_WRPH;
1306 
                    elsif datain(7) = '1' then
1307 
                      dataout <= theRegisters(7)(31 downto 16);
1308 
                      cpuState <= STATE_WR7H;
1309 
                    elsif datain(6) = '1' then
1310 
                      dataout <= theRegisters(6)(31 downto 16);
1311 
                      cpuState <= STATE_WR6H;
1312 
                    elsif datain(5) = '1' then
1313 
                      dataout <= theRegisters(5)(31 downto 16);
1314 
                      cpuState <= STATE_WR5H;
1315 
                    elsif datain(4) = '1' then
1316 
                      dataout <= theRegisters(4)(31 downto 16);
1317 
                      cpuState <= STATE_WR4H;
1318 
                    elsif datain(3) = '1' then
1319 
                      dataout <= theRegisters(3)(31 downto 16);
1320 
                      cpuState <= STATE_WR3H;
1321 
                    elsif datain(2) = '1' then
1322 
                      dataout <= theRegisters(2)(31 downto 16);
1323 
                      cpuState <= STATE_WR2H;
1324 
                    elsif datain(1) = '1' then
1325 
                      dataout <= theRegisters(1)(31 downto 16);
1326 
                      cpuState <= STATE_WR1H;
1327 
                    else
1328 
                      dataout <= theRegisters(0)(31 downto 16);
1329 
                      cpuState <= STATE_WR0H;
1330 
                    end if;
1331 
                  end if;
1332 
                when CODE_POP1 =>
1333 
                  theRegisters(15) <= theRegisters(15) + 2;
1334 
                  if datain(8 downto 0) = 0 then
1335 
                    cpuState <= STATE_FETCH;
1336 
                  else
1337 
                    addrMux  <= ADDR_SP;
1338 
                    if datain(0) = '1' then
1339 
                      cpuState <= STATE_RD0L;
1340 
                    elsif datain(1) = '1' then
1341 
                      cpuState <= STATE_RD1L;
1342 
                    elsif datain(2) = '1' then
1343 
                      cpuState <= STATE_RD2L;
1344 
                    elsif datain(3) = '1' then
1345 
                      cpuState <= STATE_RD3L;
1346 
                    elsif datain(4) = '1' then
1347 
                      cpuState <= STATE_RD4L;
1348 
                    elsif datain(5) = '1' then
1349 
                      cpuState <= STATE_RD5L;
1350 
                    elsif datain(6) = '1' then
1351 
                      cpuState <= STATE_RD6L;
1352 
                    elsif datain(7) = '1' then
1353 
                      cpuState <= STATE_RD7L;
1354 
                    else
1355 
                      cpuState <= STATE_RDPL;
1356 
                    end if;
1357 
                  end if;
1358 
                when CODE_NOP =>
1359 
                  theRegisters(15) <= theRegisters(15) + 2;
1360 
                when CODE_STMIA1 =>
1361 
                  theRegisters(15) <= theRegisters(15) + 2;
1362 
                  if datain(7 downto 0) = 0 then
1363 
                    cpuState <= STATE_FETCH;
1364 
                  else
1365 
                    address  <= theRegisters(datain108);
1366 
                    addrMux  <= ADDR_RS;
1367 
                    writeL   <= '0';
1368 
                    writeH   <= '0';
1369 
                    if datain(0) = '1' then
1370 
                      dataout <= theRegisters(0)(15 downto 0);
1371 
                      cpuState <= STATE_WR0H;
1372 
                    elsif datain(1) = '1' then
1373 
                      dataout <= theRegisters(1)(15 downto 0);
1374 
                      cpuState <= STATE_WR1H;
1375 
                    elsif datain(2) = '1' then
1376 
                      dataout <= theRegisters(2)(15 downto 0);
1377 
                      cpuState <= STATE_WR2H;
1378 
                    elsif datain(3) = '1' then
1379 
                      dataout <= theRegisters(3)(15 downto 0);
1380 
                      cpuState <= STATE_WR3H;
1381 
                    elsif datain(4) = '1' then
1382 
                      dataout <= theRegisters(4)(15 downto 0);
1383 
                      cpuState <= STATE_WR4H;
1384 
                    elsif datain(5) = '1' then
1385 
                      dataout <= theRegisters(5)(15 downto 0);
1386 
                      cpuState <= STATE_WR5H;
1387 
                    elsif datain(6) = '1' then
1388 
                      dataout <= theRegisters(6)(15 downto 0);
1389 
                      cpuState <= STATE_WR6H;
1390 
                    else
1391 
                      dataout <= theRegisters(7)(15 downto 0);
1392 
                      cpuState <= STATE_WR7H;
1393 
                    end if;
1394 
                  end if;
1395 
                when CODE_LDMIA1 =>
1396 
                  LDMread <= x"00";
1397 
                  theRegisters(15) <= theRegisters(15) + 2;
1398 
                  if datain(7 downto 0) = 0 then
1399 
                    cpuState <= STATE_FETCH;
1400 
                  else
1401 
                    address  <= theRegisters(datain108);
1402 
                    addrMux  <= ADDR_RS;
1403 
                    if datain(0) = '1' then
1404 
                      cpuState <= STATE_RD0L;
1405 
                    elsif datain(1) = '1' then
1406 
                      cpuState <= STATE_RD1L;
1407 
                    elsif datain(2) = '1' then
1408 
                      cpuState <= STATE_RD2L;
1409 
                    elsif datain(3) = '1' then
1410 
                      cpuState <= STATE_RD3L;
1411 
                    elsif datain(4) = '1' then
1412 
                      cpuState <= STATE_RD4L;
1413 
                    elsif datain(5) = '1' then
1414 
                      cpuState <= STATE_RD5L;
1415 
                    elsif datain(6) = '1' then
1416 
                      cpuState <= STATE_RD6L;
1417 
                    else
1418 
                      cpuState <= STATE_RD7L;
1419 
                    end if;
1420 
                  end if;
1421 
                when CODE_BCC1 =>
1422 
                  if branch = '1' then
1423 
                    theRegisters(15) <= theRegisters(15) + (
1424 
                      datain(7) & datain(7) & datain(7) & datain(7) &
1425 
                      datain(7) & datain(7) & datain(7) & datain(7) &
1426 
                      datain(7) & datain(7) & datain(7) & datain(7) &
1427 
                      datain(7) & datain(7) & datain(7) & datain(7) &
1428 
                      datain(7) & datain(7) & datain(7) & datain(7) &
1429 
                      datain(7) & datain(7) & datain(7) &
1430 
                      datain(7 downto 0) & "0") + x"00000004";
1431 
                  else
1432 
                    theRegisters(15) <= theRegisters(15) + 2;
1433 
                  end if;
1434 
                when CODE_B1 =>
1435 
                  theRegisters(15) <= theRegisters(15) + (
1436 
                    datain(10) & datain(10) & datain(10) & datain(10) &
1437 
                    datain(10) & datain(10) & datain(10) & datain(10) &
1438 
                    datain(10) & datain(10) & datain(10) & datain(10) &
1439 
                    datain(10) & datain(10) & datain(10) & datain(10) &
1440 
                    datain(10) & datain(10) & datain(10) & datain(10) &
1441 
                    datain(10 downto 0) & "0") + x"00000004";
1442 
                when CODE_BLX2 =>
1443 
                  theRegisters(14) <= theRegisters(15) + (
1444 
                    datain(10) & datain(10) & datain(10) & datain(10) &
1445 
                    datain(10) & datain(10) & datain(10) & datain(10) &
1446 
                    datain(10) &
1447 
                    datain(10 downto 0) & x"000") + x"00000004";
1448 
                  theRegisters(15) <= theRegisters(15) + 2;
1449 
                when CODE_BL1 =>
1450 
                  theRegisters(15) <= theRegisters(14) + (x"00000" &
1451 
                    datain(10 downto 0) & "0");
1452 
                  theRegisters(14) <= theRegisters(15) + 2;
1453 
 
1454 
                when others =>
1455 
                  cpuState <= STATE_FETCH;
1456 
              end case; -- unitControl
1457 
            end if; -- irqrequest
1458 
          when STATE_READ1 => -- ##################################################
1459 
            case unitControl2 is
1460 
              when CODE_LDRH1 | CODE_LDRH2 =>
1461 
                theRegisters(opcode20)(15 downto 0) <= datain;
1462 
                addrMux  <= ADDR_PC;
1463 
                cpuState <= STATE_FETCH;
1464 
              when CODE_LDRSH1 =>
1465 
                theRegisters(opcode20)(15 downto 0) <= datain;
1466 
                theRegisters(opcode20)(31 downto 16) <=
1467 
                    datain(15) & datain(15) & datain(15) & datain(15) & datain(15) & datain(15) &
1468 
                    datain(15) & datain(15) & datain(15) & datain(15) & datain(15) & datain(15) &
1469 
                    datain(15) & datain(15) & datain(15) & datain(15);
1470 
                addrMux  <= ADDR_PC;
1471 
                cpuState <= STATE_FETCH;
1472 
              when CODE_LDR1 | CODE_LDR4 =>
1473 
                theRegisters(opcode108)(15 downto 0) <= datain;
1474 
                address <= address + 2;
1475 
                cpuState <= STATE_READ2;
1476 
              when CODE_LDR2 | CODE_LDR3 =>
1477 
                theRegisters(opcode20)(15 downto 0) <= datain;
1478 
                address <= address + 2;
1479 
                cpuState <= STATE_READ2;
1480 
              when CODE_LDRSB1 =>
1481 
                if address(0) = '0' then
1482 
                  theRegisters(opcode20)(7 downto 0) <= datain(7 downto 0);
1483 
                  theRegisters(opcode20)(31 downto 8) <=
1484 
                    datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) &
1485 
                    datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) &
1486 
                    datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) &
1487 
                    datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7);
1488 
                else
1489 
                  theRegisters(opcode20)(7 downto 0) <= datain(15 downto 8);
1490 
                  theRegisters(opcode20)(31 downto 8) <=
1491 
                    datain(15) & datain(15) & datain(15) & datain(15) & datain(15) & datain(15) &
1492 
                    datain(15) & datain(15) & datain(15) & datain(15) & datain(15) & datain(15) &
1493 
                    datain(15) & datain(15) & datain(15) & datain(15) & datain(15) & datain(15) &
1494 
                    datain(15) & datain(15) & datain(15) & datain(15) & datain(15) & datain(15);
1495 
                end if;
1496 
                addrMux  <= ADDR_PC;
1497 
                cpuState <= STATE_FETCH;
1498 
              when CODE_LDRB1 | CODE_LDRB2 =>
1499 
                if address(0) = '0' then
1500 
                  theRegisters(opcode20)(7 downto 0) <= datain(7 downto 0);
1501 
                else
1502 
                  theRegisters(opcode20)(7 downto 0) <= datain(15 downto 8);
1503 
                end if;
1504 
                theRegisters(opcode20)(31 downto 8) <= x"000000";
1505 
                addrMux  <= ADDR_PC;
1506 
                cpuState <= STATE_FETCH;
1507 
 
1508 
              when others =>
1509 
                cpuState <= STATE_FETCH;
1510 
            end case; -- unitControl2
1511 
 
1512 
          when STATE_READ2 => -- ##################################################
1513 
            case unitControl2 is
1514 
              when CODE_LDR1 | CODE_LDR4 =>
1515 
                theRegisters(opcode108)(31 downto 16) <= datain;
1516 
                addrMux  <= ADDR_PC;
1517 
                cpuState <= STATE_FETCH;
1518 
              when CODE_LDR2 | CODE_LDR3 =>
1519 
                theRegisters(opcode20)(31 downto 16) <= datain;
1520 
                addrMux  <= ADDR_PC;
1521 
                cpuState <= STATE_FETCH;
1522 
 
1523 
              when others =>
1524 
                cpuState <= STATE_FETCH;
1525 
            end case; -- unitControl2
1526 
 
1527 
          when STATE_RD0L => -- ##################################################
1528 
            case unitControl2 is
1529 
              when CODE_POP1 =>
1530 
                theRegisters(13) <= theRegisters(13) + 2;
1531 
                theRegisters(0)(15 downto 0) <= datain;
1532 
                cpuState <= STATE_RD0H;
1533 
              when CODE_LDMIA1 =>
1534 
                LDMread(0) <= '1';
1535 
                theRegisters(0)(15 downto 0) <= datain;
1536 
                address <= address + 2;
1537 
                cpuState <= STATE_RD0H;
1538 
 
1539 
              when others =>
1540 
                cpuState <= STATE_FETCH;
1541 
            end case; -- unitControl2
1542 
 
1543 
          when STATE_RD0H => -- ##################################################
1544 
            case unitControl2 is
1545 
              when CODE_POP1 =>
1546 
                theRegisters(13) <= theRegisters(13) + 2;
1547 
                theRegisters(0)(31 downto 16) <= datain;
1548 
                if opcode(8 downto 1) = 0 then
1549 
                  addrMux  <= ADDR_PC;
1550 
                  cpuState <= STATE_FETCH;
1551 
                else
1552 
                  if opcode(1) = '1' then
1553 
                    cpuState <= STATE_RD1L;
1554 
                  elsif opcode(2) = '1' then
1555 
                    cpuState <= STATE_RD2L;
1556 
                  elsif opcode(3) = '1' then
1557 
                    cpuState <= STATE_RD3L;
1558 
                  elsif opcode(4) = '1' then
1559 
                    cpuState <= STATE_RD4L;
1560 
                  elsif opcode(5) = '1' then
1561 
                    cpuState <= STATE_RD5L;
1562 
                  elsif opcode(6) = '1' then
1563 
                    cpuState <= STATE_RD6L;
1564 
                  elsif opcode(7) = '1' then
1565 
                    cpuState <= STATE_RD7L;
1566 
                  else
1567 
                    cpuState <= STATE_RDPL;
1568 
                  end if;
1569 
                end if;
1570 
              when CODE_LDMIA1 =>
1571 
                address <= address + 2;
1572 
                if opcode(7 downto 1) = 0 then
1573 
                  addrMux  <= ADDR_PC;
1574 
                  if opcode108 = 0 then
1575 
                    theRegisters(0)(31 downto 16) <= datain;
1576 
                  else
1577 
                    theRegisters(opcode108) <= address + 2;
1578 
                  end if;
1579 
                  cpuState <= STATE_FETCH;
1580 
                else
1581 
                  theRegisters(0)(31 downto 16) <= datain;
1582 
                  if opcode(1) = '1' then
1583 
                    cpuState <= STATE_RD1L;
1584 
                  elsif opcode(2) = '1' then
1585 
                    cpuState <= STATE_RD2L;
1586 
                  elsif opcode(3) = '1' then
1587 
                    cpuState <= STATE_RD3L;
1588 
                  elsif opcode(4) = '1' then
1589 
                    cpuState <= STATE_RD4L;
1590 
                  elsif opcode(5) = '1' then
1591 
                    cpuState <= STATE_RD5L;
1592 
                  elsif opcode(6) = '1' then
1593 
                    cpuState <= STATE_RD6L;
1594 
                  else
1595 
                    cpuState <= STATE_RD7L;
1596 
                  end if;
1597 
                end if;
1598 
 
1599 
              when others =>
1600 
                cpuState <= STATE_FETCH;
1601 
            end case; -- unitControl2
1602 
 
1603 
          when STATE_RD1L => -- ##################################################
1604 
            case unitControl2 is
1605 
              when CODE_POP1 =>
1606 
                theRegisters(13) <= theRegisters(13) + 2;
1607 
                theRegisters(1)(15 downto 0) <= datain;
1608 
                cpuState <= STATE_RD1H;
1609 
              when CODE_LDMIA1 =>
1610 
                LDMread(1) <= '1';
1611 
                theRegisters(1)(15 downto 0) <= datain;
1612 
                address <= address + 2;
1613 
                cpuState <= STATE_RD1H;
1614 
 
1615 
              when others =>
1616 
                cpuState <= STATE_FETCH;
1617 
            end case; -- unitControl2
1618 
 
1619 
          when STATE_RD1H => -- ##################################################
1620 
            case unitControl2 is
1621 
              when CODE_POP1 =>
1622 
                theRegisters(13) <= theRegisters(13) + 2;
1623 
                theRegisters(1)(31 downto 16) <= datain;
1624 
                if opcode(8 downto 2) = 0 then
1625 
                  addrMux  <= ADDR_PC;
1626 
                  cpuState <= STATE_FETCH;
1627 
                else
1628 
                  if opcode(2) = '1' then
1629 
                    cpuState <= STATE_RD2L;
1630 
                  elsif opcode(3) = '1' then
1631 
                    cpuState <= STATE_RD3L;
1632 
                  elsif opcode(4) = '1' then
1633 
                    cpuState <= STATE_RD4L;
1634 
                  elsif opcode(5) = '1' then
1635 
                    cpuState <= STATE_RD5L;
1636 
                  elsif opcode(6) = '1' then
1637 
                    cpuState <= STATE_RD6L;
1638 
                  elsif opcode(7) = '1' then
1639 
                    cpuState <= STATE_RD7L;
1640 
                  else
1641 
                    cpuState <= STATE_RDPL;
1642 
                  end if;
1643 
                end if;
1644 
              when CODE_LDMIA1 =>
1645 
                address <= address + 2;
1646 
                if opcode(7 downto 2) = 0 then
1647 
                  theRegisters(1)(31 downto 16) <= datain;
1648 
                  if opcode108 /= 1 then
1649 
                    if LDMread(opcode108) /= '1' then
1650 
                      theRegisters(opcode108) <= address + 2;
1651 
                    end if;
1652 
                  end if;
1653 
                  addrMux  <= ADDR_PC;
1654 
                  cpuState <= STATE_FETCH;
1655 
                else
1656 
                  theRegisters(1)(31 downto 16) <= datain;
1657 
                  if opcode(2) = '1' then
1658 
                    cpuState <= STATE_RD2L;
1659 
                  elsif opcode(3) = '1' then
1660 
                    cpuState <= STATE_RD3L;
1661 
                  elsif opcode(4) = '1' then
1662 
                    cpuState <= STATE_RD4L;
1663 
                  elsif opcode(5) = '1' then
1664 
                    cpuState <= STATE_RD5L;
1665 
                  elsif opcode(6) = '1' then
1666 
                    cpuState <= STATE_RD6L;
1667 
                  else
1668 
                    cpuState <= STATE_RD7L;
1669 
                  end if;
1670 
                end if;
1671 
 
1672 
              when others =>
1673 
                cpuState <= STATE_FETCH;
1674 
            end case; -- unitControl2
1675 
 
1676 
          when STATE_RD2L => -- ##################################################
1677 
            case unitControl2 is
1678 
              when CODE_POP1 =>
1679 
                theRegisters(13) <= theRegisters(13) + 2;
1680 
                theRegisters(2)(15 downto 0) <= datain;
1681 
                cpuState <= STATE_RD2H;
1682 
              when CODE_LDMIA1 =>
1683 
                LDMread(2) <= '1';
1684 
                theRegisters(2)(15 downto 0) <= datain;
1685 
                address <= address + 2;
1686 
                cpuState <= STATE_RD2H;
1687 
 
1688 
              when others =>
1689 
                cpuState <= STATE_FETCH;
1690 
            end case; -- unitControl2
1691 
 
1692 
          when STATE_RD2H => -- ##################################################
1693 
            case unitControl2 is
1694 
              when CODE_POP1 =>
1695 
                theRegisters(13) <= theRegisters(13) + 2;
1696 
                theRegisters(2)(31 downto 16) <= datain;
1697 
                if opcode(8 downto 3) = 0 then
1698 
                  addrMux  <= ADDR_PC;
1699 
                  cpuState <= STATE_FETCH;
1700 
                else
1701 
                  if opcode(3) = '1' then
1702 
                    cpuState <= STATE_RD3L;
1703 
                  elsif opcode(4) = '1' then
1704 
                    cpuState <= STATE_RD4L;
1705 
                  elsif opcode(5) = '1' then
1706 
                    cpuState <= STATE_RD5L;
1707 
                  elsif opcode(6) = '1' then
1708 
                    cpuState <= STATE_RD6L;
1709 
                  elsif opcode(7) = '1' then
1710 
                    cpuState <= STATE_RD7L;
1711 
                  else
1712 
                    cpuState <= STATE_RDPL;
1713 
                  end if;
1714 
                end if;
1715 
              when CODE_LDMIA1 =>
1716 
                address <= address + 2;
1717 
                if opcode(7 downto 3) = 0 then
1718 
                  addrMux  <= ADDR_PC;
1719 
                  theRegisters(2)(31 downto 16) <= datain;
1720 
                  if opcode108 /= 2 then
1721 
                    if LDMread(opcode108) /= '1' then
1722 
                      theRegisters(opcode108) <= address + 2;
1723 
                    end if;
1724 
                  end if;
1725 
                  cpuState <= STATE_FETCH;
1726 
                else
1727 
                  theRegisters(2)(31 downto 16) <= datain;
1728 
                  if opcode(3) = '1' then
1729 
                    cpuState <= STATE_RD3L;
1730 
                  elsif opcode(4) = '1' then
1731 
                    cpuState <= STATE_RD4L;
1732 
                  elsif opcode(5) = '1' then
1733 
                    cpuState <= STATE_RD5L;
1734 
                  elsif opcode(6) = '1' then
1735 
                    cpuState <= STATE_RD6L;
1736 
                  else
1737 
                    cpuState <= STATE_RD7L;
1738 
                  end if;
1739 
                end if;
1740 
 
1741 
              when others =>
1742 
                cpuState <= STATE_FETCH;
1743 
            end case; -- unitControl2
1744 
 
1745 
          when STATE_RD3L => -- ##################################################
1746 
            case unitControl2 is
1747 
              when CODE_POP1 =>
1748 
                theRegisters(13) <= theRegisters(13) + 2;
1749 
                theRegisters(3)(15 downto 0) <= datain;
1750 
                cpuState <= STATE_RD3H;
1751 
              when CODE_LDMIA1 =>
1752 
                LDMread(3) <= '1';
1753 
                theRegisters(3)(15 downto 0) <= datain;
1754 
                address <= address + 2;
1755 
                cpuState <= STATE_RD3H;
1756 
 
1757 
              when others =>
1758 
                cpuState <= STATE_FETCH;
1759 
            end case; -- unitControl2
1760 
 
1761 
          when STATE_RD3H => -- ##################################################
1762 
            case unitControl2 is
1763 
              when CODE_POP1 =>
1764 
                theRegisters(13) <= theRegisters(13) + 2;
1765 
                theRegisters(3)(31 downto 16) <= datain;
1766 
                if opcode(8 downto 4) = 0 then
1767 
                  addrMux  <= ADDR_PC;
1768 
                  cpuState <= STATE_FETCH;
1769 
                else
1770 
                  if opcode(4) = '1' then
1771 
                    cpuState <= STATE_RD4L;
1772 
                  elsif opcode(5) = '1' then
1773 
                    cpuState <= STATE_RD5L;
1774 
                  elsif opcode(6) = '1' then
1775 
                    cpuState <= STATE_RD6L;
1776 
                  elsif opcode(7) = '1' then
1777 
                    cpuState <= STATE_RD7L;
1778 
                  else
1779 
                    cpuState <= STATE_RDPL;
1780 
                  end if;
1781 
                end if;
1782 
              when CODE_LDMIA1 =>
1783 
                address <= address + 2;
1784 
                if opcode(7 downto 4) = 0 then
1785 
                  addrMux  <= ADDR_PC;
1786 
                  theRegisters(3)(31 downto 16) <= datain;
1787 
                  if opcode108 /= 3 then
1788 
                    if LDMread(opcode108) /= '1' then
1789 
                      theRegisters(opcode108) <= address + 2;
1790 
                    end if;
1791 
                  end if;
1792 
                  cpuState <= STATE_FETCH;
1793 
                else
1794 
                  theRegisters(3)(31 downto 16) <= datain;
1795 
                  if opcode(4) = '1' then
1796 
                    cpuState <= STATE_RD4L;
1797 
                  elsif opcode(5) = '1' then
1798 
                    cpuState <= STATE_RD5L;
1799 
                  elsif opcode(6) = '1' then
1800 
                    cpuState <= STATE_RD6L;
1801 
                  else
1802 
                    cpuState <= STATE_RD7L;
1803 
                  end if;
1804 
                end if;
1805 
 
1806 
              when others =>
1807 
                cpuState <= STATE_FETCH;
1808 
            end case; -- unitControl2
1809 
 
1810 
          when STATE_RD4L => -- ##################################################
1811 
            case unitControl2 is
1812 
              when CODE_POP1 =>
1813 
                theRegisters(13) <= theRegisters(13) + 2;
1814 
                theRegisters(4)(15 downto 0) <= datain;
1815 
                cpuState <= STATE_RD4H;
1816 
              when CODE_LDMIA1 =>
1817 
                LDMread(4) <= '1';
1818 
                theRegisters(4)(15 downto 0) <= datain;
1819 
                address <= address + 2;
1820 
                cpuState <= STATE_RD4H;
1821 
 
1822 
              when others =>
1823 
                cpuState <= STATE_FETCH;
1824 
            end case; -- unitControl2
1825 
 
1826 
          when STATE_RD4H => -- ##################################################
1827 
            case unitControl2 is
1828 
              when CODE_POP1 =>
1829 
                theRegisters(13) <= theRegisters(13) + 2;
1830 
                theRegisters(4)(31 downto 16) <= datain;
1831 
                if opcode(8 downto 5) = 0 then
1832 
                  addrMux  <= ADDR_PC;
1833 
                  cpuState <= STATE_FETCH;
1834 
                else
1835 
                  if opcode(5) = '1' then
1836 
                    cpuState <= STATE_RD5L;
1837 
                  elsif opcode(6) = '1' then
1838 
                    cpuState <= STATE_RD6L;
1839 
                  elsif opcode(7) = '1' then
1840 
                    cpuState <= STATE_RD7L;
1841 
                  else
1842 
                    cpuState <= STATE_RDPL;
1843 
                  end if;
1844 
                end if;
1845 
              when CODE_LDMIA1 =>
1846 
                address <= address + 2;
1847 
                if opcode(7 downto 5) = 0 then
1848 
                  addrMux  <= ADDR_PC;
1849 
                  theRegisters(4)(31 downto 16) <= datain;
1850 
                  if opcode108 /= 4 then
1851 
                    if LDMread(opcode108) /= '1' then
1852 
                      theRegisters(opcode108) <= address + 2;
1853 
                    end if;
1854 
                  end if;
1855 
                  cpuState <= STATE_FETCH;
1856 
                else
1857 
                  theRegisters(4)(31 downto 16) <= datain;
1858 
                  if opcode(5) = '1' then
1859 
                    cpuState <= STATE_RD5L;
1860 
                  elsif opcode(6) = '1' then
1861 
                    cpuState <= STATE_RD6L;
1862 
                  else
1863 
                    cpuState <= STATE_RD7L;
1864 
                  end if;
1865 
                end if;
1866 
 
1867 
              when others =>
1868 
                cpuState <= STATE_FETCH;
1869 
            end case; -- unitControl2
1870 
 
1871 
          when STATE_RD5L => -- ##################################################
1872 
            case unitControl2 is
1873 
              when CODE_POP1 =>
1874 
                theRegisters(13) <= theRegisters(13) + 2;
1875 
                theRegisters(5)(15 downto 0) <= datain;
1876 
                cpuState <= STATE_RD5H;
1877 
              when CODE_LDMIA1 =>
1878 
                LDMread(5) <= '1';
1879 
                theRegisters(5)(15 downto 0) <= datain;
1880 
                address <= address + 2;
1881 
                cpuState <= STATE_RD5H;
1882 
 
1883 
              when others =>
1884 
                cpuState <= STATE_FETCH;
1885 
            end case; -- unitControl2
1886 
 
1887 
          when STATE_RD5H => -- ##################################################
1888 
            case unitControl2 is
1889 
              when CODE_POP1 =>
1890 
                theRegisters(13) <= theRegisters(13) + 2;
1891 
                theRegisters(5)(31 downto 16) <= datain;
1892 
                if opcode(8 downto 6) = 0 then
1893 
                  addrMux  <= ADDR_PC;
1894 
                  cpuState <= STATE_FETCH;
1895 
                else
1896 
                  if opcode(6) = '1' then
1897 
                    cpuState <= STATE_RD6L;
1898 
                  elsif opcode(7) = '1' then
1899 
                    cpuState <= STATE_RD7L;
1900 
                  else
1901 
                    cpuState <= STATE_RDPL;
1902 
                  end if;
1903 
                end if;
1904 
              when CODE_LDMIA1 =>
1905 
                address <= address + 2;
1906 
                if opcode(7 downto 6) = 0 then
1907 
                  addrMux  <= ADDR_PC;
1908 
                  theRegisters(5)(31 downto 16) <= datain;
1909 
                  if opcode108 /= 5 then
1910 
                    if LDMread(opcode108) /= '1' then
1911 
                      theRegisters(opcode108) <= address + 2;
1912 
                    end if;
1913 
                  end if;
1914 
                  cpuState <= STATE_FETCH;
1915 
                else
1916 
                  theRegisters(5)(31 downto 16) <= datain;
1917 
                  if opcode(6) = '1' then
1918 
                    cpuState <= STATE_RD6L;
1919 
                  else
1920 
                    cpuState <= STATE_RD7L;
1921 
                  end if;
1922 
                end if;
1923 
 
1924 
              when others =>
1925 
                cpuState <= STATE_FETCH;
1926 
            end case; -- unitControl2
1927 
 
1928 
          when STATE_RD6L => -- ##################################################
1929 
            case unitControl2 is
1930 
              when CODE_POP1 =>
1931 
                theRegisters(13) <= theRegisters(13) + 2;
1932 
                theRegisters(6)(15 downto 0) <= datain;
1933 
                cpuState <= STATE_RD6H;
1934 
              when CODE_LDMIA1 =>
1935 
                LDMread(7) <= '1';
1936 
                theRegisters(6)(15 downto 0) <= datain;
1937 
                address <= address + 2;
1938 
                cpuState <= STATE_RD6H;
1939 
 
1940 
              when others =>
1941 
                cpuState <= STATE_FETCH;
1942 
            end case; -- unitControl2
1943 
 
1944 
          when STATE_RD6H => -- ##################################################
1945 
            case unitControl2 is
1946 
              when CODE_POP1 =>
1947 
                theRegisters(13) <= theRegisters(13) + 2;
1948 
                theRegisters(6)(31 downto 16) <= datain;
1949 
                if opcode(8 downto 7) = 0 then
1950 
                  addrMux  <= ADDR_PC;
1951 
                  cpuState <= STATE_FETCH;
1952 
                else
1953 
                  if opcode(7) = '1' then
1954 
                    cpuState <= STATE_RD7L;
1955 
                  else
1956 
                    cpuState <= STATE_RDPL;
1957 
                  end if;
1958 
                end if;
1959 
              when CODE_LDMIA1 =>
1960 
                address <= address + 2;
1961 
                if opcode(7) = '0' then
1962 
                  addrMux  <= ADDR_PC;
1963 
                  theRegisters(6)(31 downto 16) <= datain;
1964 
                  if opcode108 /= 6 then
1965 
                    if LDMread(opcode108) /= '1' then
1966 
                      theRegisters(opcode108) <= address + 2;
1967 
                    end if;
1968 
                  end if;
1969 
                  cpuState <= STATE_FETCH;
1970 
                else
1971 
                  theRegisters(6)(31 downto 16) <= datain;
1972 
                  cpuState <= STATE_RD7L;
1973 
                end if;
1974 
 
1975 
              when others =>
1976 
                cpuState <= STATE_FETCH;
1977 
            end case; -- unitControl2
1978 
 
1979 
          when STATE_RD7L => -- ##################################################
1980 
            case unitControl2 is
1981 
              when CODE_POP1 =>
1982 
                theRegisters(13) <= theRegisters(13) + 2;
1983 
                theRegisters(7)(15 downto 0) <= datain;
1984 
                cpuState <= STATE_RD7H;
1985 
              when CODE_LDMIA1 =>
1986 
                LDMread(7) <= '1';
1987 
                theRegisters(7)(15 downto 0) <= datain;
1988 
                address <= address + 2;
1989 
                cpuState <= STATE_RD7H;
1990 
 
1991 
              when others =>
1992 
                cpuState <= STATE_FETCH;
1993 
            end case; -- unitControl2
1994 
 
1995 
          when STATE_RD7H => -- ##################################################
1996 
            case unitControl2 is
1997 
              when CODE_POP1 =>
1998 
                theRegisters(13) <= theRegisters(13) + 2;
1999 
                theRegisters(7)(31 downto 16) <= datain;
2000 
                if opcode(8) = '0' then
2001 
                  addrMux  <= ADDR_PC;
2002 
                  cpuState <= STATE_FETCH;
2003 
                else
2004 
                  cpuState <= STATE_RDPL;
2005 
                end if;
2006 
              when CODE_LDMIA1 =>
2007 
                address <= address + 2;
2008 
                theRegisters(7)(31 downto 16) <= datain;
2009 
                if opcode108 /= 7 then
2010 
                  if LDMread(opcode108) /= '1' then
2011 
                    theRegisters(opcode108) <= address + 2;
2012 
                  end if;
2013 
                end if;
2014 
                addrMux  <= ADDR_PC;
2015 
                cpuState <= STATE_FETCH;
2016 
 
2017 
              when others =>
2018 
                cpuState <= STATE_FETCH;
2019 
            end case; -- unitControl2
2020 
 
2021 
          when STATE_RDPL => -- ##################################################
2022 
            case unitControl2 is
2023 
              when CODE_POP1 =>
2024 
                if theRegisters(14) = x"FFFFFFF9" then
2025 
                  cpuState <= STATE_RET;
2026 
                else
2027 
                  theRegisters(13) <= theRegisters(13) + 2;
2028 
                  theRegisters(15)(15 downto 0) <= datain;
2029 
                  cpuState <= STATE_RDPH;
2030 
                end if;
2031 
              when others =>
2032 
                cpuState <= STATE_FETCH;
2033 
            end case; -- unitControl2
2034 
 
2035 
          when STATE_RDPH => -- ##################################################
2036 
            case unitControl2 is
2037 
              when CODE_POP1 =>
2038 
                theRegisters(13) <= theRegisters(13) + 2;
2039 
                theRegisters(15)(31 downto 16) <= datain;
2040 
                addrMux  <= ADDR_PC;
2041 
                cpuState <= STATE_FETCH;
2042 
              when others =>
2043 
                cpuState <= STATE_FETCH;
2044 
            end case; -- unitControl2
2045 
 
2046 
 
2047 
 
2048 
          when STATE_WRITE1 => -- ##################################################
2049 
            case unitControl2 is
2050 
              when CODE_STR1 | CODE_STR2 =>
2051 
                address <= address + 2;
2052 
                dataout  <= theRegisters(opcode20)(31 downto 16);
2053 
                cpuState <= STATE_WRITE2;
2054 
              when CODE_STRH1 | CODE_STRB1 | CODE_STRB2 | CODE_STRH2 =>
2055 
                addrMux  <= ADDR_PC;
2056 
                writeL   <= '1';
2057 
                writeH   <= '1';
2058 
                cpuState <= STATE_FETCH;
2059 
              when CODE_STR3 =>
2060 
                address <= address + 2;
2061 
                dataout  <= theRegisters(opcode108)(31 downto 16);
2062 
                cpuState <= STATE_WRITE2;
2063 
 
2064 
              when others =>
2065 
                cpuState <= STATE_FETCH;
2066 
            end case; -- unitControl2
2067 
 
2068 
          when STATE_WRITE2 => -- ##################################################
2069 
            case unitControl2 is
2070 
              when CODE_STR1 | CODE_STR2 | CODE_STR3 =>
2071 
                addrMux  <= ADDR_PC;
2072 
                writeL   <= '1';
2073 
                writeH   <= '1';
2074 
                cpuState <= STATE_FETCH;
2075 
 
2076 
              when others =>
2077 
                cpuState <= STATE_FETCH;
2078 
            end case; -- unitControl2
2079 
 
2080 
          when STATE_WRPH =>  -- ##################################################
2081 
            case unitControl2 is
2082 
              when CODE_PUSH1 =>
2083 
                theRegisters(13) <= theRegisters(13) - 2;
2084 
                dataout  <= theRegisters(14)(15 downto 0);
2085 
                cpuState <= STATE_WRPL;
2086 
 
2087 
              when others =>
2088 
                writeL <= '1';
2089 
                writeH <= '1';
2090 
                cpuState <= STATE_FETCH;
2091 
            end case; -- unitControl2
2092 
 
2093 
          when STATE_WRPL =>  -- ##################################################
2094 
            case unitControl2 is
2095 
              when CODE_PUSH1 =>
2096 
                if opcode(7 downto 0) = 0 then
2097 
                  writeL   <= '1';
2098 
                  writeH   <= '1';
2099 
                  addrMux  <= ADDR_PC;
2100 
                  cpuState <= STATE_FETCH;
2101 
                else
2102 
                  theRegisters(13) <= theRegisters(13) - 2;
2103 
                  if opcode(7) = '1' then
2104 
                    dataout <= theRegisters(7)(31 downto 16);
2105 
                    cpuState <= STATE_WR7H;
2106 
                  elsif opcode(6) = '1' then
2107 
                    dataout <= theRegisters(6)(31 downto 16);
2108 
                    cpuState <= STATE_WR6H;
2109 
                  elsif opcode(5) = '1' then
2110 
                    dataout <= theRegisters(5)(31 downto 16);
2111 
                    cpuState <= STATE_WR5H;
2112 
                  elsif opcode(4) = '1' then
2113 
                    dataout <= theRegisters(4)(31 downto 16);
2114 
                    cpuState <= STATE_WR4H;
2115 
                  elsif opcode(3) = '1' then
2116 
                    dataout <= theRegisters(3)(31 downto 16);
2117 
                    cpuState <= STATE_WR3H;
2118 
                  elsif opcode(2) = '1' then
2119 
                    dataout <= theRegisters(2)(31 downto 16);
2120 
                    cpuState <= STATE_WR2H;
2121 
                  elsif opcode(1) = '1' then
2122 
                    dataout <= theRegisters(1)(31 downto 16);
2123 
                    cpuState <= STATE_WR1H;
2124 
                  else
2125 
                    dataout <= theRegisters(0)(31 downto 16);
2126 
                    cpuState <= STATE_WR0H;
2127 
                  end if;
2128 
                end if;
2129 
 
2130 
              when others =>
2131 
                writeL <= '1';
2132 
                writeH <= '1';
2133 
                cpuState <= STATE_FETCH;
2134 
            end case; -- unitControl2
2135 
 
2136 
          when STATE_WR7H =>  -- ##################################################
2137 
            case unitControl2 is
2138 
              when CODE_PUSH1 =>
2139 
                theRegisters(13) <= theRegisters(13) - 2;
2140 
                dataout  <= theRegisters(7)(15 downto 0);
2141 
                cpuState <= STATE_WR7L;
2142 
              when CODE_STMIA1 =>
2143 
                address <= address + 2;
2144 
                dataout <= theRegisters(7)(31 downto 16);
2145 
                cpuState <= STATE_WR7L;
2146 
 
2147 
              when others =>
2148 
                writeL <= '1';
2149 
                writeH <= '1';
2150 
                cpuState <= STATE_FETCH;
2151 
            end case; -- unitControl2
2152 
 
2153 
          when STATE_WR7L =>  -- ##################################################
2154 
            case unitControl2 is
2155 
              when CODE_PUSH1 =>
2156 
                if opcode(6 downto 0) = 0 then
2157 
                  writeL   <= '1';
2158 
                  writeH   <= '1';
2159 
                  addrMux  <= ADDR_PC;
2160 
                  cpuState <= STATE_FETCH;
2161 
                else
2162 
                  theRegisters(13) <= theRegisters(13) - 2;
2163 
                  if opcode(6) = '1' then
2164 
                    dataout <= theRegisters(6)(31 downto 16);
2165 
                    cpuState <= STATE_WR6H;
2166 
                  elsif opcode(5) = '1' then
2167 
                    dataout <= theRegisters(5)(31 downto 16);
2168 
                    cpuState <= STATE_WR5H;
2169 
                  elsif opcode(4) = '1' then
2170 
                    dataout <= theRegisters(4)(31 downto 16);
2171 
                    cpuState <= STATE_WR4H;
2172 
                  elsif opcode(3) = '1' then
2173 
                    dataout <= theRegisters(3)(31 downto 16);
2174 
                    cpuState <= STATE_WR3H;
2175 
                  elsif opcode(2) = '1' then
2176 
                    dataout <= theRegisters(2)(31 downto 16);
2177 
                    cpuState <= STATE_WR2H;
2178 
                  elsif opcode(1) = '1' then
2179 
                    dataout <= theRegisters(1)(31 downto 16);
2180 
                    cpuState <= STATE_WR1H;
2181 
                  else
2182 
                    dataout <= theRegisters(0)(31 downto 16);
2183 
                    cpuState <= STATE_WR0H;
2184 
                  end if;
2185 
                end if;
2186 
              when CODE_STMIA1 =>
2187 
                address <= address + 2;
2188 
                writeL <= '1';
2189 
                writeH <= '1';
2190 
                addrMux <= ADDR_PC;
2191 
                theRegisters(opcode108) <= address + 2;
2192 
                cpuState <= STATE_FETCH;
2193 
 
2194 
              when others =>
2195 
                writeL <= '1';
2196 
                writeH <= '1';
2197 
                cpuState <= STATE_FETCH;
2198 
            end case; -- unitControl2
2199 
 
2200 
          when STATE_WR6H =>  -- ##################################################
2201 
            case unitControl2 is
2202 
              when CODE_PUSH1 =>
2203 
                theRegisters(13) <= theRegisters(13) - 2;
2204 
                dataout  <= theRegisters(6)(15 downto 0);
2205 
                cpuState <= STATE_WR6L;
2206 
              when CODE_STMIA1 =>
2207 
                address <= address + 2;
2208 
                dataout <= theRegisters(6)(31 downto 16);
2209 
                cpuState <= STATE_WR6L;
2210 
 
2211 
              when others =>
2212 
                writeL <= '1';
2213 
                writeH <= '1';
2214 
                cpuState <= STATE_FETCH;
2215 
            end case; -- unitControl2
2216 
 
2217 
          when STATE_WR6L =>  -- ##################################################
2218 
            case unitControl2 is
2219 
              when CODE_PUSH1 =>
2220 
                if opcode(5 downto 0) = 0 then
2221 
                  writeL   <= '1';
2222 
                  writeH   <= '1';
2223 
                  addrMux  <= ADDR_PC;
2224 
                  cpuState <= STATE_FETCH;
2225 
                else
2226 
                  theRegisters(13) <= theRegisters(13) - 2;
2227 
                  if opcode(5) = '1' then
2228 
                    dataout <= theRegisters(5)(31 downto 16);
2229 
                    cpuState <= STATE_WR5H;
2230 
                  elsif opcode(4) = '1' then
2231 
                    dataout <= theRegisters(4)(31 downto 16);
2232 
                    cpuState <= STATE_WR4H;
2233 
                  elsif opcode(3) = '1' then
2234 
                    dataout <= theRegisters(3)(31 downto 16);
2235 
                    cpuState <= STATE_WR3H;
2236 
                  elsif opcode(2) = '1' then
2237 
                    dataout <= theRegisters(2)(31 downto 16);
2238 
                    cpuState <= STATE_WR2H;
2239 
                  elsif opcode(1) = '1' then
2240 
                    dataout <= theRegisters(1)(31 downto 16);
2241 
                    cpuState <= STATE_WR1H;
2242 
                  else
2243 
                    dataout <= theRegisters(0)(31 downto 16);
2244 
                    cpuState <= STATE_WR0H;
2245 
                  end if;
2246 
                end if;
2247 
              when CODE_STMIA1 =>
2248 
                address <= address + 2;
2249 
                if opcode(7) = '0' then
2250 
                  writeL <= '1';
2251 
                  writeH <= '1';
2252 
                  addrMux <= ADDR_PC;
2253 
                  theRegisters(opcode108) <= address + 2;
2254 
                  cpuState <= STATE_FETCH;
2255 
                else
2256 
                  dataout <= theRegisters(7)(15 downto 0);
2257 
                  cpuState <= STATE_WR7H;
2258 
                end if;
2259 
 
2260 
              when others =>
2261 
                writeL <= '1';
2262 
                writeH <= '1';
2263 
                cpuState <= STATE_FETCH;
2264 
            end case; -- unitControl2
2265 
 
2266 
          when STATE_WR5H =>  -- ##################################################
2267 
            case unitControl2 is
2268 
              when CODE_PUSH1 =>
2269 
                theRegisters(13) <= theRegisters(13) - 2;
2270 
                dataout  <= theRegisters(5)(15 downto 0);
2271 
                cpuState <= STATE_WR5L;
2272 
              when CODE_STMIA1 =>
2273 
                address <= address + 2;
2274 
                dataout <= theRegisters(5)(31 downto 16);
2275 
                cpuState <= STATE_WR5L;
2276 
 
2277 
              when others =>
2278 
                writeL <= '1';
2279 
                writeH <= '1';
2280 
                cpuState <= STATE_FETCH;
2281 
            end case; -- unitControl2
2282 
 
2283 
          when STATE_WR5L =>  -- ##################################################
2284 
            case unitControl2 is
2285 
              when CODE_PUSH1 =>
2286 
                if opcode(4 downto 0) = 0 then
2287 
                  writeL   <= '1';
2288 
                  writeH   <= '1';
2289 
                  addrMux  <= ADDR_PC;
2290 
                  cpuState <= STATE_FETCH;
2291 
                else
2292 
                  theRegisters(13) <= theRegisters(13) - 2;
2293 
                  if opcode(4) = '1' then
2294 
                    dataout <= theRegisters(4)(31 downto 16);
2295 
                    cpuState <= STATE_WR4H;
2296 
                  elsif opcode(3) = '1' then
2297 
                    dataout <= theRegisters(3)(31 downto 16);
2298 
                    cpuState <= STATE_WR3H;
2299 
                  elsif opcode(2) = '1' then
2300 
                    dataout <= theRegisters(2)(31 downto 16);
2301 
                    cpuState <= STATE_WR2H;
2302 
                  elsif opcode(1) = '1' then
2303 
                    dataout <= theRegisters(1)(31 downto 16);
2304 
                    cpuState <= STATE_WR1H;
2305 
                  else
2306 
                    dataout <= theRegisters(0)(31 downto 16);
2307 
                    cpuState <= STATE_WR0H;
2308 
                  end if;
2309 
                end if;
2310 
              when CODE_STMIA1 =>
2311 
                address <= address + 2;
2312 
                if opcode(7 downto 6) = 0 then
2313 
                  writeL <= '1';
2314 
                  writeH <= '1';
2315 
                  addrMux <= ADDR_PC;
2316 
                  theRegisters(opcode108) <= address + 2;
2317 
                  cpuState <= STATE_FETCH;
2318 
                else
2319 
                  if opcode(6) = '1' then
2320 
                    dataout <= theRegisters(6)(15 downto 0);
2321 
                    cpuState <= STATE_WR6H;
2322 
                  else
2323 
                    dataout <= theRegisters(7)(15 downto 0);
2324 
                    cpuState <= STATE_WR7H;
2325 
                  end if;
2326 
                end if;
2327 
 
2328 
              when others =>
2329 
                writeL <= '1';
2330 
                writeH <= '1';
2331 
                cpuState <= STATE_FETCH;
2332 
            end case; -- unitControl2
2333 
 
2334 
          when STATE_WR4H =>  -- ##################################################
2335 
            case unitControl2 is
2336 
              when CODE_PUSH1 =>
2337 
                theRegisters(13) <= theRegisters(13) - 2;
2338 
                dataout  <= theRegisters(4)(15 downto 0);
2339 
                cpuState <= STATE_WR4L;
2340 
              when CODE_STMIA1 =>
2341 
                address <= address + 2;
2342 
                dataout <= theRegisters(4)(31 downto 16);
2343 
                cpuState <= STATE_WR4L;
2344 
 
2345 
              when others =>
2346 
                writeL <= '1';
2347 
                writeH <= '1';
2348 
                cpuState <= STATE_FETCH;
2349 
            end case; -- unitControl2
2350 
 
2351 
          when STATE_WR4L =>  -- ##################################################
2352 
            case unitControl2 is
2353 
              when CODE_PUSH1 =>
2354 
                if opcode(3 downto 0) = 0 then
2355 
                  writeL   <= '1';
2356 
                  writeH   <= '1';
2357 
                  addrMux  <= ADDR_PC;
2358 
                  cpuState <= STATE_FETCH;
2359 
                else
2360 
                  theRegisters(13) <= theRegisters(13) - 2;
2361 
                  if opcode(3) = '1' then
2362 
                    dataout <= theRegisters(3)(31 downto 16);
2363 
                    cpuState <= STATE_WR3H;
2364 
                  elsif opcode(2) = '1' then
2365 
                    dataout <= theRegisters(2)(31 downto 16);
2366 
                    cpuState <= STATE_WR2H;
2367 
                  elsif opcode(1) = '1' then
2368 
                    dataout <= theRegisters(1)(31 downto 16);
2369 
                    cpuState <= STATE_WR1H;
2370 
                  else
2371 
                    dataout <= theRegisters(0)(31 downto 16);
2372 
                    cpuState <= STATE_WR0H;
2373 
                  end if;
2374 
                end if;
2375 
              when CODE_STMIA1 =>
2376 
                address <= address + 2;
2377 
                if opcode(7 downto 5) = 0 then
2378 
                  writeL <= '1';
2379 
                  writeH <= '1';
2380 
                  addrMux <= ADDR_PC;
2381 
                  theRegisters(opcode108) <= address + 2;
2382 
                  cpuState <= STATE_FETCH;
2383 
                else
2384 
                  if opcode(5) = '1' then
2385 
                    dataout <= theRegisters(5)(15 downto 0);
2386 
                    cpuState <= STATE_WR5H;
2387 
                  elsif opcode(6) = '1' then
2388 
                    dataout <= theRegisters(6)(15 downto 0);
2389 
                    cpuState <= STATE_WR6H;
2390 
                  else
2391 
                    dataout <= theRegisters(7)(15 downto 0);
2392 
                    cpuState <= STATE_WR7H;
2393 
                  end if;
2394 
                end if;
2395 
 
2396 
              when others =>
2397 
                writeL <= '1';
2398 
                writeH <= '1';
2399 
                cpuState <= STATE_FETCH;
2400 
            end case; -- unitControl2
2401 
 
2402 
          when STATE_WR3H =>  -- ##################################################
2403 
            case unitControl2 is
2404 
              when CODE_PUSH1 =>
2405 
                theRegisters(13) <= theRegisters(13) - 2;
2406 
                dataout  <= theRegisters(3)(15 downto 0);
2407 
                cpuState <= STATE_WR3L;
2408 
              when CODE_STMIA1 =>
2409 
                address <= address + 2;
2410 
                dataout <= theRegisters(3)(31 downto 16);
2411 
                cpuState <= STATE_WR3L;
2412 
 
2413 
              when others =>
2414 
                writeL <= '1';
2415 
                writeH <= '1';
2416 
                cpuState <= STATE_FETCH;
2417 
            end case; -- unitControl2
2418 
 
2419 
          when STATE_WR3L =>  -- ##################################################
2420 
            case unitControl2 is
2421 
              when CODE_PUSH1 =>
2422 
                if opcode(2 downto 0) = 0 then
2423 
                  writeL   <= '1';
2424 
                  writeH   <= '1';
2425 
                  addrMux  <= ADDR_PC;
2426 
                  cpuState <= STATE_FETCH;
2427 
                else
2428 
                  theRegisters(13) <= theRegisters(13) - 2;
2429 
                  if opcode(2) = '1' then
2430 
                    dataout <= theRegisters(2)(31 downto 16);
2431 
                    cpuState <= STATE_WR2H;
2432 
                  elsif opcode(1) = '1' then
2433 
                    dataout <= theRegisters(1)(31 downto 16);
2434 
                    cpuState <= STATE_WR1H;
2435 
                  else
2436 
                    dataout <= theRegisters(0)(31 downto 16);
2437 
                    cpuState <= STATE_WR0H;
2438 
                  end if;
2439 
                end if;
2440 
              when CODE_STMIA1 =>
2441 
                address <= address + 2;
2442 
                if opcode(7 downto 4) = 0 then
2443 
                  writeL <= '1';
2444 
                  writeH <= '1';
2445 
                  addrMux <= ADDR_PC;
2446 
                  theRegisters(opcode108) <= address + 2;
2447 
                  cpuState <= STATE_FETCH;
2448 
                else
2449 
                  if opcode(4) = '1' then
2450 
                    dataout <= theRegisters(4)(15 downto 0);
2451 
                    cpuState <= STATE_WR4H;
2452 
                  elsif opcode(5) = '1' then
2453 
                    dataout <= theRegisters(5)(15 downto 0);
2454 
                    cpuState <= STATE_WR5H;
2455 
                  elsif opcode(6) = '1' then
2456 
                    dataout <= theRegisters(6)(15 downto 0);
2457 
                    cpuState <= STATE_WR6H;
2458 
                  else
2459 
                    dataout <= theRegisters(7)(15 downto 0);
2460 
                    cpuState <= STATE_WR7H;
2461 
                  end if;
2462 
                end if;
2463 
 
2464 
              when others =>
2465 
                writeL <= '1';
2466 
                writeH <= '1';
2467 
                cpuState <= STATE_FETCH;
2468 
            end case; -- unitControl2
2469 
 
2470 
          when STATE_WR2H =>  -- ##################################################
2471 
            case unitControl2 is
2472 
              when CODE_PUSH1 =>
2473 
                theRegisters(13) <= theRegisters(13) - 2;
2474 
                dataout  <= theRegisters(2)(15 downto 0);
2475 
                cpuState <= STATE_WR2L;
2476 
              when CODE_STMIA1 =>
2477 
                address <= address + 2;
2478 
                dataout <= theRegisters(2)(31 downto 16);
2479 
                cpuState <= STATE_WR2L;
2480 
 
2481 
              when others =>
2482 
                writeL <= '1';
2483 
                writeH <= '1';
2484 
                cpuState <= STATE_FETCH;
2485 
            end case; -- unitControl2
2486 
 
2487 
          when STATE_WR2L =>  -- ##################################################
2488 
            case unitControl2 is
2489 
              when CODE_PUSH1 =>
2490 
                if opcode(1 downto 0) = 0 then
2491 
                  writeL   <= '1';
2492 
                  writeH   <= '1';
2493 
                  addrMux  <= ADDR_PC;
2494 
                  cpuState <= STATE_FETCH;
2495 
                else
2496 
                  theRegisters(13) <= theRegisters(13) - 2;
2497 
                  if opcode(1) = '1' then
2498 
                    dataout <= theRegisters(1)(31 downto 16);
2499 
                    cpuState <= STATE_WR1H;
2500 
                  else
2501 
                    dataout <= theRegisters(0)(31 downto 16);
2502 
                    cpuState <= STATE_WR0H;
2503 
                  end if;
2504 
                end if;
2505 
              when CODE_STMIA1 =>
2506 
                address <= address + 2;
2507 
                if opcode(7 downto 3) = 0 then
2508 
                  writeL <= '1';
2509 
                  writeH <= '1';
2510 
                  addrMux <= ADDR_PC;
2511 
                  theRegisters(opcode108) <= address + 2;
2512 
                  cpuState <= STATE_FETCH;
2513 
                else
2514 
                  if opcode(3) = '1' then
2515 
                    dataout <= theRegisters(3)(15 downto 0);
2516 
                    cpuState <= STATE_WR3H;
2517 
                  elsif opcode(4) = '1' then
2518 
                    dataout <= theRegisters(4)(15 downto 0);
2519 
                    cpuState <= STATE_WR4H;
2520 
                  elsif opcode(5) = '1' then
2521 
                    dataout <= theRegisters(5)(15 downto 0);
2522 
                    cpuState <= STATE_WR5H;
2523 
                  elsif opcode(6) = '1' then
2524 
                    dataout <= theRegisters(6)(15 downto 0);
2525 
                    cpuState <= STATE_WR6H;
2526 
                  else
2527 
                    dataout <= theRegisters(7)(15 downto 0);
2528 
                    cpuState <= STATE_WR7H;
2529 
                  end if;
2530 
                end if;
2531 
 
2532 
              when others =>
2533 
                writeL <= '1';
2534 
                writeH <= '1';
2535 
                cpuState <= STATE_FETCH;
2536 
            end case; -- unitControl2
2537 
 
2538 
          when STATE_WR1H =>  -- ##################################################
2539 
            case unitControl2 is
2540 
              when CODE_PUSH1 =>
2541 
                theRegisters(13) <= theRegisters(13) - 2;
2542 
                dataout  <= theRegisters(1)(15 downto 0);
2543 
                cpuState <= STATE_WR1L;
2544 
              when CODE_STMIA1 =>
2545 
                address <= address + 2;
2546 
                dataout <= theRegisters(1)(31 downto 16);
2547 
                cpuState <= STATE_WR1L;
2548 
 
2549 
              when others =>
2550 
                writeL <= '1';
2551 
                writeH <= '1';
2552 
                cpuState <= STATE_FETCH;
2553 
            end case; -- unitControl2
2554 
 
2555 
          when STATE_WR1L =>  -- ##################################################
2556 
            case unitControl2 is
2557 
              when CODE_PUSH1 =>
2558 
                if opcode(0) = '0' then
2559 
                  writeL   <= '1';
2560 
                  writeH   <= '1';
2561 
                  addrMux  <= ADDR_PC;
2562 
                  cpuState <= STATE_FETCH;
2563 
                else
2564 
                  theRegisters(13) <= theRegisters(13) - 2;
2565 
                  dataout <= theRegisters(0)(31 downto 16);
2566 
                  cpuState <= STATE_WR0H;
2567 
                end if;
2568 
            when CODE_STMIA1 =>
2569 
                address <= address + 2;
2570 
                if opcode(7 downto 2) = 0 then
2571 
                  writeL <= '1';
2572 
                  writeH <= '1';
2573 
                  addrMux <= ADDR_PC;
2574 
                  theRegisters(opcode108) <= address + 2;
2575 
                  cpuState <= STATE_FETCH;
2576 
                else
2577 
                  if opcode(2) = '1' then
2578 
                    dataout <= theRegisters(2)(15 downto 0);
2579 
                    cpuState <= STATE_WR2H;
2580 
                  elsif opcode(3) = '1' then
2581 
                    dataout <= theRegisters(3)(15 downto 0);
2582 
                    cpuState <= STATE_WR3H;
2583 
                  elsif opcode(4) = '1' then
2584 
                    dataout <= theRegisters(4)(15 downto 0);
2585 
                    cpuState <= STATE_WR4H;
2586 
                  elsif opcode(5) = '1' then
2587 
                    dataout <= theRegisters(5)(15 downto 0);
2588 
                    cpuState <= STATE_WR5H;
2589 
                  elsif opcode(6) = '1' then
2590 
                    dataout <= theRegisters(6)(15 downto 0);
2591 
                    cpuState <= STATE_WR6H;
2592 
                  else
2593 
                    dataout <= theRegisters(7)(15 downto 0);
2594 
                    cpuState <= STATE_WR7H;
2595 
                  end if;
2596 
                end if;
2597 
 
2598 
              when others =>
2599 
                writeL <= '1';
2600 
                writeH <= '1';
2601 
                cpuState <= STATE_FETCH;
2602 
            end case; -- unitControl2
2603 
 
2604 
          when STATE_WR0H =>  -- ##################################################
2605 
            case unitControl2 is
2606 
              when CODE_PUSH1 =>
2607 
                theRegisters(13) <= theRegisters(13) - 2;
2608 
                dataout  <= theRegisters(0)(15 downto 0);
2609 
                cpuState <= STATE_WR0L;
2610 
              when CODE_STMIA1 =>
2611 
                address <= address + 2;
2612 
                dataout <= theRegisters(0)(31 downto 16);
2613 
                cpuState <= STATE_WR0L;
2614 
 
2615 
 
2616 
              when others =>
2617 
                writeL <= '1';
2618 
                writeH <= '1';
2619 
                cpuState <= STATE_FETCH;
2620 
            end case; -- unitControl2
2621 
 
2622 
          when STATE_WR0L =>  -- ##################################################
2623 
            case unitControl2 is
2624 
              when CODE_PUSH1 =>
2625 
                writeL   <= '1';
2626 
                writeH   <= '1';
2627 
                addrMux  <= ADDR_PC;
2628 
                cpuState <= STATE_FETCH;
2629 
              when CODE_STMIA1 =>
2630 
                address <= address + 2;
2631 
                if opcode(7 downto 1) = 0 then
2632 
                  writeL <= '1';
2633 
                  writeH <= '1';
2634 
                  addrMux <= ADDR_PC;
2635 
                  theRegisters(opcode108) <= address + 2;
2636 
                  cpuState <= STATE_FETCH;
2637 
                else
2638 
                  if opcode(1) = '1' then
2639 
                    dataout <= theRegisters(1)(15 downto 0);
2640 
                    cpuState <= STATE_WR1H;
2641 
                  elsif opcode(2) = '1' then
2642 
                    dataout <= theRegisters(2)(15 downto 0);
2643 
                    cpuState <= STATE_WR2H;
2644 
                  elsif opcode(3) = '1' then
2645 
                    dataout <= theRegisters(3)(15 downto 0);
2646 
                    cpuState <= STATE_WR3H;
2647 
                  elsif opcode(4) = '1' then
2648 
                    dataout <= theRegisters(4)(15 downto 0);
2649 
                    cpuState <= STATE_WR4H;
2650 
                  elsif opcode(5) = '1' then
2651 
                    dataout <= theRegisters(5)(15 downto 0);
2652 
                    cpuState <= STATE_WR5H;
2653 
                  elsif opcode(6) = '1' then
2654 
                    dataout <= theRegisters(6)(15 downto 0);
2655 
                    cpuState <= STATE_WR6H;
2656 
                  else
2657 
                    dataout <= theRegisters(7)(15 downto 0);
2658 
                    cpuState <= STATE_WR7H;
2659 
                  end if;
2660 
                end if;
2661 
 
2662 
              when others =>
2663 
                writeL <= '1';
2664 
                writeH <= '1';
2665 
                cpuState <= STATE_FETCH;
2666 
            end case; -- unitControl2
2667 
 
2668 
 
2669 
 
2670 
          when others =>
2671 
            cpuState <= STATE_FETCH;
2672 
        end case; -- cpuState
2673 
      end if; -- rst = '0'
2674 
    end if; -- rising_edge(clk)
2675 
  end process;
2676 
 
2677 
 
2678 
end behavior;

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