| 1 |
10 |
riedelx |
---------------------------------------------------------------
|
| 2 |
|
|
-- CortexI a CortexM3 CPU clone
|
| 3 |
|
|
-- Ulrich Riedel
|
| 4 |
|
|
-- 2009.09.10
|
| 5 |
|
|
-- supplied at LGPL
|
| 6 |
|
|
-- riedel@ziffernkasten.de
|
| 7 |
|
|
-- search for #MAIN# for CortexI CPU
|
| 8 |
|
|
---------------------------------------------------------------
|
| 9 |
|
|
library IEEE;
|
| 10 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
| 11 |
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
| 12 |
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
| 13 |
|
|
|
| 14 |
|
|
package CortexIinclude is
|
| 15 |
|
|
|
| 16 |
|
|
constant SIZE_8BIT : std_logic_vector(1 downto 0) := "00";
|
| 17 |
|
|
constant SIZE_16BIT : std_logic_vector(1 downto 0) := "01";
|
| 18 |
|
|
constant SIZE_32BIT : std_logic_vector(1 downto 0) := "10";
|
| 19 |
|
|
constant SIZE_32SBIT : std_logic_vector(1 downto 0) := "11";
|
| 20 |
|
|
|
| 21 |
|
|
constant BS_ROL : std_logic_vector(2 downto 0) := "000";
|
| 22 |
|
|
constant BS_LSL : std_logic_vector(2 downto 0) := "001";
|
| 23 |
|
|
constant BS_ROR : std_logic_vector(2 downto 0) := "010";
|
| 24 |
|
|
constant BS_LSR : std_logic_vector(2 downto 0) := "011";
|
| 25 |
|
|
constant BS_ASR : std_logic_vector(2 downto 0) := "100";
|
| 26 |
|
|
|
| 27 |
|
|
end CortexIinclude;
|
| 28 |
|
|
|
| 29 |
|
|
package body CortexIinclude is
|
| 30 |
|
|
|
| 31 |
|
|
end CortexIinclude;
|
| 32 |
|
|
|
| 33 |
|
|
--------------------------------------------------------------
|
| 34 |
|
|
library IEEE;
|
| 35 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
| 36 |
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
| 37 |
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
| 38 |
|
|
|
| 39 |
|
|
use work.CortexIinclude.ALL;
|
| 40 |
|
|
|
| 41 |
|
|
entity bshifter is Port(
|
| 42 |
|
|
din : in std_logic_vector(31 downto 0);
|
| 43 |
|
|
size : in std_logic_vector( 1 downto 0);
|
| 44 |
|
|
mode : in std_logic_vector( 2 downto 0);
|
| 45 |
|
|
count : in std_logic_vector( 4 downto 0);
|
| 46 |
|
|
cyOut : out std_logic;
|
| 47 |
|
|
dout : out std_logic_vector(31 downto 0)
|
| 48 |
|
|
);
|
| 49 |
|
|
end bshifter;
|
| 50 |
|
|
|
| 51 |
|
|
Library UNISIM;
|
| 52 |
|
|
use UNISIM.vcomponents.all;
|
| 53 |
|
|
|
| 54 |
|
|
architecture behavioral of bshifter is
|
| 55 |
|
|
|
| 56 |
|
|
signal shift : std_logic_vector(4 downto 0);
|
| 57 |
|
|
signal ENCODE : STD_LOGIC_VECTOR (17 downto 0);
|
| 58 |
|
|
signal WORDA : STD_LOGIC_VECTOR (17 downto 0);
|
| 59 |
|
|
signal WORDB : STD_LOGIC_VECTOR (17 downto 0);
|
| 60 |
|
|
signal WORDC : STD_LOGIC_VECTOR (17 downto 0);
|
| 61 |
|
|
signal WORDD : STD_LOGIC_VECTOR (17 downto 0);
|
| 62 |
|
|
|
| 63 |
|
|
signal OUTA : STD_LOGIC_VECTOR (35 downto 0);
|
| 64 |
|
|
signal OUTB : STD_LOGIC_VECTOR (35 downto 0);
|
| 65 |
|
|
signal OUTC : STD_LOGIC_VECTOR (35 downto 0);
|
| 66 |
|
|
signal OUTD : STD_LOGIC_VECTOR (35 downto 0);
|
| 67 |
|
|
|
| 68 |
|
|
signal temp : std_logic_vector(31 downto 0);
|
| 69 |
|
|
|
| 70 |
|
|
signal input : std_logic_vector(31 downto 0);
|
| 71 |
|
|
signal output : std_logic_vector(31 downto 0);
|
| 72 |
|
|
|
| 73 |
|
|
begin
|
| 74 |
|
|
|
| 75 |
|
|
process(din, size) -- data in multiplexor
|
| 76 |
|
|
begin
|
| 77 |
|
|
case size is
|
| 78 |
|
|
when SIZE_8BIT => -- 8bit
|
| 79 |
|
|
input <= din(7 downto 0) &
|
| 80 |
|
|
din(7 downto 0) &
|
| 81 |
|
|
din(7 downto 0) &
|
| 82 |
|
|
din(7 downto 0);
|
| 83 |
|
|
when SIZE_16BIT => -- 16bit
|
| 84 |
|
|
input <= din(15 downto 0) & din(15 downto 0);
|
| 85 |
|
|
when SIZE_32BIT | SIZE_32SBIT => -- 32bit
|
| 86 |
|
|
input <= din;
|
| 87 |
|
|
when others =>
|
| 88 |
|
|
null;
|
| 89 |
|
|
end case; -- size
|
| 90 |
|
|
end process;
|
| 91 |
|
|
|
| 92 |
|
|
process(output, size, mode) -- data output multiplexor
|
| 93 |
|
|
begin
|
| 94 |
|
|
case size is
|
| 95 |
|
|
when SIZE_8BIT => -- 8bit
|
| 96 |
|
|
case mode is
|
| 97 |
|
|
when "000" => -- ROL
|
| 98 |
|
|
dout <= output;
|
| 99 |
|
|
when "001" => -- LSL
|
| 100 |
|
|
dout <= output;
|
| 101 |
|
|
when "010" => -- ROR
|
| 102 |
|
|
dout <= output;
|
| 103 |
|
|
when "011" => -- LSR
|
| 104 |
|
|
dout <= x"000000" & output(31 downto 24);
|
| 105 |
|
|
when "100" => -- ASR
|
| 106 |
|
|
dout <= x"000000" & output(31 downto 24);
|
| 107 |
|
|
when others =>
|
| 108 |
|
|
dout <= output;
|
| 109 |
|
|
end case; -- mode
|
| 110 |
|
|
when SIZE_16BIT => -- 16bit
|
| 111 |
|
|
case mode is
|
| 112 |
|
|
when "000" => -- ROL
|
| 113 |
|
|
dout <= output;
|
| 114 |
|
|
when "001" => -- LSL
|
| 115 |
|
|
dout <= output;
|
| 116 |
|
|
when "010" => -- ROR
|
| 117 |
|
|
dout <= output;
|
| 118 |
|
|
when "011" => -- LSR
|
| 119 |
|
|
dout <= x"0000" & output(31 downto 16);
|
| 120 |
|
|
when "100" => -- ASR
|
| 121 |
|
|
dout <= x"0000" & output(31 downto 16);
|
| 122 |
|
|
when others =>
|
| 123 |
|
|
dout <= output;
|
| 124 |
|
|
end case; -- mode
|
| 125 |
|
|
when SIZE_32BIT | SIZE_32SBIT => -- 32bit
|
| 126 |
|
|
dout <= output;
|
| 127 |
|
|
when others =>
|
| 128 |
|
|
null;
|
| 129 |
|
|
end case; -- size
|
| 130 |
|
|
end process;
|
| 131 |
|
|
|
| 132 |
|
|
process(count, mode, temp, input)
|
| 133 |
|
|
begin
|
| 134 |
|
|
case mode is
|
| 135 |
|
|
when BS_ROL => -- ROL
|
| 136 |
|
|
shift <= count;
|
| 137 |
|
|
output <= temp;
|
| 138 |
|
|
cyOut <= input(conv_integer(32 - count));
|
| 139 |
|
|
when BS_LSL => -- LSL
|
| 140 |
|
|
shift <= count;
|
| 141 |
|
|
cyOut <= input(conv_integer(32 - count));
|
| 142 |
|
|
case count is
|
| 143 |
|
|
when "00000" =>
|
| 144 |
|
|
output <= temp;
|
| 145 |
|
|
when "00001" =>
|
| 146 |
|
|
output <= temp and "11111111111111111111111111111110";
|
| 147 |
|
|
when "00010" =>
|
| 148 |
|
|
output <= temp and "11111111111111111111111111111100";
|
| 149 |
|
|
when "00011" =>
|
| 150 |
|
|
output <= temp and "11111111111111111111111111111000";
|
| 151 |
|
|
when "00100" =>
|
| 152 |
|
|
output <= temp and "11111111111111111111111111110000";
|
| 153 |
|
|
when "00101" =>
|
| 154 |
|
|
output <= temp and "11111111111111111111111111100000";
|
| 155 |
|
|
when "00110" =>
|
| 156 |
|
|
output <= temp and "11111111111111111111111111000000";
|
| 157 |
|
|
when "00111" =>
|
| 158 |
|
|
output <= temp and "11111111111111111111111110000000";
|
| 159 |
|
|
when "01000" =>
|
| 160 |
|
|
output <= temp and "11111111111111111111111100000000";
|
| 161 |
|
|
when "01001" =>
|
| 162 |
|
|
output <= temp and "11111111111111111111111000000000";
|
| 163 |
|
|
when "01010" =>
|
| 164 |
|
|
output <= temp and "11111111111111111111110000000000";
|
| 165 |
|
|
when "01011" =>
|
| 166 |
|
|
output <= temp and "11111111111111111111100000000000";
|
| 167 |
|
|
when "01100" =>
|
| 168 |
|
|
output <= temp and "11111111111111111111000000000000";
|
| 169 |
|
|
when "01101" =>
|
| 170 |
|
|
output <= temp and "11111111111111111110000000000000";
|
| 171 |
|
|
when "01110" =>
|
| 172 |
|
|
output <= temp and "11111111111111111100000000000000";
|
| 173 |
|
|
when "01111" =>
|
| 174 |
|
|
output <= temp and "11111111111111111000000000000000";
|
| 175 |
|
|
when "10000" =>
|
| 176 |
|
|
output <= temp and "11111111111111110000000000000000";
|
| 177 |
|
|
when "10001" =>
|
| 178 |
|
|
output <= temp and "11111111111111100000000000000000";
|
| 179 |
|
|
when "10010" =>
|
| 180 |
|
|
output <= temp and "11111111111111000000000000000000";
|
| 181 |
|
|
when "10011" =>
|
| 182 |
|
|
output <= temp and "11111111111110000000000000000000";
|
| 183 |
|
|
when "10100" =>
|
| 184 |
|
|
output <= temp and "11111111111100000000000000000000";
|
| 185 |
|
|
when "10101" =>
|
| 186 |
|
|
output <= temp and "11111111111000000000000000000000";
|
| 187 |
|
|
when "10110" =>
|
| 188 |
|
|
output <= temp and "11111111110000000000000000000000";
|
| 189 |
|
|
when "10111" =>
|
| 190 |
|
|
output <= temp and "11111111100000000000000000000000";
|
| 191 |
|
|
when "11000" =>
|
| 192 |
|
|
output <= temp and "11111111000000000000000000000000";
|
| 193 |
|
|
when "11001" =>
|
| 194 |
|
|
output <= temp and "11111110000000000000000000000000";
|
| 195 |
|
|
when "11010" =>
|
| 196 |
|
|
output <= temp and "11111100000000000000000000000000";
|
| 197 |
|
|
when "11011" =>
|
| 198 |
|
|
output <= temp and "11111000000000000000000000000000";
|
| 199 |
|
|
when "11100" =>
|
| 200 |
|
|
output <= temp and "11110000000000000000000000000000";
|
| 201 |
|
|
when "11101" =>
|
| 202 |
|
|
output <= temp and "11100000000000000000000000000000";
|
| 203 |
|
|
when "11110" =>
|
| 204 |
|
|
output <= temp and "11000000000000000000000000000000";
|
| 205 |
|
|
when "11111" =>
|
| 206 |
|
|
output <= temp and "10000000000000000000000000000000";
|
| 207 |
|
|
when others =>
|
| 208 |
|
|
output <= temp;
|
| 209 |
|
|
end case; -- count
|
| 210 |
|
|
when BS_ROR => -- ROR
|
| 211 |
|
|
shift <= 32 - count;
|
| 212 |
|
|
output <= temp;
|
| 213 |
|
|
cyOut <= input(conv_integer(count - 1));
|
| 214 |
|
|
when BS_LSR => -- LSR
|
| 215 |
|
|
shift <= 32 - count;
|
| 216 |
|
|
cyOut <= input(conv_integer(count - 1));
|
| 217 |
|
|
case count is
|
| 218 |
|
|
when "00000" =>
|
| 219 |
|
|
output <= temp;
|
| 220 |
|
|
when "00001" =>
|
| 221 |
|
|
output <= temp and "01111111111111111111111111111111";
|
| 222 |
|
|
when "00010" =>
|
| 223 |
|
|
output <= temp and "00111111111111111111111111111111";
|
| 224 |
|
|
when "00011" =>
|
| 225 |
|
|
output <= temp and "00011111111111111111111111111111";
|
| 226 |
|
|
when "00100" =>
|
| 227 |
|
|
output <= temp and "00001111111111111111111111111111";
|
| 228 |
|
|
when "00101" =>
|
| 229 |
|
|
output <= temp and "00000111111111111111111111111111";
|
| 230 |
|
|
when "00110" =>
|
| 231 |
|
|
output <= temp and "00000011111111111111111111111111";
|
| 232 |
|
|
when "00111" =>
|
| 233 |
|
|
output <= temp and "00000001111111111111111111111111";
|
| 234 |
|
|
when "01000" =>
|
| 235 |
|
|
output <= temp and "00000000111111111111111111111111";
|
| 236 |
|
|
when "01001" =>
|
| 237 |
|
|
output <= temp and "00000000011111111111111111111111";
|
| 238 |
|
|
when "01010" =>
|
| 239 |
|
|
output <= temp and "00000000001111111111111111111111";
|
| 240 |
|
|
when "01011" =>
|
| 241 |
|
|
output <= temp and "00000000000111111111111111111111";
|
| 242 |
|
|
when "01100" =>
|
| 243 |
|
|
output <= temp and "00000000000011111111111111111111";
|
| 244 |
|
|
when "01101" =>
|
| 245 |
|
|
output <= temp and "00000000000001111111111111111111";
|
| 246 |
|
|
when "01110" =>
|
| 247 |
|
|
output <= temp and "00000000000000111111111111111111";
|
| 248 |
|
|
when "01111" =>
|
| 249 |
|
|
output <= temp and "00000000000000011111111111111111";
|
| 250 |
|
|
when "10000" =>
|
| 251 |
|
|
output <= temp and "00000000000000001111111111111111";
|
| 252 |
|
|
when "10001" =>
|
| 253 |
|
|
output <= temp and "00000000000000000111111111111111";
|
| 254 |
|
|
when "10010" =>
|
| 255 |
|
|
output <= temp and "00000000000000000011111111111111";
|
| 256 |
|
|
when "10011" =>
|
| 257 |
|
|
output <= temp and "00000000000000000001111111111111";
|
| 258 |
|
|
when "10100" =>
|
| 259 |
|
|
output <= temp and "00000000000000000000111111111111";
|
| 260 |
|
|
when "10101" =>
|
| 261 |
|
|
output <= temp and "00000000000000000000011111111111";
|
| 262 |
|
|
when "10110" =>
|
| 263 |
|
|
output <= temp and "00000000000000000000001111111111";
|
| 264 |
|
|
when "10111" =>
|
| 265 |
|
|
output <= temp and "00000000000000000000000111111111";
|
| 266 |
|
|
when "11000" =>
|
| 267 |
|
|
output <= temp and "00000000000000000000000011111111";
|
| 268 |
|
|
when "11001" =>
|
| 269 |
|
|
output <= temp and "00000000000000000000000001111111";
|
| 270 |
|
|
when "11010" =>
|
| 271 |
|
|
output <= temp and "00000000000000000000000000111111";
|
| 272 |
|
|
when "11011" =>
|
| 273 |
|
|
output <= temp and "00000000000000000000000000011111";
|
| 274 |
|
|
when "11100" =>
|
| 275 |
|
|
output <= temp and "00000000000000000000000000001111";
|
| 276 |
|
|
when "11101" =>
|
| 277 |
|
|
output <= temp and "00000000000000000000000000000111";
|
| 278 |
|
|
when "11110" =>
|
| 279 |
|
|
output <= temp and "00000000000000000000000000000011";
|
| 280 |
|
|
when "11111" =>
|
| 281 |
|
|
output <= temp and "00000000000000000000000000000001";
|
| 282 |
|
|
when others =>
|
| 283 |
|
|
output <= temp;
|
| 284 |
|
|
end case; -- count
|
| 285 |
|
|
when BS_ASR => -- ASR
|
| 286 |
|
|
shift <= 32 - count;
|
| 287 |
|
|
cyOut <= input(conv_integer(count - 1));
|
| 288 |
|
|
case count is
|
| 289 |
|
|
when "00000" =>
|
| 290 |
|
|
output <= (input(31) & input(31) & input(31) & input(31) &
|
| 291 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 292 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 293 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 294 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 295 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 296 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 297 |
|
|
input(31) & input(31) & input(31) & input(31));
|
| 298 |
|
|
when "00001" =>
|
| 299 |
|
|
output <= (temp and "01111111111111111111111111111111") or
|
| 300 |
|
|
(input(31) & "0000000000000000000000000000000");
|
| 301 |
|
|
when "00010" =>
|
| 302 |
|
|
output <= (temp and "00111111111111111111111111111111") or
|
| 303 |
|
|
(input(31) & input(31) &
|
| 304 |
|
|
"000000000000000000000000000000");
|
| 305 |
|
|
when "00011" =>
|
| 306 |
|
|
output <= (temp and "00011111111111111111111111111111") or
|
| 307 |
|
|
(input(31) & input(31) & input(31) &
|
| 308 |
|
|
"00000000000000000000000000000");
|
| 309 |
|
|
when "00100" =>
|
| 310 |
|
|
output <= (temp and "00001111111111111111111111111111") or
|
| 311 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 312 |
|
|
"0000000000000000000000000000");
|
| 313 |
|
|
when "00101" =>
|
| 314 |
|
|
output <= (temp and "00000111111111111111111111111111") or
|
| 315 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 316 |
|
|
input(31) & "000000000000000000000000000");
|
| 317 |
|
|
when "00110" =>
|
| 318 |
|
|
output <= (temp and "00000011111111111111111111111111") or
|
| 319 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 320 |
|
|
input(31) & input(31) &
|
| 321 |
|
|
"00000000000000000000000000");
|
| 322 |
|
|
when "00111" =>
|
| 323 |
|
|
output <= (temp and "00000001111111111111111111111111") or
|
| 324 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 325 |
|
|
input(31) & input(31) & input(31) &
|
| 326 |
|
|
"0000000000000000000000000");
|
| 327 |
|
|
when "01000" =>
|
| 328 |
|
|
output <= (temp and "00000000111111111111111111111111") or
|
| 329 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 330 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 331 |
|
|
"000000000000000000000000");
|
| 332 |
|
|
when "01001" =>
|
| 333 |
|
|
output <= (temp and "00000000011111111111111111111111") or
|
| 334 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 335 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 336 |
|
|
input(31) & "00000000000000000000000");
|
| 337 |
|
|
when "01010" =>
|
| 338 |
|
|
output <= (temp and "00000000001111111111111111111111") or
|
| 339 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 340 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 341 |
|
|
input(31) & input(31) & "0000000000000000000000");
|
| 342 |
|
|
when "01011" =>
|
| 343 |
|
|
output <= (temp and "00000000000111111111111111111111") or
|
| 344 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 345 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 346 |
|
|
input(31) & input(31) & input(31) &
|
| 347 |
|
|
"000000000000000000000");
|
| 348 |
|
|
when "01100" =>
|
| 349 |
|
|
output <= (temp and "00000000000011111111111111111111") or
|
| 350 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 351 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 352 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 353 |
|
|
"00000000000000000000");
|
| 354 |
|
|
when "01101" =>
|
| 355 |
|
|
output <= (temp and "00000000000001111111111111111111") or
|
| 356 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 357 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 358 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 359 |
|
|
input(31) & "0000000000000000000");
|
| 360 |
|
|
when "01110" =>
|
| 361 |
|
|
output <= (temp and "00000000000000111111111111111111") or
|
| 362 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 363 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 364 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 365 |
|
|
input(31) & input(31) & "000000000000000000");
|
| 366 |
|
|
when "01111" =>
|
| 367 |
|
|
output <= (temp and "00000000000000011111111111111111") or
|
| 368 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 369 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 370 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 371 |
|
|
input(31) & input(31) & input(31) &
|
| 372 |
|
|
"00000000000000000");
|
| 373 |
|
|
when "10000" =>
|
| 374 |
|
|
output <= (temp and "00000000000000001111111111111111") or
|
| 375 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 376 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 377 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 378 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 379 |
|
|
"0000000000000000");
|
| 380 |
|
|
when "10001" =>
|
| 381 |
|
|
output <= (temp and "00000000000000000111111111111111") or
|
| 382 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 383 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 384 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 385 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 386 |
|
|
input(31) & "000000000000000");
|
| 387 |
|
|
when "10010" =>
|
| 388 |
|
|
output <= (temp and "00000000000000000011111111111111") or
|
| 389 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 390 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 391 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 392 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 393 |
|
|
input(31) & input(31) & "00000000000000");
|
| 394 |
|
|
when "10011" =>
|
| 395 |
|
|
output <= (temp and "00000000000000000001111111111111") or
|
| 396 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 397 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 398 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 399 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 400 |
|
|
input(31) & input(31) & input(31) & "0000000000000");
|
| 401 |
|
|
when "10100" =>
|
| 402 |
|
|
output <= (temp and "00000000000000000000111111111111") or
|
| 403 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 404 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 405 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 406 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 407 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 408 |
|
|
"000000000000");
|
| 409 |
|
|
when "10101" =>
|
| 410 |
|
|
output <= (temp and "00000000000000000000011111111111") or
|
| 411 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 412 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 413 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 414 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 415 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 416 |
|
|
input(31) & "00000000000");
|
| 417 |
|
|
when "10110" =>
|
| 418 |
|
|
output <= (temp and "00000000000000000000001111111111") or
|
| 419 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 420 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 421 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 422 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 423 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 424 |
|
|
input(31) & input(31) & "0000000000");
|
| 425 |
|
|
when "10111" =>
|
| 426 |
|
|
output <= (temp and "00000000000000000000000111111111") or
|
| 427 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 428 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 429 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 430 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 431 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 432 |
|
|
input(31) & input(31) & input(31) & "000000000");
|
| 433 |
|
|
when "11000" =>
|
| 434 |
|
|
output <= (temp and "00000000000000000000000011111111") or
|
| 435 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 436 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 437 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 438 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 439 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 440 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 441 |
|
|
"00000000");
|
| 442 |
|
|
when "11001" =>
|
| 443 |
|
|
output <= (temp and "00000000000000000000000001111111") or
|
| 444 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 445 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 446 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 447 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 448 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 449 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 450 |
|
|
input(31) & "0000000");
|
| 451 |
|
|
when "11010" =>
|
| 452 |
|
|
output <= (temp and "00000000000000000000000000111111") or
|
| 453 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 454 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 455 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 456 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 457 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 458 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 459 |
|
|
input(31) & input(31) & "000000");
|
| 460 |
|
|
when "11011" =>
|
| 461 |
|
|
output <= (temp and "00000000000000000000000000011111") or
|
| 462 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 463 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 464 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 465 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 466 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 467 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 468 |
|
|
input(31) & input(31) & input(31) & "00000");
|
| 469 |
|
|
when "11100" =>
|
| 470 |
|
|
output <= (temp and "00000000000000000000000000001111") or
|
| 471 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 472 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 473 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 474 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 475 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 476 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 477 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 478 |
|
|
"0000");
|
| 479 |
|
|
when "11101" =>
|
| 480 |
|
|
output <= (temp and "00000000000000000000000000000111") or
|
| 481 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 482 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 483 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 484 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 485 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 486 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 487 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 488 |
|
|
input(31) & "000");
|
| 489 |
|
|
when "11110" =>
|
| 490 |
|
|
output <= (temp and "00000000000000000000000000000011") or
|
| 491 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 492 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 493 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 494 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 495 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 496 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 497 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 498 |
|
|
input(31) & input(31) & "00");
|
| 499 |
|
|
when "11111" =>
|
| 500 |
|
|
output <= (temp and "00000000000000000000000000000001") or
|
| 501 |
|
|
(input(31) & input(31) & input(31) & input(31) &
|
| 502 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 503 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 504 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 505 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 506 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 507 |
|
|
input(31) & input(31) & input(31) & input(31) &
|
| 508 |
|
|
input(31) & input(31) & input(31) & "0");
|
| 509 |
|
|
when others =>
|
| 510 |
|
|
output <= temp;
|
| 511 |
|
|
end case; -- count
|
| 512 |
|
|
when others =>
|
| 513 |
|
|
shift <= count;
|
| 514 |
|
|
output <= temp;
|
| 515 |
|
|
end case; -- mode
|
| 516 |
|
|
end process;
|
| 517 |
|
|
|
| 518 |
|
|
-------------- 32bit barrel shifter
|
| 519 |
|
|
ENCODE(17 downto 8) <= (others => '0');
|
| 520 |
|
|
|
| 521 |
|
|
WORDA(17 downto 16) <= (others => '0');
|
| 522 |
|
|
WORDB(17 downto 16) <= (others => '0');
|
| 523 |
|
|
WORDC(17 downto 16) <= (others => '0');
|
| 524 |
|
|
WORDD(17 downto 16) <= (others => '0');
|
| 525 |
|
|
|
| 526 |
|
|
WORDA(15 downto 8) <= input ( 7 downto 0);
|
| 527 |
|
|
WORDB(15 downto 8) <= input (15 downto 8);
|
| 528 |
|
|
WORDC(15 downto 8) <= input (23 downto 16);
|
| 529 |
|
|
WORDD(15 downto 8) <= input (31 downto 24);
|
| 530 |
|
|
|
| 531 |
|
|
WORDA(7 downto 0) <= input (31 downto 24);
|
| 532 |
|
|
WORDB(7 downto 0) <= input ( 7 downto 0);
|
| 533 |
|
|
WORDC(7 downto 0) <= input (15 downto 8);
|
| 534 |
|
|
WORDD(7 downto 0) <= input (23 downto 16);
|
| 535 |
|
|
|
| 536 |
|
|
ONE_HOT:
|
| 537 |
|
|
with SHIFT(2 downto 0) select
|
| 538 |
|
|
encode(7 downto 0) <=
|
| 539 |
|
|
"00000001" when "000", --0
|
| 540 |
|
|
"00000010" when "001", --1
|
| 541 |
|
|
"00000100" when "010", --2
|
| 542 |
|
|
"00001000" when "011", --3
|
| 543 |
|
|
"00010000" when "100", --4
|
| 544 |
|
|
"00100000" when "101", --5
|
| 545 |
|
|
"01000000" when "110", --6
|
| 546 |
|
|
"10000000" when others; --7
|
| 547 |
|
|
|
| 548 |
|
|
MULTA: MULT18X18 port map (A => WORDA, B => ENCODE, P => OUTA);
|
| 549 |
|
|
MULTB: MULT18X18 port map (A => WORDB, B => ENCODE, P => OUTB);
|
| 550 |
|
|
MULTC: MULT18X18 port map (A => WORDC, B => ENCODE, P => OUTC);
|
| 551 |
|
|
MULTD: MULT18X18 port map (A => WORDD, B => ENCODE, P => OUTD);
|
| 552 |
|
|
|
| 553 |
|
|
MUXA:
|
| 554 |
|
|
process(SHIFT, OUTA, OUTB, OUTC, OUTD)
|
| 555 |
|
|
begin
|
| 556 |
|
|
case SHIFT(4 downto 3) is
|
| 557 |
|
|
when "00" => temp(7 downto 0) <= OUTA(15 downto 8);
|
| 558 |
|
|
when "01" => temp(7 downto 0) <= OUTD(15 downto 8);
|
| 559 |
|
|
when "10" => temp(7 downto 0) <= OUTC(15 downto 8);
|
| 560 |
|
|
when others => temp(7 downto 0) <= OUTB(15 downto 8);
|
| 561 |
|
|
end case;
|
| 562 |
|
|
end process;
|
| 563 |
|
|
|
| 564 |
|
|
MUXB:
|
| 565 |
|
|
process(SHIFT, OUTA, OUTB, OUTC, OUTD)
|
| 566 |
|
|
begin
|
| 567 |
|
|
case SHIFT(4 downto 3) is
|
| 568 |
|
|
when "00" => temp(15 downto 8) <= OUTB(15 downto 8);
|
| 569 |
|
|
when "01" => temp(15 downto 8) <= OUTA(15 downto 8);
|
| 570 |
|
|
when "10" => temp(15 downto 8) <= OUTD(15 downto 8);
|
| 571 |
|
|
when others => temp(15 downto 8) <= OUTC(15 downto 8);
|
| 572 |
|
|
end case;
|
| 573 |
|
|
end process;
|
| 574 |
|
|
|
| 575 |
|
|
MUXC:
|
| 576 |
|
|
process(SHIFT, OUTA, OUTB, OUTC, OUTD)
|
| 577 |
|
|
begin
|
| 578 |
|
|
case SHIFT(4 downto 3) is
|
| 579 |
|
|
when "00" => temp(23 downto 16) <= OUTC(15 downto 8);
|
| 580 |
|
|
when "01" => temp(23 downto 16) <= OUTB(15 downto 8);
|
| 581 |
|
|
when "10" => temp(23 downto 16) <= OUTA(15 downto 8);
|
| 582 |
|
|
when others => temp(23 downto 16) <= OUTD(15 downto 8);
|
| 583 |
|
|
end case;
|
| 584 |
|
|
end process;
|
| 585 |
|
|
|
| 586 |
|
|
MUXD:
|
| 587 |
|
|
process(SHIFT, OUTA, OUTB, OUTC, OUTD)
|
| 588 |
|
|
begin
|
| 589 |
|
|
case SHIFT(4 downto 3) is
|
| 590 |
|
|
when "00" => temp(31 downto 24) <= OUTD(15 downto 8);
|
| 591 |
|
|
when "01" => temp(31 downto 24) <= OUTC(15 downto 8);
|
| 592 |
|
|
when "10" => temp(31 downto 24) <= OUTB(15 downto 8);
|
| 593 |
|
|
when others => temp(31 downto 24) <= OUTA(15 downto 8);
|
| 594 |
|
|
end case;
|
| 595 |
|
|
end process;
|
| 596 |
|
|
|
| 597 |
|
|
end behavioral;
|
| 598 |
|
|
|
| 599 |
|
|
----------------------------------------------------------------------------------
|
| 600 |
|
|
library IEEE;
|
| 601 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
| 602 |
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
| 603 |
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
| 604 |
|
|
|
| 605 |
|
|
---- Uncomment the following library declaration if instantiating
|
| 606 |
|
|
---- any Xilinx primitives in this code.
|
| 607 |
|
|
library UNISIM;
|
| 608 |
|
|
use UNISIM.VComponents.all;
|
| 609 |
|
|
|
| 610 |
|
|
entity Multiplier is
|
| 611 |
|
|
Port ( a : in STD_LOGIC_VECTOR (31 downto 0);
|
| 612 |
|
|
b : in STD_LOGIC_VECTOR (31 downto 0);
|
| 613 |
|
|
p : out STD_LOGIC_VECTOR (63 downto 0));
|
| 614 |
|
|
end Multiplier;
|
| 615 |
|
|
|
| 616 |
|
|
architecture Behavioral of Multiplier is
|
| 617 |
|
|
|
| 618 |
|
|
signal WORDAL : std_logic_vector(17 downto 0);
|
| 619 |
|
|
signal WORDAH : std_logic_vector(17 downto 0);
|
| 620 |
|
|
signal WORDBL : std_logic_vector(17 downto 0);
|
| 621 |
|
|
signal WORDBH : std_logic_vector(17 downto 0);
|
| 622 |
|
|
signal PROD0 : std_logic_vector(35 downto 0);
|
| 623 |
|
|
signal PROD1 : std_logic_vector(35 downto 0);
|
| 624 |
|
|
signal PROD2 : std_logic_vector(35 downto 0);
|
| 625 |
|
|
signal PROD3 : std_logic_vector(35 downto 0);
|
| 626 |
|
|
|
| 627 |
|
|
begin
|
| 628 |
|
|
|
| 629 |
|
|
-- A * B
|
| 630 |
|
|
-- B(15.. 0) * A(15..0)
|
| 631 |
|
|
-- B(15.. 0) * A(31..16)
|
| 632 |
|
|
-- B(31..16) * A(15.. 0)
|
| 633 |
|
|
-- B(31..16) * A(31..16)
|
| 634 |
|
|
WORDAL <= "00" & a(15 downto 0);
|
| 635 |
|
|
WORDAH <= "00" & a(31 downto 16);
|
| 636 |
|
|
WORDBL <= "00" & b(15 downto 0);
|
| 637 |
|
|
WORDBH <= "00" & b(31 downto 16);
|
| 638 |
|
|
|
| 639 |
|
|
MULTA: MULT18X18 port map (A => WORDAL, B => WORDBL, P => PROD0);
|
| 640 |
|
|
MULTB: MULT18X18 port map (A => WORDAH, B => WORDBL, P => PROD1);
|
| 641 |
|
|
MULTC: MULT18X18 port map (A => WORDAL, B => WORDBH, P => PROD2);
|
| 642 |
|
|
MULTD: MULT18X18 port map (A => WORDAH, B => WORDBH, P => PROD3);
|
| 643 |
|
|
|
| 644 |
|
|
p <= (x"00000000" & PROD0(31 downto 0)) +
|
| 645 |
|
|
(x"0000" & PROD1(31 downto 0) & x"0000") +
|
| 646 |
|
|
(x"0000" & PROD2(31 downto 0) & x"0000") +
|
| 647 |
|
|
(PROD3(31 downto 0) & x"00000000");
|
| 648 |
|
|
|
| 649 |
|
|
end Behavioral;
|
| 650 |
|
|
|
| 651 |
|
|
--################################################################
|
| 652 |
|
|
--###### AT HERE THE Cortex CPU ##################################
|
| 653 |
|
|
--################################################################
|
| 654 |
|
|
-- #MAIN#
|
| 655 |
|
|
LIBRARY ieee;
|
| 656 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
| 657 |
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
| 658 |
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
| 659 |
|
|
|
| 660 |
|
|
use work.CortexIinclude.ALL;
|
| 661 |
|
|
|
| 662 |
|
|
Library UNISIM;
|
| 663 |
|
|
use UNISIM.vcomponents.all;
|
| 664 |
|
|
|
| 665 |
|
|
ENTITY CortexI IS
|
| 666 |
|
|
PORT(
|
| 667 |
|
|
clk : in std_logic;
|
| 668 |
|
|
rst : in std_logic;
|
| 669 |
|
|
irq : in std_logic;
|
| 670 |
|
|
addr : out std_logic_vector(31 downto 0);
|
| 671 |
|
|
wrl : out std_logic;
|
| 672 |
|
|
wrh : out std_logic;
|
| 673 |
|
|
datain : in std_logic_vector(15 downto 0);
|
| 674 |
|
|
dataout : out std_logic_vector(15 downto 0)
|
| 675 |
|
|
);
|
| 676 |
|
|
END CortexI;
|
| 677 |
|
|
|
| 678 |
|
|
ARCHITECTURE behavior OF CortexI IS
|
| 679 |
|
|
|
| 680 |
|
|
constant STATE_FETCH : std_logic_vector(6 downto 0) := "0000000";
|
| 681 |
|
|
constant STATE_READ1 : std_logic_vector(6 downto 0) := "0000001";
|
| 682 |
|
|
constant STATE_READ2 : std_logic_vector(6 downto 0) := "0000010";
|
| 683 |
|
|
constant STATE_WRITE1 : std_logic_vector(6 downto 0) := "0000011";
|
| 684 |
|
|
constant STATE_WRITE2 : std_logic_vector(6 downto 0) := "0000100";
|
| 685 |
|
|
constant STATE_RD0L : std_logic_vector(6 downto 0) := "0000101";
|
| 686 |
|
|
constant STATE_RD0H : std_logic_vector(6 downto 0) := "0000110";
|
| 687 |
|
|
constant STATE_RD1L : std_logic_vector(6 downto 0) := "0000111";
|
| 688 |
|
|
constant STATE_RD1H : std_logic_vector(6 downto 0) := "0001000";
|
| 689 |
|
|
constant STATE_RD2L : std_logic_vector(6 downto 0) := "0001001";
|
| 690 |
|
|
constant STATE_RD2H : std_logic_vector(6 downto 0) := "0001010";
|
| 691 |
|
|
constant STATE_RD3L : std_logic_vector(6 downto 0) := "0001011";
|
| 692 |
|
|
constant STATE_RD3H : std_logic_vector(6 downto 0) := "0001100";
|
| 693 |
|
|
constant STATE_RD4L : std_logic_vector(6 downto 0) := "0001101";
|
| 694 |
|
|
constant STATE_RD4H : std_logic_vector(6 downto 0) := "0001110";
|
| 695 |
|
|
constant STATE_RD5L : std_logic_vector(6 downto 0) := "0001111";
|
| 696 |
|
|
constant STATE_RD5H : std_logic_vector(6 downto 0) := "0010000";
|
| 697 |
|
|
constant STATE_RD6L : std_logic_vector(6 downto 0) := "0010001";
|
| 698 |
|
|
constant STATE_RD6H : std_logic_vector(6 downto 0) := "0010010";
|
| 699 |
|
|
constant STATE_RD7L : std_logic_vector(6 downto 0) := "0010011";
|
| 700 |
|
|
constant STATE_RD7H : std_logic_vector(6 downto 0) := "0010100";
|
| 701 |
|
|
constant STATE_RDPL : std_logic_vector(6 downto 0) := "0010101";
|
| 702 |
|
|
constant STATE_RDPH : std_logic_vector(6 downto 0) := "0010110";
|
| 703 |
|
|
constant STATE_WR0L : std_logic_vector(6 downto 0) := "0010111";
|
| 704 |
|
|
constant STATE_WR0H : std_logic_vector(6 downto 0) := "0011000";
|
| 705 |
|
|
constant STATE_WR1L : std_logic_vector(6 downto 0) := "0011001";
|
| 706 |
|
|
constant STATE_WR1H : std_logic_vector(6 downto 0) := "0011010";
|
| 707 |
|
|
constant STATE_WR2L : std_logic_vector(6 downto 0) := "0011011";
|
| 708 |
|
|
constant STATE_WR2H : std_logic_vector(6 downto 0) := "0011100";
|
| 709 |
|
|
constant STATE_WR3L : std_logic_vector(6 downto 0) := "0011101";
|
| 710 |
|
|
constant STATE_WR3H : std_logic_vector(6 downto 0) := "0011110";
|
| 711 |
|
|
constant STATE_WR4L : std_logic_vector(6 downto 0) := "0011111";
|
| 712 |
|
|
constant STATE_WR4H : std_logic_vector(6 downto 0) := "0100000";
|
| 713 |
|
|
constant STATE_WR5L : std_logic_vector(6 downto 0) := "0100001";
|
| 714 |
|
|
constant STATE_WR5H : std_logic_vector(6 downto 0) := "0100010";
|
| 715 |
|
|
constant STATE_WR6L : std_logic_vector(6 downto 0) := "0100011";
|
| 716 |
|
|
constant STATE_WR6H : std_logic_vector(6 downto 0) := "0100100";
|
| 717 |
|
|
constant STATE_WR7L : std_logic_vector(6 downto 0) := "0100101";
|
| 718 |
|
|
constant STATE_WR7H : std_logic_vector(6 downto 0) := "0100110";
|
| 719 |
|
|
constant STATE_WRPL : std_logic_vector(6 downto 0) := "0100111";
|
| 720 |
|
|
constant STATE_WRPH : std_logic_vector(6 downto 0) := "0101000";
|
| 721 |
|
|
constant STATE_RESET0 : std_logic_vector(6 downto 0) := "0101001";
|
| 722 |
|
|
constant STATE_RESET1 : std_logic_vector(6 downto 0) := "0101010";
|
| 723 |
|
|
constant STATE_RESET2 : std_logic_vector(6 downto 0) := "0101011";
|
| 724 |
|
|
constant STATE_RESET3 : std_logic_vector(6 downto 0) := "0101100";
|
| 725 |
|
|
constant STATE_IRQ : std_logic_vector(6 downto 0) := "0101101";
|
| 726 |
|
|
constant STATE_IRQ1 : std_logic_vector(6 downto 0) := "0101110";
|
| 727 |
|
|
constant STATE_IRQ2 : std_logic_vector(6 downto 0) := "0101111";
|
| 728 |
|
|
constant STATE_IRQ3 : std_logic_vector(6 downto 0) := "0110000";
|
| 729 |
|
|
constant STATE_IRQ4 : std_logic_vector(6 downto 0) := "0110001";
|
| 730 |
|
|
constant STATE_IRQ5 : std_logic_vector(6 downto 0) := "0110010";
|
| 731 |
|
|
constant STATE_IRQ6 : std_logic_vector(6 downto 0) := "0110011";
|
| 732 |
|
|
constant STATE_IRQ7 : std_logic_vector(6 downto 0) := "0110100";
|
| 733 |
|
|
constant STATE_IRQ8 : std_logic_vector(6 downto 0) := "0110101";
|
| 734 |
|
|
constant STATE_IRQ9 : std_logic_vector(6 downto 0) := "0110110";
|
| 735 |
|
|
constant STATE_IRQ10 : std_logic_vector(6 downto 0) := "0110111";
|
| 736 |
|
|
constant STATE_IRQ11 : std_logic_vector(6 downto 0) := "0111000";
|
| 737 |
|
|
constant STATE_IRQ12 : std_logic_vector(6 downto 0) := "0111001";
|
| 738 |
|
|
constant STATE_IRQ13 : std_logic_vector(6 downto 0) := "0111010";
|
| 739 |
|
|
constant STATE_IRQ14 : std_logic_vector(6 downto 0) := "0111011";
|
| 740 |
|
|
constant STATE_IRQ15 : std_logic_vector(6 downto 0) := "0111100";
|
| 741 |
|
|
constant STATE_IRQ16 : std_logic_vector(6 downto 0) := "0111101";
|
| 742 |
|
|
constant STATE_IRQ17 : std_logic_vector(6 downto 0) := "0111110";
|
| 743 |
|
|
constant STATE_RET : std_logic_vector(6 downto 0) := "0111111";
|
| 744 |
|
|
constant STATE_RET1 : std_logic_vector(6 downto 0) := "1000000";
|
| 745 |
|
|
constant STATE_RET2 : std_logic_vector(6 downto 0) := "1000001";
|
| 746 |
|
|
constant STATE_RET3 : std_logic_vector(6 downto 0) := "1000010";
|
| 747 |
|
|
constant STATE_RET4 : std_logic_vector(6 downto 0) := "1000011";
|
| 748 |
|
|
constant STATE_RET5 : std_logic_vector(6 downto 0) := "1000100";
|
| 749 |
|
|
constant STATE_RET6 : std_logic_vector(6 downto 0) := "1000101";
|
| 750 |
|
|
constant STATE_RET7 : std_logic_vector(6 downto 0) := "1000110";
|
| 751 |
|
|
constant STATE_RET8 : std_logic_vector(6 downto 0) := "1000111";
|
| 752 |
|
|
constant STATE_RET9 : std_logic_vector(6 downto 0) := "1001000";
|
| 753 |
|
|
constant STATE_RET10 : std_logic_vector(6 downto 0) := "1001001";
|
| 754 |
|
|
constant STATE_RET11 : std_logic_vector(6 downto 0) := "1001010";
|
| 755 |
|
|
constant STATE_RET12 : std_logic_vector(6 downto 0) := "1001011";
|
| 756 |
|
|
constant STATE_RET13 : std_logic_vector(6 downto 0) := "1001100";
|
| 757 |
|
|
constant STATE_RET14 : std_logic_vector(6 downto 0) := "1001101";
|
| 758 |
|
|
constant STATE_RET15 : std_logic_vector(6 downto 0) := "1001110";
|
| 759 |
|
|
constant STATE_RET16 : std_logic_vector(6 downto 0) := "1001111";
|
| 760 |
|
|
constant STATE_RET17 : std_logic_vector(6 downto 0) := "1010000";
|
| 761 |
|
|
|
| 762 |
|
|
constant CODE_LSL1 : std_logic_vector(6 downto 0) := "0000000";
|
| 763 |
|
|
constant CODE_LSR1 : std_logic_vector(6 downto 0) := "0000001";
|
| 764 |
|
|
constant CODE_ASR1 : std_logic_vector(6 downto 0) := "0000010";
|
| 765 |
|
|
constant CODE_ADD1 : std_logic_vector(6 downto 0) := "0000011";
|
| 766 |
|
|
constant CODE_SUB1 : std_logic_vector(6 downto 0) := "0000100";
|
| 767 |
|
|
constant CODE_ADD2 : std_logic_vector(6 downto 0) := "0000110";
|
| 768 |
|
|
constant CODE_SUB2 : std_logic_vector(6 downto 0) := "0000111";
|
| 769 |
|
|
constant CODE_MOV1 : std_logic_vector(6 downto 0) := "0001000";
|
| 770 |
|
|
constant CODE_CMP1 : std_logic_vector(6 downto 0) := "0001001";
|
| 771 |
|
|
constant CODE_ADD3 : std_logic_vector(6 downto 0) := "0001010";
|
| 772 |
|
|
constant CODE_SUB3 : std_logic_vector(6 downto 0) := "0001011";
|
| 773 |
|
|
constant CODE_AND1 : std_logic_vector(6 downto 0) := "0001100";
|
| 774 |
|
|
constant CODE_EOR1 : std_logic_vector(6 downto 0) := "0001101";
|
| 775 |
|
|
constant CODE_LSL2 : std_logic_vector(6 downto 0) := "0001110";
|
| 776 |
|
|
constant CODE_LSR2 : std_logic_vector(6 downto 0) := "0001111";
|
| 777 |
|
|
constant CODE_ASR2 : std_logic_vector(6 downto 0) := "0010000";
|
| 778 |
|
|
constant CODE_ADC1 : std_logic_vector(6 downto 0) := "0010001";
|
| 779 |
|
|
constant CODE_SBC1 : std_logic_vector(6 downto 0) := "0010010";
|
| 780 |
|
|
constant CODE_ROR1 : std_logic_vector(6 downto 0) := "0010011";
|
| 781 |
|
|
constant CODE_TST1 : std_logic_vector(6 downto 0) := "0010100";
|
| 782 |
|
|
constant CODE_NEG1 : std_logic_vector(6 downto 0) := "0010101";
|
| 783 |
|
|
constant CODE_CMP2 : std_logic_vector(6 downto 0) := "0010110";
|
| 784 |
|
|
constant CODE_CMN1 : std_logic_vector(6 downto 0) := "0010111";
|
| 785 |
|
|
constant CODE_ORR1 : std_logic_vector(6 downto 0) := "0011000";
|
| 786 |
|
|
constant CODE_MUL1 : std_logic_vector(6 downto 0) := "0011001";
|
| 787 |
|
|
constant CODE_BIC1 : std_logic_vector(6 downto 0) := "0011010";
|
| 788 |
|
|
constant CODE_MVN1 : std_logic_vector(6 downto 0) := "0011011";
|
| 789 |
|
|
constant CODE_ADD4 : std_logic_vector(6 downto 0) := "0011100";
|
| 790 |
|
|
constant CODE_CMP3 : std_logic_vector(6 downto 0) := "0011101";
|
| 791 |
|
|
constant CODE_CPY1 : std_logic_vector(6 downto 0) := "0011110";
|
| 792 |
|
|
constant CODE_BX1 : std_logic_vector(6 downto 0) := "0011111";
|
| 793 |
|
|
constant CODE_LDR1 : std_logic_vector(6 downto 0) := "0100000";
|
| 794 |
|
|
constant CODE_STR1 : std_logic_vector(6 downto 0) := "0100001";
|
| 795 |
|
|
constant CODE_STRH1 : std_logic_vector(6 downto 0) := "0100010";
|
| 796 |
|
|
constant CODE_STRB1 : std_logic_vector(6 downto 0) := "0100011";
|
| 797 |
|
|
constant CODE_LDRSB1 : std_logic_vector(6 downto 0) := "0100100";
|
| 798 |
|
|
constant CODE_LDR2 : std_logic_vector(6 downto 0) := "0100101";
|
| 799 |
|
|
constant CODE_LDRH1 : std_logic_vector(6 downto 0) := "0100110";
|
| 800 |
|
|
constant CODE_LDRB1 : std_logic_vector(6 downto 0) := "0100111";
|
| 801 |
|
|
constant CODE_LDRSH1 : std_logic_vector(6 downto 0) := "0101000";
|
| 802 |
|
|
constant CODE_STR2 : std_logic_vector(6 downto 0) := "0101001";
|
| 803 |
|
|
constant CODE_LDR3 : std_logic_vector(6 downto 0) := "0101010";
|
| 804 |
|
|
constant CODE_STRB2 : std_logic_vector(6 downto 0) := "0101011";
|
| 805 |
|
|
constant CODE_LDRB2 : std_logic_vector(6 downto 0) := "0101100";
|
| 806 |
|
|
constant CODE_STRH2 : std_logic_vector(6 downto 0) := "0101101";
|
| 807 |
|
|
constant CODE_LDRH2 : std_logic_vector(6 downto 0) := "0101110";
|
| 808 |
|
|
constant CODE_STR3 : std_logic_vector(6 downto 0) := "0101111";
|
| 809 |
|
|
constant CODE_LDR4 : std_logic_vector(6 downto 0) := "0110000";
|
| 810 |
|
|
constant CODE_ADD5 : std_logic_vector(6 downto 0) := "0110001";
|
| 811 |
|
|
constant CODE_ADD6 : std_logic_vector(6 downto 0) := "0110010";
|
| 812 |
|
|
constant CODE_ADD7 : std_logic_vector(6 downto 0) := "0110011";
|
| 813 |
|
|
constant CODE_SUB4 : std_logic_vector(6 downto 0) := "0110100";
|
| 814 |
|
|
constant CODE_SXTH1 : std_logic_vector(6 downto 0) := "0110101";
|
| 815 |
|
|
constant CODE_SXTB1 : std_logic_vector(6 downto 0) := "0110110";
|
| 816 |
|
|
constant CODE_UXTH1 : std_logic_vector(6 downto 0) := "0110111";
|
| 817 |
|
|
constant CODE_UXTB1 : std_logic_vector(6 downto 0) := "0111000";
|
| 818 |
|
|
constant CODE_PUSH1 : std_logic_vector(6 downto 0) := "0111001";
|
| 819 |
|
|
constant CODE_POP1 : std_logic_vector(6 downto 0) := "0111010";
|
| 820 |
|
|
constant CODE_STMIA1 : std_logic_vector(6 downto 0) := "0111011";
|
| 821 |
|
|
constant CODE_LDMIA1 : std_logic_vector(6 downto 0) := "0111100";
|
| 822 |
|
|
constant CODE_BCC1 : std_logic_vector(6 downto 0) := "0111101";
|
| 823 |
|
|
constant CODE_SWI1 : std_logic_vector(6 downto 0) := "0111110";
|
| 824 |
|
|
constant CODE_B1 : std_logic_vector(6 downto 0) := "0111111";
|
| 825 |
|
|
constant CODE_BLX1 : std_logic_vector(6 downto 0) := "1000000";
|
| 826 |
|
|
constant CODE_BLX2 : std_logic_vector(6 downto 0) := "1000001";
|
| 827 |
|
|
constant CODE_BL1 : std_logic_vector(6 downto 0) := "1000010";
|
| 828 |
|
|
constant CODE_NOP : std_logic_vector(6 downto 0) := "1000011";
|
| 829 |
|
|
constant CODE_XXX : std_logic_vector(6 downto 0) := "1111111";
|
| 830 |
|
|
|
| 831 |
|
|
constant N_FLAG : integer := 31;
|
| 832 |
|
|
constant Z_FLAG : integer := 30;
|
| 833 |
|
|
constant C_FLAG : integer := 29;
|
| 834 |
|
|
constant V_FLAG : integer := 28;
|
| 835 |
|
|
|
| 836 |
|
|
constant WRITE_B_LOW : std_logic_vector(3 downto 0) := "0000";
|
| 837 |
|
|
constant WRITE_B_HIGH : std_logic_vector(3 downto 0) := "0001";
|
| 838 |
|
|
constant WRITE_H_BOTH : std_logic_vector(3 downto 0) := "0010";
|
| 839 |
|
|
constant WRITE_H_LOW : std_logic_vector(3 downto 0) := "0011";
|
| 840 |
|
|
constant WRITE_H_HIGH : std_logic_vector(3 downto 0) := "0100";
|
| 841 |
|
|
constant WRITE_W_LOW : std_logic_vector(3 downto 0) := "0101";
|
| 842 |
|
|
constant WRITE_W_HIGH : std_logic_vector(3 downto 0) := "0110";
|
| 843 |
|
|
constant WRITE_W_LOWB : std_logic_vector(3 downto 0) := "0111";
|
| 844 |
|
|
constant WRITE_W_MID : std_logic_vector(3 downto 0) := "1000";
|
| 845 |
|
|
constant WRITE_W_HIGHB : std_logic_vector(3 downto 0) := "1001";
|
| 846 |
|
|
|
| 847 |
|
|
constant ADDR_PC : std_logic_vector(1 downto 0) := "00";
|
| 848 |
|
|
constant ADDR_SP : std_logic_vector(1 downto 0) := "01";
|
| 849 |
|
|
constant ADDR_RS : std_logic_vector(1 downto 0) := "10";
|
| 850 |
|
|
constant ADDR_RT : std_logic_vector(1 downto 0) := "11";
|
| 851 |
|
|
|
| 852 |
|
|
|
| 853 |
|
|
type typeRegisters is array (0 to 15) of std_logic_vector(31 downto 0);
|
| 854 |
|
|
|
| 855 |
|
|
signal theRegisters : typeRegisters;
|
| 856 |
|
|
signal cpsrRegister : std_logic_Vector(31 downto 0);
|
| 857 |
|
|
signal cpuState : std_logic_vector( 6 downto 0);
|
| 858 |
|
|
signal opcode : std_logic_vector(15 downto 0);
|
| 859 |
|
|
signal addrMux : std_logic_vector( 1 downto 0);
|
| 860 |
|
|
signal address : std_logic_vector(31 downto 0);
|
| 861 |
|
|
signal irq_d : std_logic;
|
| 862 |
|
|
signal irqRequest : std_logic;
|
| 863 |
|
|
signal writeL : std_logic;
|
| 864 |
|
|
signal writeH : std_logic;
|
| 865 |
|
|
signal shiftResult : std_logic_vector(31 downto 0);
|
| 866 |
|
|
signal cyShiftOut : std_logic;
|
| 867 |
|
|
signal shiftMode : std_logic_vector( 2 downto 0);
|
| 868 |
|
|
signal shiftCount : std_logic_vector( 4 downto 0);
|
| 869 |
|
|
signal shiftIn : std_logic_vector(31 downto 0);
|
| 870 |
|
|
signal LDMread : std_logic_vector( 7 downto 0);
|
| 871 |
|
|
|
| 872 |
|
|
signal unitControl : std_logic_vector( 6 downto 0);
|
| 873 |
|
|
signal unitControl2 : std_logic_vector( 6 downto 0);
|
| 874 |
|
|
|
| 875 |
|
|
signal factor1 : std_logic_vector(31 downto 0);
|
| 876 |
|
|
signal factor2 : std_logic_vector(31 downto 0);
|
| 877 |
|
|
signal product : std_logic_vector(63 downto 0);
|
| 878 |
|
|
|
| 879 |
|
|
signal branch : std_logic;
|
| 880 |
|
|
|
| 881 |
|
|
signal datain20 : integer range 0 to 15;
|
| 882 |
|
|
signal datain53 : integer range 0 to 15;
|
| 883 |
|
|
signal datain86 : integer range 0 to 15;
|
| 884 |
|
|
signal datain108 : integer range 0 to 15;
|
| 885 |
|
|
|
| 886 |
|
|
signal opcode20 : integer range 0 to 15;
|
| 887 |
|
|
signal opcode53 : integer range 0 to 15;
|
| 888 |
|
|
signal opcode86 : integer range 0 to 15;
|
| 889 |
|
|
signal opcode108 : integer range 0 to 15;
|
| 890 |
|
|
|
| 891 |
|
|
component bshifter Port (
|
| 892 |
|
|
din : in std_logic_vector(31 downto 0);
|
| 893 |
|
|
size : in std_logic_vector( 1 downto 0);
|
| 894 |
|
|
mode : in std_logic_vector( 2 downto 0);
|
| 895 |
|
|
count : in std_logic_vector( 4 downto 0);
|
| 896 |
|
|
cyOut : out std_logic;
|
| 897 |
|
|
dout : out std_logic_vector(31 downto 0)
|
| 898 |
|
|
);
|
| 899 |
|
|
end component;
|
| 900 |
|
|
|
| 901 |
|
|
component Multiplier -- 32 x 32 = 64 bit unsigned product multiplier
|
| 902 |
|
|
port(a : in std_logic_vector(31 downto 0); -- multiplicand
|
| 903 |
|
|
b : in std_logic_vector(31 downto 0); -- multiplier
|
| 904 |
|
|
p : out std_logic_vector(63 downto 0)); -- product
|
| 905 |
|
|
end component;
|
| 906 |
|
|
|
| 907 |
|
|
begin
|
| 908 |
|
|
|
| 909 |
|
|
datain20 <= conv_integer("0" & datain( 2 downto 0));
|
| 910 |
|
|
datain53 <= conv_integer("0" & datain( 5 downto 3));
|
| 911 |
|
|
datain86 <= conv_integer("0" & datain( 8 downto 6));
|
| 912 |
|
|
datain108 <= conv_integer("0" & datain(10 downto 8));
|
| 913 |
|
|
opcode20 <= conv_integer("0" & opcode( 2 downto 0));
|
| 914 |
|
|
opcode53 <= conv_integer("0" & opcode( 5 downto 3));
|
| 915 |
|
|
opcode86 <= conv_integer("0" & opcode( 8 downto 6));
|
| 916 |
|
|
opcode108 <= conv_integer("0" & opcode(10 downto 8));
|
| 917 |
|
|
|
| 918 |
|
|
--#################################################################
|
| 919 |
|
|
-- barrel shifter
|
| 920 |
|
|
shiftMode <= BS_LSL when (unitControl = CODE_LSL1) or (unitControl = CODE_LSL2) else
|
| 921 |
|
|
BS_LSR when (unitControl = CODE_LSR1) or (unitControl = CODE_LSR2) else
|
| 922 |
|
|
BS_ASR when (unitControl = CODE_ASR1) or (unitControl = CODE_ASR2) else
|
| 923 |
|
|
BS_ROR;
|
| 924 |
|
|
shiftCount <= datain(10 downto 6)
|
| 925 |
|
|
when (unitControl = CODE_LSL1) or (unitControl = CODE_LSR1) or (unitControl = CODE_ASR1) else
|
| 926 |
|
|
theRegisters(datain53)(4 downto 0);
|
| 927 |
|
|
shiftIn <= theRegisters(datain53)
|
| 928 |
|
|
when (unitControl = CODE_LSL1) or (unitControl = CODE_LSR1) or (unitControl = CODE_ASR1) else
|
| 929 |
|
|
theRegisters(datain20);
|
| 930 |
|
|
barrelShifter : bshifter Port map(
|
| 931 |
|
|
din => shiftIn, --: in std_logic_vector(31 downto 0);
|
| 932 |
|
|
size => SIZE_32BIT, --: in std_logic_vector( 1 downto 0);
|
| 933 |
|
|
mode => shiftMode, --: in std_logic_vector( 2 downto 0);
|
| 934 |
|
|
count => shiftCount, --: in std_logic_vector( 4 downto 0);
|
| 935 |
|
|
cyOut => cyShiftOut, --: out std_logic;
|
| 936 |
|
|
dout => shiftResult --: out std_logic_vector(31 downto 0)
|
| 937 |
|
|
);
|
| 938 |
|
|
|
| 939 |
|
|
--#################################################################
|
| 940 |
|
|
-- multiplier
|
| 941 |
|
|
multip : Multiplier Port map(
|
| 942 |
|
|
a => factor1,
|
| 943 |
|
|
b => factor2,
|
| 944 |
|
|
p => product
|
| 945 |
|
|
);
|
| 946 |
|
|
factor1 <= theRegisters(datain20);
|
| 947 |
|
|
factor2 <= theRegisters(datain53);
|
| 948 |
|
|
|
| 949 |
|
|
--#################################################################
|
| 950 |
|
|
-- decodes instruction bits to control bits for other ARMT units
|
| 951 |
|
|
process(datain)
|
| 952 |
|
|
begin
|
| 953 |
|
|
case datain(15 downto 11) is
|
| 954 |
|
|
when "00000" => unitControl <= CODE_LSL1;
|
| 955 |
|
|
when "00001" => unitControl <= CODE_LSR1;
|
| 956 |
|
|
when "00010" => unitControl <= CODE_ASR1;
|
| 957 |
|
|
when "00011" =>
|
| 958 |
|
|
case datain(10 downto 9) is
|
| 959 |
|
|
when "00" => unitControl <= CODE_ADD1;
|
| 960 |
|
|
when "01" => unitControl <= CODE_SUB1;
|
| 961 |
|
|
when "10" => unitControl <= CODE_ADD2;
|
| 962 |
|
|
when "11" => unitControl <= CODE_SUB2;
|
| 963 |
|
|
when others => unitControl <= CODE_XXX;
|
| 964 |
|
|
end case;
|
| 965 |
|
|
when "00100" => unitControl <= CODE_MOV1;
|
| 966 |
|
|
when "00101" => unitControl <= CODE_CMP1;
|
| 967 |
|
|
when "00110" => unitControl <= CODE_ADD3;
|
| 968 |
|
|
when "00111" => unitControl <= CODE_SUB3;
|
| 969 |
|
|
when "01000" =>
|
| 970 |
|
|
if datain(10) = '0' then
|
| 971 |
|
|
case datain(9 downto 6) is
|
| 972 |
|
|
when "0000" => unitControl <= CODE_AND1;
|
| 973 |
|
|
when "0001" => unitControl <= CODE_EOR1;
|
| 974 |
|
|
when "0010" => unitControl <= CODE_LSL2;
|
| 975 |
|
|
when "0011" => unitControl <= CODE_LSR2;
|
| 976 |
|
|
when "0100" => unitControl <= CODE_ASR2;
|
| 977 |
|
|
when "0101" => unitControl <= CODE_ADC1;
|
| 978 |
|
|
when "0110" => unitControl <= CODE_SBC1;
|
| 979 |
|
|
when "0111" => unitControl <= CODE_ROR1;
|
| 980 |
|
|
when "1000" => unitControl <= CODE_TST1;
|
| 981 |
|
|
when "1001" => unitControl <= CODE_NEG1;
|
| 982 |
|
|
when "1010" => unitControl <= CODE_CMP2;
|
| 983 |
|
|
when "1011" => unitControl <= CODE_CMN1;
|
| 984 |
|
|
when "1100" => unitControl <= CODE_ORR1;
|
| 985 |
|
|
when "1101" => unitControl <= CODE_MUL1;
|
| 986 |
|
|
when "1110" => unitControl <= CODE_BIC1;
|
| 987 |
|
|
when "1111" => unitControl <= CODE_MVN1;
|
| 988 |
|
|
when others => unitControl <= CODE_XXX;
|
| 989 |
|
|
end case;
|
| 990 |
|
|
else
|
| 991 |
|
|
case datain(9 downto 8) is
|
| 992 |
|
|
when "00" => unitControl <= CODE_ADD4;
|
| 993 |
|
|
when "01" => unitControl <= CODE_CMP3;
|
| 994 |
|
|
when "10" => unitControl <= CODE_CPY1; -- MOV
|
| 995 |
|
|
when "11" => unitControl <= CODE_BX1;
|
| 996 |
|
|
when others => unitControl <= CODE_XXX;
|
| 997 |
|
|
end case;
|
| 998 |
|
|
end if;
|
| 999 |
|
|
when "01001" => unitControl <= CODE_LDR1;
|
| 1000 |
|
|
when "01010" =>
|
| 1001 |
|
|
case datain(10 downto 9) is
|
| 1002 |
|
|
when "00" => unitControl <= CODE_STR1;
|
| 1003 |
|
|
when "01" => unitControl <= CODE_STRH1;
|
| 1004 |
|
|
when "10" => unitControl <= CODE_STRB1;
|
| 1005 |
|
|
when "11" => unitControl <= CODE_LDRSB1;
|
| 1006 |
|
|
when others => unitControl <= CODE_XXX;
|
| 1007 |
|
|
end case;
|
| 1008 |
|
|
when "01011" =>
|
| 1009 |
|
|
case datain(10 downto 9) is
|
| 1010 |
|
|
when "00" => unitControl <= CODE_LDR2;
|
| 1011 |
|
|
when "01" => unitControl <= CODE_LDRH1;
|
| 1012 |
|
|
when "10" => unitControl <= CODE_LDRB1;
|
| 1013 |
|
|
when "11" => unitControl <= CODE_LDRSH1;
|
| 1014 |
|
|
when others => unitControl <= CODE_XXX;
|
| 1015 |
|
|
end case;
|
| 1016 |
|
|
when "01100" => unitControl <= CODE_STR2;
|
| 1017 |
|
|
when "01101" => unitControl <= CODE_LDR3;
|
| 1018 |
|
|
when "01110" => unitControl <= CODE_STRB2;
|
| 1019 |
|
|
when "01111" => unitControl <= CODE_LDRB2;
|
| 1020 |
|
|
when "10000" => unitControl <= CODE_STRH2;
|
| 1021 |
|
|
when "10001" => unitControl <= CODE_LDRH2;
|
| 1022 |
|
|
when "10010" => unitControl <= CODE_STR3;
|
| 1023 |
|
|
when "10011" => unitControl <= CODE_LDR4;
|
| 1024 |
|
|
when "10100" => unitControl <= CODE_ADD5;
|
| 1025 |
|
|
when "10101" => unitControl <= CODE_ADD6;
|
| 1026 |
|
|
when "10110" =>
|
| 1027 |
|
|
case datain(10 downto 7) is
|
| 1028 |
|
|
when "0000" => unitControl <= CODE_ADD7;
|
| 1029 |
|
|
when "0001" => unitControl <= CODE_SUB4;
|
| 1030 |
|
|
when "0100" =>
|
| 1031 |
|
|
if datain(6) = '0' then
|
| 1032 |
|
|
unitControl <= CODE_SXTH1;
|
| 1033 |
|
|
else
|
| 1034 |
|
|
unitControl <= CODE_SXTB1;
|
| 1035 |
|
|
end if;
|
| 1036 |
|
|
when "0101" =>
|
| 1037 |
|
|
if datain(6) = '0' then
|
| 1038 |
|
|
unitControl <= CODE_UXTH1;
|
| 1039 |
|
|
else
|
| 1040 |
|
|
unitControl <= CODE_UXTB1;
|
| 1041 |
|
|
end if;
|
| 1042 |
|
|
when "1000" | "1001" | "1010" | "1011" =>
|
| 1043 |
|
|
unitControl <= CODE_PUSH1;
|
| 1044 |
|
|
when others => unitControl <= CODE_XXX;
|
| 1045 |
|
|
end case;
|
| 1046 |
|
|
when "10111" =>
|
| 1047 |
|
|
if datain(10 downto 8) = "100" or datain(10 downto 8) = "101" then
|
| 1048 |
|
|
unitControl <= CODE_POP1;
|
| 1049 |
|
|
else
|
| 1050 |
|
|
unitControl <= CODE_NOP;
|
| 1051 |
|
|
end if;
|
| 1052 |
|
|
when "11000" => unitControl <= CODE_STMIA1;
|
| 1053 |
|
|
when "11001" => unitControl <= CODE_LDMIA1;
|
| 1054 |
|
|
when "11010" | "11011" =>
|
| 1055 |
|
|
-- if datain(11 downto 8) = "1111" then
|
| 1056 |
|
|
-- unitControl <= CODE_SWI1;
|
| 1057 |
|
|
-- else
|
| 1058 |
|
|
unitControl <= CODE_BCC1;
|
| 1059 |
|
|
-- end if;
|
| 1060 |
|
|
when "11100" => unitControl <= CODE_B1;
|
| 1061 |
|
|
when "11101" => unitControl <= CODE_BLX1;
|
| 1062 |
|
|
when "11110" => unitControl <= CODE_BLX2;
|
| 1063 |
|
|
when "11111" => unitControl <= CODE_BL1;
|
| 1064 |
|
|
when others => unitControl <= CODE_XXX;
|
| 1065 |
|
|
end case; -- datain(15 downto 11)
|
| 1066 |
|
|
end process;
|
| 1067 |
|
|
|
| 1068 |
|
|
wrl <= writeL;
|
| 1069 |
|
|
wrH <= writeH;
|
| 1070 |
|
|
--#################################################################
|
| 1071 |
|
|
-- address bus multiplexer
|
| 1072 |
|
|
addr <= theRegisters(15) when addrMux = ADDR_PC else
|
| 1073 |
|
|
theRegisters(13) when addrMux = ADDR_SP else
|
| 1074 |
|
|
address;
|
| 1075 |
|
|
|
| 1076 |
|
|
--#################################################################
|
| 1077 |
|
|
-- check flags for branch
|
| 1078 |
|
|
process(datain, cpsrRegister)
|
| 1079 |
|
|
begin
|
| 1080 |
|
|
case datain(11 downto 8) is
|
| 1081 |
|
|
when "0000" => -- EQ
|
| 1082 |
|
|
if cpsrRegister(Z_FLAG) = '1' then
|
| 1083 |
|
|
branch <= '1';
|
| 1084 |
|
|
else
|
| 1085 |
|
|
branch <= '0';
|
| 1086 |
|
|
end if;
|
| 1087 |
|
|
when "0001" => -- NE
|
| 1088 |
|
|
if cpsrRegister(Z_FLAG) = '0' then
|
| 1089 |
|
|
branch <= '1';
|
| 1090 |
|
|
else
|
| 1091 |
|
|
branch <= '0';
|
| 1092 |
|
|
end if;
|
| 1093 |
|
|
when "0010" => -- CS
|
| 1094 |
|
|
if cpsrRegister(C_FLAG) = '1' then
|
| 1095 |
|
|
branch <= '1';
|
| 1096 |
|
|
else
|
| 1097 |
|
|
branch <= '0';
|
| 1098 |
|
|
end if;
|
| 1099 |
|
|
when "0011" => -- CC
|
| 1100 |
|
|
if cpsrRegister(C_FLAG) = '0' then
|
| 1101 |
|
|
branch <= '1';
|
| 1102 |
|
|
else
|
| 1103 |
|
|
branch <= '0';
|
| 1104 |
|
|
end if;
|
| 1105 |
|
|
when "0100" => -- MI
|
| 1106 |
|
|
if cpsrRegister(N_FLAG) = '1' then
|
| 1107 |
|
|
branch <= '1';
|
| 1108 |
|
|
else
|
| 1109 |
|
|
branch <= '0';
|
| 1110 |
|
|
end if;
|
| 1111 |
|
|
when "0101" => -- PL
|
| 1112 |
|
|
if cpsrRegister(N_FLAG) = '0' then
|
| 1113 |
|
|
branch <= '1';
|
| 1114 |
|
|
else
|
| 1115 |
|
|
branch <= '0';
|
| 1116 |
|
|
end if;
|
| 1117 |
|
|
when "0110" => -- VS
|
| 1118 |
|
|
if cpsrRegister(V_FLAG) = '1' then
|
| 1119 |
|
|
branch <= '1';
|
| 1120 |
|
|
else
|
| 1121 |
|
|
branch <= '0';
|
| 1122 |
|
|
end if;
|
| 1123 |
|
|
when "0111" => -- VC
|
| 1124 |
|
|
if cpsrRegister(V_FLAG) = '0' then
|
| 1125 |
|
|
branch <= '1';
|
| 1126 |
|
|
else
|
| 1127 |
|
|
branch <= '0';
|
| 1128 |
|
|
end if;
|
| 1129 |
|
|
when "1000" => -- HI
|
| 1130 |
|
|
if cpsrRegister(C_FLAG) = '1' and cpsrRegister(Z_FLAG) = '0' then
|
| 1131 |
|
|
branch <= '1';
|
| 1132 |
|
|
else
|
| 1133 |
|
|
branch <= '0';
|
| 1134 |
|
|
end if;
|
| 1135 |
|
|
when "1001" => -- LS
|
| 1136 |
|
|
if cpsrRegister(C_FLAG) = '0' or cpsrRegister(Z_FLAG) = '1' then
|
| 1137 |
|
|
branch <= '1';
|
| 1138 |
|
|
else
|
| 1139 |
|
|
branch <= '0';
|
| 1140 |
|
|
end if;
|
| 1141 |
|
|
when "1010" => -- GE
|
| 1142 |
|
|
if cpsrRegister(N_FLAG) = cpsrRegister(V_FLAG) then
|
| 1143 |
|
|
branch <= '1';
|
| 1144 |
|
|
else
|
| 1145 |
|
|
branch <= '0';
|
| 1146 |
|
|
end if;
|
| 1147 |
|
|
when "1011" => -- LT
|
| 1148 |
|
|
if cpsrRegister(N_FLAG) /= cpsrRegister(V_FLAG) then
|
| 1149 |
|
|
branch <= '1';
|
| 1150 |
|
|
else
|
| 1151 |
|
|
branch <= '0';
|
| 1152 |
|
|
end if;
|
| 1153 |
|
|
when "1100" => -- GT
|
| 1154 |
|
|
if cpsrRegister(Z_FLAG) = '0' and (cpsrRegister(N_FLAG) = cpsrRegister(V_FLAG)) then
|
| 1155 |
|
|
branch <= '1';
|
| 1156 |
|
|
else
|
| 1157 |
|
|
branch <= '0';
|
| 1158 |
|
|
end if;
|
| 1159 |
|
|
when "1101" => -- LE
|
| 1160 |
|
|
if cpsrRegister(Z_FLAG) = '1' or (cpsrRegister(N_FLAG) /= cpsrRegister(V_FLAG)) then
|
| 1161 |
|
|
branch <= '1';
|
| 1162 |
|
|
else
|
| 1163 |
|
|
branch <= '0';
|
| 1164 |
|
|
end if;
|
| 1165 |
|
|
when "1110" => -- AL
|
| 1166 |
|
|
branch <= '1';
|
| 1167 |
|
|
when others =>
|
| 1168 |
|
|
branch <= '0';
|
| 1169 |
|
|
end case; -- datain(11 downto 8)
|
| 1170 |
|
|
end process;
|
| 1171 |
|
|
|
| 1172 |
|
|
--#################################################################
|
| 1173 |
|
|
-- ARMT cpu main state machine
|
| 1174 |
|
|
process(rst, clk)
|
| 1175 |
|
|
variable tres : std_logic_vector(32 downto 0);
|
| 1176 |
|
|
variable tsum : std_logic_vector(31 downto 0);
|
| 1177 |
|
|
variable op1 : std_logic;
|
| 1178 |
|
|
variable op2 : std_logic;
|
| 1179 |
|
|
variable opr : std_logic;
|
| 1180 |
|
|
begin
|
| 1181 |
|
|
if rising_edge(clk) then
|
| 1182 |
|
|
if rst = '0' then
|
| 1183 |
|
|
theRegisters( 0) <= x"00000000";
|
| 1184 |
|
|
theRegisters( 1) <= x"00000000";
|
| 1185 |
|
|
theRegisters( 2) <= x"00000000";
|
| 1186 |
|
|
theRegisters( 3) <= x"00000000";
|
| 1187 |
|
|
theRegisters( 4) <= x"00000000";
|
| 1188 |
|
|
theRegisters( 5) <= x"00000000";
|
| 1189 |
|
|
theRegisters( 6) <= x"00000000";
|
| 1190 |
|
|
theRegisters( 7) <= x"00000000";
|
| 1191 |
|
|
theRegisters( 8) <= x"00000000";
|
| 1192 |
|
|
theRegisters( 9) <= x"00000000";
|
| 1193 |
|
|
theRegisters(10) <= x"00000000";
|
| 1194 |
|
|
theRegisters(11) <= x"00000000";
|
| 1195 |
|
|
theRegisters(12) <= x"00000000";
|
| 1196 |
|
|
theRegisters(13) <= x"00000000"; -- SP
|
| 1197 |
|
|
theRegisters(14) <= x"00000000"; -- LR
|
| 1198 |
|
|
theRegisters(15) <= x"00000000"; -- PC
|
| 1199 |
|
|
cpsrRegister <= x"00000000";
|
| 1200 |
|
|
cpuState <= STATE_RESET0;
|
| 1201 |
|
|
writeL <= '1';
|
| 1202 |
|
|
writeH <= '1';
|
| 1203 |
|
|
LDMread <= x"00";
|
| 1204 |
|
|
addrMux <= ADDR_PC;
|
| 1205 |
|
|
address <= x"00000000";
|
| 1206 |
|
|
irq_d <= '1';
|
| 1207 |
|
|
irqRequest <= '0';
|
| 1208 |
|
|
unitControl2 <= "0000000";
|
| 1209 |
|
|
else
|
| 1210 |
|
|
irq_d <= irq;
|
| 1211 |
|
|
if (irq = '0') and (irq_d = '1') then --and (flagI = '0') then -- irq falling edge ?
|
| 1212 |
|
|
irqRequest <= '1';
|
| 1213 |
|
|
end if;
|
| 1214 |
|
|
case cpuState is
|
| 1215 |
|
|
when STATE_RESET0 => -- ##################################################
|
| 1216 |
|
|
theRegisters(13)(15 downto 0) <= datain; -- STACK low
|
| 1217 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1218 |
|
|
cpuState <= STATE_RESET1;
|
| 1219 |
|
|
when STATE_RESET1 => -- ##################################################
|
| 1220 |
|
|
theRegisters(13)(31 downto 16) <= datain; -- STACK high
|
| 1221 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1222 |
|
|
cpuState <= STATE_RESET2;
|
| 1223 |
|
|
when STATE_RESET2 => -- ##################################################
|
| 1224 |
|
|
address(15 downto 0) <= datain and x"FFFE"; -- PC low make even address
|
| 1225 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1226 |
|
|
cpuState <= STATE_RESET3;
|
| 1227 |
|
|
when STATE_RESET3 => -- ##################################################
|
| 1228 |
|
|
theRegisters(15) <= datain & address(15 downto 0); -- PC high
|
| 1229 |
|
|
cpuState <= STATE_FETCH;
|
| 1230 |
|
|
when STATE_IRQ => -- ####################################################
|
| 1231 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1232 |
|
|
dataout <= cpsrRegister(15 downto 0);
|
| 1233 |
|
|
cpuState <= STATE_IRQ1;
|
| 1234 |
|
|
when STATE_IRQ1 => -- ####################################################
|
| 1235 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1236 |
|
|
dataout <= theRegisters(15)(31 downto 16);
|
| 1237 |
|
|
cpuState <= STATE_IRQ2;
|
| 1238 |
|
|
when STATE_IRQ2 => -- ####################################################
|
| 1239 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1240 |
|
|
dataout <= theRegisters(15)(15 downto 0);
|
| 1241 |
|
|
cpuState <= STATE_IRQ3;
|
| 1242 |
|
|
when STATE_IRQ3 => -- ####################################################
|
| 1243 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1244 |
|
|
dataout <= theRegisters(14)(31 downto 16); -- ??? FFFFFFF9
|
| 1245 |
|
|
cpuState <= STATE_IRQ4;
|
| 1246 |
|
|
when STATE_IRQ4 => -- ####################################################
|
| 1247 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1248 |
|
|
dataout <= theRegisters(14)(15 downto 0); -- ??? FFFFFFF9
|
| 1249 |
|
|
cpuState <= STATE_IRQ5;
|
| 1250 |
|
|
when STATE_IRQ5 => -- ####################################################
|
| 1251 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1252 |
|
|
dataout <= theRegisters(12)(31 downto 16);
|
| 1253 |
|
|
cpuState <= STATE_IRQ6;
|
| 1254 |
|
|
when STATE_IRQ6 => -- ####################################################
|
| 1255 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1256 |
|
|
dataout <= theRegisters(12)(15 downto 0);
|
| 1257 |
|
|
cpuState <= STATE_IRQ7;
|
| 1258 |
|
|
when STATE_IRQ7 => -- ####################################################
|
| 1259 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1260 |
|
|
dataout <= theRegisters(3)(31 downto 16);
|
| 1261 |
|
|
cpuState <= STATE_IRQ8;
|
| 1262 |
|
|
when STATE_IRQ8 => -- ####################################################
|
| 1263 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1264 |
|
|
dataout <= theRegisters(3)(15 downto 0);
|
| 1265 |
|
|
cpuState <= STATE_IRQ9;
|
| 1266 |
|
|
when STATE_IRQ9 => -- ####################################################
|
| 1267 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1268 |
|
|
dataout <= theRegisters(2)(31 downto 16);
|
| 1269 |
|
|
cpuState <= STATE_IRQ10;
|
| 1270 |
|
|
when STATE_IRQ10 => -- ####################################################
|
| 1271 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1272 |
|
|
dataout <= theRegisters(2)(15 downto 0);
|
| 1273 |
|
|
cpuState <= STATE_IRQ11;
|
| 1274 |
|
|
when STATE_IRQ11 => -- ####################################################
|
| 1275 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1276 |
|
|
dataout <= theRegisters(1)(31 downto 16);
|
| 1277 |
|
|
cpuState <= STATE_IRQ12;
|
| 1278 |
|
|
when STATE_IRQ12 => -- ####################################################
|
| 1279 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1280 |
|
|
dataout <= theRegisters(1)(15 downto 0);
|
| 1281 |
|
|
cpuState <= STATE_IRQ13;
|
| 1282 |
|
|
when STATE_IRQ13 => -- ####################################################
|
| 1283 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1284 |
|
|
dataout <= theRegisters(0)(31 downto 16);
|
| 1285 |
|
|
cpuState <= STATE_IRQ14;
|
| 1286 |
|
|
when STATE_IRQ14 => -- ####################################################
|
| 1287 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1288 |
|
|
dataout <= theRegisters(0)(15 downto 0);
|
| 1289 |
|
|
cpuState <= STATE_IRQ15;
|
| 1290 |
|
|
when STATE_IRQ15 => -- ####################################################
|
| 1291 |
|
|
writeL <= '1';
|
| 1292 |
|
|
writeH <= '1';
|
| 1293 |
|
|
theRegisters(14) <= x"FFFFFFF9"; -- exception return value
|
| 1294 |
|
|
address <= x"00000008"; -- NMI vector
|
| 1295 |
|
|
addrMux <= ADDR_RS;
|
| 1296 |
|
|
cpuState <= STATE_IRQ16;
|
| 1297 |
|
|
when STATE_IRQ16 => -- ###################################################
|
| 1298 |
|
|
theRegisters(15)(15 downto 0) <= datain and x"FFFE";
|
| 1299 |
|
|
address <= address + 2;
|
| 1300 |
|
|
cpuState <= STATE_IRQ17;
|
| 1301 |
|
|
when STATE_IRQ17 => -- ###################################################
|
| 1302 |
|
|
theRegisters(15)(31 downto 16) <= datain;
|
| 1303 |
|
|
addrMux <= ADDR_PC;
|
| 1304 |
|
|
cpuState <= STATE_FETCH;
|
| 1305 |
|
|
when STATE_RET => -- #####################################################
|
| 1306 |
|
|
addrMux <= ADDR_SP;
|
| 1307 |
|
|
cpuState <= STATE_RET1;
|
| 1308 |
|
|
when STATE_RET1 => -- #####################################################
|
| 1309 |
|
|
theRegisters(0)(15 downto 0) <= datain;
|
| 1310 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1311 |
|
|
cpuState <= STATE_RET2;
|
| 1312 |
|
|
when STATE_RET2 => -- #####################################################
|
| 1313 |
|
|
theRegisters(0)(31 downto 16) <= datain;
|
| 1314 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1315 |
|
|
cpuState <= STATE_RET3;
|
| 1316 |
|
|
when STATE_RET3 => -- #####################################################
|
| 1317 |
|
|
theRegisters(1)(15 downto 0) <= datain;
|
| 1318 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1319 |
|
|
cpuState <= STATE_RET4;
|
| 1320 |
|
|
when STATE_RET4 => -- #####################################################
|
| 1321 |
|
|
theRegisters(1)(31 downto 16) <= datain;
|
| 1322 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1323 |
|
|
cpuState <= STATE_RET5;
|
| 1324 |
|
|
when STATE_RET5 => -- #####################################################
|
| 1325 |
|
|
theRegisters(2)(15 downto 0) <= datain;
|
| 1326 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1327 |
|
|
cpuState <= STATE_RET6;
|
| 1328 |
|
|
when STATE_RET6 => -- #####################################################
|
| 1329 |
|
|
theRegisters(2)(31 downto 16) <= datain;
|
| 1330 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1331 |
|
|
cpuState <= STATE_RET7;
|
| 1332 |
|
|
when STATE_RET7 => -- #####################################################
|
| 1333 |
|
|
theRegisters(3)(15 downto 0) <= datain;
|
| 1334 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1335 |
|
|
cpuState <= STATE_RET8;
|
| 1336 |
|
|
when STATE_RET8 => -- #####################################################
|
| 1337 |
|
|
theRegisters(3)(31 downto 16) <= datain;
|
| 1338 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1339 |
|
|
cpuState <= STATE_RET9;
|
| 1340 |
|
|
when STATE_RET9 => -- #####################################################
|
| 1341 |
|
|
theRegisters(12)(15 downto 0) <= datain;
|
| 1342 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1343 |
|
|
cpuState <= STATE_RET10;
|
| 1344 |
|
|
when STATE_RET10 => -- #####################################################
|
| 1345 |
|
|
theRegisters(12)(31 downto 16) <= datain;
|
| 1346 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1347 |
|
|
cpuState <= STATE_RET11;
|
| 1348 |
|
|
when STATE_RET11 => -- #####################################################
|
| 1349 |
|
|
theRegisters(14)(15 downto 0) <= datain;
|
| 1350 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1351 |
|
|
cpuState <= STATE_RET12;
|
| 1352 |
|
|
when STATE_RET12 => -- #####################################################
|
| 1353 |
|
|
theRegisters(14)(31 downto 16) <= datain;
|
| 1354 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1355 |
|
|
cpuState <= STATE_RET13;
|
| 1356 |
|
|
when STATE_RET13 => -- #####################################################
|
| 1357 |
|
|
theRegisters(15)(15 downto 0) <= datain;
|
| 1358 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1359 |
|
|
cpuState <= STATE_RET14;
|
| 1360 |
|
|
when STATE_RET14 => -- #####################################################
|
| 1361 |
|
|
theRegisters(15)(31 downto 16) <= datain;
|
| 1362 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1363 |
|
|
cpuState <= STATE_RET15;
|
| 1364 |
|
|
when STATE_RET15 => -- #####################################################
|
| 1365 |
|
|
cpsrRegister(15 downto 0) <= datain;
|
| 1366 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1367 |
|
|
cpuState <= STATE_RET16;
|
| 1368 |
|
|
when STATE_RET16 => -- #####################################################
|
| 1369 |
|
|
cpsrRegister(31 downto 16) <= datain;
|
| 1370 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 1371 |
|
|
addrMux <= ADDR_PC;
|
| 1372 |
|
|
cpuState <= STATE_FETCH;
|
| 1373 |
|
|
when STATE_FETCH => -- ###################################################
|
| 1374 |
|
|
unitControl2 <= unitControl;
|
| 1375 |
|
|
opcode <= datain;
|
| 1376 |
|
|
if irqrequest = '1' then -- irq ???
|
| 1377 |
|
|
irqrequest <= '0';
|
| 1378 |
|
|
cpuState <= STATE_IRQ;
|
| 1379 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1380 |
|
|
addrMux <= ADDR_SP;
|
| 1381 |
|
|
dataout <= cpsrRegister(31 downto 16);
|
| 1382 |
|
|
writeL <= '0';
|
| 1383 |
|
|
writeH <= '0';
|
| 1384 |
|
|
else
|
| 1385 |
|
|
case unitControl is
|
| 1386 |
|
|
when CODE_LSL1 | CODE_LSR1 | CODE_ASR1 |
|
| 1387 |
|
|
CODE_LSL2 | CODE_LSR2 | CODE_ASR2 |
|
| 1388 |
|
|
CODE_ROR1 =>
|
| 1389 |
|
|
theRegisters(datain20) <= shiftResult;
|
| 1390 |
|
|
cpsrRegister(N_FLAG) <= shiftResult(31);
|
| 1391 |
|
|
if shiftResult = 0 then
|
| 1392 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1393 |
|
|
else
|
| 1394 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1395 |
|
|
end if;
|
| 1396 |
|
|
cpsrRegister(C_FLAG) <= cyShiftOut;
|
| 1397 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1398 |
|
|
when CODE_CPY1 => -- Rd = Rm
|
| 1399 |
|
|
if (datain(7) & datain(2 downto 0) = "1111") then
|
| 1400 |
|
|
theRegisters(conv_integer(datain(7) & datain(2 downto 0))) <=
|
| 1401 |
|
|
theRegisters(conv_integer(datain(6 downto 3)));
|
| 1402 |
|
|
else
|
| 1403 |
|
|
theRegisters(conv_integer(datain(7) & datain(2 downto 0))) <=
|
| 1404 |
|
|
theRegisters(conv_integer(datain(6 downto 3)));
|
| 1405 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1406 |
|
|
end if;
|
| 1407 |
|
|
when CODE_ADD4 => -- Rd = Rd + Rm
|
| 1408 |
|
|
if (datain(7) & datain(2 downto 0) = "1111") then
|
| 1409 |
|
|
theRegisters(conv_integer(datain(7) & datain(2 downto 0))) <=
|
| 1410 |
|
|
theRegisters(conv_integer(datain(7) & datain(2 downto 0))) +
|
| 1411 |
|
|
theRegisters(conv_integer(datain(6 downto 3)));
|
| 1412 |
|
|
else
|
| 1413 |
|
|
theRegisters(conv_integer(datain(7) & datain(2 downto 0))) <=
|
| 1414 |
|
|
theRegisters(conv_integer(datain(7) & datain(2 downto 0))) +
|
| 1415 |
|
|
theRegisters(conv_integer(datain(6 downto 3)));
|
| 1416 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1417 |
|
|
end if;
|
| 1418 |
|
|
when CODE_ADD6 => -- Rn = SP + imm
|
| 1419 |
|
|
theRegisters(datain108) <=
|
| 1420 |
|
|
theRegisters(13) +
|
| 1421 |
|
|
(x"00000" & "00" & datain(7 downto 0) & "00");
|
| 1422 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1423 |
|
|
when CODE_ADD7 => -- SP = SP + imm
|
| 1424 |
|
|
theRegisters(13) <= theRegisters(13) +
|
| 1425 |
|
|
(x"00000" & "000" & datain(6 downto 0) & "00");
|
| 1426 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1427 |
|
|
when CODE_SUB4 => -- SP = SP - imm
|
| 1428 |
|
|
theRegisters(13) <= theRegisters(13) -
|
| 1429 |
|
|
(x"00000" & "000" & datain(6 downto 0) & "00");
|
| 1430 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1431 |
|
|
when CODE_ADD1 =>
|
| 1432 |
|
|
tres := ("0" & theRegisters(datain53)) +
|
| 1433 |
|
|
("0" & theRegisters(datain86));
|
| 1434 |
|
|
theRegisters(datain20) <=
|
| 1435 |
|
|
theRegisters(datain53) +
|
| 1436 |
|
|
theRegisters(datain86);
|
| 1437 |
|
|
cpsrRegister(C_FLAG) <= tres(32);
|
| 1438 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1439 |
|
|
if tres(31 downto 0) = 0 then
|
| 1440 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1441 |
|
|
else
|
| 1442 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1443 |
|
|
end if;
|
| 1444 |
|
|
op1 := theRegisters(datain53)(31);
|
| 1445 |
|
|
op2 := theRegisters(datain86)(31);
|
| 1446 |
|
|
opr := tres(31);
|
| 1447 |
|
|
cpsrRegister(V_FLAG) <= (op1 and op2 and not opr) or
|
| 1448 |
|
|
(not op1 and not op2 and opr);
|
| 1449 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1450 |
|
|
when CODE_SUB1 =>
|
| 1451 |
|
|
tres := ("0" & theRegisters(datain53)) -
|
| 1452 |
|
|
("0" & theRegisters(datain86));
|
| 1453 |
|
|
theRegisters(datain20) <=
|
| 1454 |
|
|
theRegisters(datain53) -
|
| 1455 |
|
|
theRegisters(datain86);
|
| 1456 |
|
|
cpsrRegister(C_FLAG) <= not tres(32);
|
| 1457 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1458 |
|
|
if tres(31 downto 0) = 0 then
|
| 1459 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1460 |
|
|
else
|
| 1461 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1462 |
|
|
end if;
|
| 1463 |
|
|
op1 := theRegisters(datain53)(31);
|
| 1464 |
|
|
op2 := theRegisters(datain86)(31);
|
| 1465 |
|
|
opr := tres(31);
|
| 1466 |
|
|
cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
|
| 1467 |
|
|
(not op1 and op2 and opr);
|
| 1468 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1469 |
|
|
when CODE_ADD2 =>
|
| 1470 |
|
|
tres := ("0" & theRegisters(datain53)) +
|
| 1471 |
|
|
("0" & x"0000000" & "0" & datain(8 downto 6));
|
| 1472 |
|
|
theRegisters(datain20) <=
|
| 1473 |
|
|
theRegisters(datain53) +
|
| 1474 |
|
|
(x"0000000" & "0" & datain(8 downto 6));
|
| 1475 |
|
|
cpsrRegister(C_FLAG) <= tres(32);
|
| 1476 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1477 |
|
|
if tres(31 downto 0) = 0 then
|
| 1478 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1479 |
|
|
else
|
| 1480 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1481 |
|
|
end if;
|
| 1482 |
|
|
op1 := theRegisters(datain53)(31);
|
| 1483 |
|
|
op2 := '0';
|
| 1484 |
|
|
opr := tres(31);
|
| 1485 |
|
|
cpsrRegister(V_FLAG) <= (op1 and op2 and not opr) or
|
| 1486 |
|
|
(not op1 and not op2 and opr);
|
| 1487 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1488 |
|
|
when CODE_SUB2 =>
|
| 1489 |
|
|
tres := ("0" & theRegisters(datain53)) -
|
| 1490 |
|
|
("0" & x"0000000" & "0" & datain(8 downto 6));
|
| 1491 |
|
|
theRegisters(datain20) <=
|
| 1492 |
|
|
theRegisters(datain53) -
|
| 1493 |
|
|
(x"0000000" & "0" & datain(8 downto 6));
|
| 1494 |
|
|
cpsrRegister(C_FLAG) <= not tres(32);
|
| 1495 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1496 |
|
|
if tres(31 downto 0) = 0 then
|
| 1497 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1498 |
|
|
else
|
| 1499 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1500 |
|
|
end if;
|
| 1501 |
|
|
op1 := theRegisters(datain53)(31);
|
| 1502 |
|
|
op2 := '0';
|
| 1503 |
|
|
opr := tres(31);
|
| 1504 |
|
|
cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
|
| 1505 |
|
|
(not op1 and op2 and opr);
|
| 1506 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1507 |
|
|
when CODE_MOV1 =>
|
| 1508 |
|
|
tres := "0" & x"000000" & datain(7 downto 0);
|
| 1509 |
|
|
theRegisters(datain108) <= x"000000" & datain(7 downto 0);
|
| 1510 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1511 |
|
|
if tres(31 downto 0) = 0 then
|
| 1512 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1513 |
|
|
else
|
| 1514 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1515 |
|
|
end if;
|
| 1516 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1517 |
|
|
when CODE_CMP1 =>
|
| 1518 |
|
|
tres := ("0" & theRegisters(datain108)) -
|
| 1519 |
|
|
("0" & x"000000" & datain(7 downto 0));
|
| 1520 |
|
|
cpsrRegister(C_FLAG) <= not tres(32);
|
| 1521 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1522 |
|
|
if tres(31 downto 0) = 0 then
|
| 1523 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1524 |
|
|
else
|
| 1525 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1526 |
|
|
end if;
|
| 1527 |
|
|
op1 := theRegisters(datain108)(31);
|
| 1528 |
|
|
op2 := '0';
|
| 1529 |
|
|
opr := tres(31);
|
| 1530 |
|
|
cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
|
| 1531 |
|
|
(not op1 and op2 and opr);
|
| 1532 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1533 |
|
|
when CODE_ADD3 =>
|
| 1534 |
|
|
tres := ("0" & theRegisters(datain108)) +
|
| 1535 |
|
|
("0" & x"000000" & datain(7 downto 0));
|
| 1536 |
|
|
theRegisters(datain108) <=
|
| 1537 |
|
|
theRegisters(datain108) +
|
| 1538 |
|
|
(x"000000" & datain(7 downto 0));
|
| 1539 |
|
|
cpsrRegister(C_FLAG) <= tres(32);
|
| 1540 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1541 |
|
|
if tres(31 downto 0) = 0 then
|
| 1542 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1543 |
|
|
else
|
| 1544 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1545 |
|
|
end if;
|
| 1546 |
|
|
op1 := theRegisters(datain108)(31);
|
| 1547 |
|
|
op2 := '0';
|
| 1548 |
|
|
opr := tres(31);
|
| 1549 |
|
|
cpsrRegister(V_FLAG) <= (op1 and op2 and not opr) or
|
| 1550 |
|
|
(not op1 and not op2 and opr);
|
| 1551 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1552 |
|
|
when CODE_SUB3 =>
|
| 1553 |
|
|
tres := ("0" & theRegisters(datain108)) -
|
| 1554 |
|
|
("0" & x"000000" & datain(7 downto 0));
|
| 1555 |
|
|
theRegisters(datain108) <=
|
| 1556 |
|
|
theRegisters(datain108) -
|
| 1557 |
|
|
(x"000000" & datain(7 downto 0));
|
| 1558 |
|
|
cpsrRegister(C_FLAG) <= not tres(32);
|
| 1559 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1560 |
|
|
if tres(31 downto 0) = 0 then
|
| 1561 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1562 |
|
|
else
|
| 1563 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1564 |
|
|
end if;
|
| 1565 |
|
|
op1 := theRegisters(datain108)(31);
|
| 1566 |
|
|
op2 := '0';
|
| 1567 |
|
|
opr := tres(31);
|
| 1568 |
|
|
cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
|
| 1569 |
|
|
(not op1 and op2 and opr);
|
| 1570 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1571 |
|
|
when CODE_AND1 =>
|
| 1572 |
|
|
tres := ("0" & theRegisters(datain20)) and
|
| 1573 |
|
|
("0" & theRegisters(datain53));
|
| 1574 |
|
|
theRegisters(datain20) <=
|
| 1575 |
|
|
theRegisters(datain20) and
|
| 1576 |
|
|
theRegisters(datain53);
|
| 1577 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1578 |
|
|
if tres(31 downto 0) = 0 then
|
| 1579 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1580 |
|
|
else
|
| 1581 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1582 |
|
|
end if;
|
| 1583 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1584 |
|
|
when CODE_EOR1 =>
|
| 1585 |
|
|
tres := ("0" & theRegisters(datain20)) xor
|
| 1586 |
|
|
("0" & theRegisters(datain53));
|
| 1587 |
|
|
theRegisters(datain20) <=
|
| 1588 |
|
|
theRegisters(datain20) xor
|
| 1589 |
|
|
theRegisters(datain53);
|
| 1590 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1591 |
|
|
if tres(31 downto 0) = 0 then
|
| 1592 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1593 |
|
|
else
|
| 1594 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1595 |
|
|
end if;
|
| 1596 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1597 |
|
|
when CODE_ADC1 =>
|
| 1598 |
|
|
tres := ("0" & theRegisters(datain20)) +
|
| 1599 |
|
|
("0" & theRegisters(datain53)) +
|
| 1600 |
|
|
(x"00000000" & cpsrRegister(C_FLAG));
|
| 1601 |
|
|
theRegisters(datain20) <=
|
| 1602 |
|
|
theRegisters(datain20) +
|
| 1603 |
|
|
theRegisters(datain53) +
|
| 1604 |
|
|
("000" & x"0000000" & cpsrRegister(C_FLAG));
|
| 1605 |
|
|
cpsrRegister(C_FLAG) <= tres(32);
|
| 1606 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1607 |
|
|
if tres(31 downto 0) = 0 then
|
| 1608 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1609 |
|
|
else
|
| 1610 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1611 |
|
|
end if;
|
| 1612 |
|
|
op1 := theRegisters(datain20)(31);
|
| 1613 |
|
|
op2 := theRegisters(datain53)(31);
|
| 1614 |
|
|
opr := tres(31);
|
| 1615 |
|
|
cpsrRegister(V_FLAG) <= (op1 and op2 and not opr) or
|
| 1616 |
|
|
(not op1 and not op2 and opr);
|
| 1617 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1618 |
|
|
when CODE_SBC1 =>
|
| 1619 |
|
|
tres := ("0" & theRegisters(datain20)) -
|
| 1620 |
|
|
("0" & theRegisters(datain53)) -
|
| 1621 |
|
|
("000" & x"0000000" & (not cpsrRegister(C_FLAG)));
|
| 1622 |
|
|
theRegisters(datain20) <=
|
| 1623 |
|
|
theRegisters(datain20) -
|
| 1624 |
|
|
theRegisters(datain53) -
|
| 1625 |
|
|
("000" & x"0000000" & (not cpsrRegister(C_FLAG)));
|
| 1626 |
|
|
cpsrRegister(C_FLAG) <= not tres(32);
|
| 1627 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1628 |
|
|
if tres(31 downto 0) = 0 then
|
| 1629 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1630 |
|
|
else
|
| 1631 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1632 |
|
|
end if;
|
| 1633 |
|
|
op1 := theRegisters(datain20)(31);
|
| 1634 |
|
|
op2 := theRegisters(datain53)(31);
|
| 1635 |
|
|
opr := tres(31);
|
| 1636 |
|
|
cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
|
| 1637 |
|
|
(not op1 and op2 and opr);
|
| 1638 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1639 |
|
|
when CODE_TST1 =>
|
| 1640 |
|
|
tres := ("0" & theRegisters(datain20)) and
|
| 1641 |
|
|
("0" & theRegisters(datain53));
|
| 1642 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1643 |
|
|
if tres(31 downto 0) = 0 then
|
| 1644 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1645 |
|
|
else
|
| 1646 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1647 |
|
|
end if;
|
| 1648 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1649 |
|
|
when CODE_NEG1 =>
|
| 1650 |
|
|
tres := ("0" & x"00000000") -
|
| 1651 |
|
|
("0" & theRegisters(datain53));
|
| 1652 |
|
|
theRegisters(datain20) <=
|
| 1653 |
|
|
x"00000000" -
|
| 1654 |
|
|
theRegisters(datain53);
|
| 1655 |
|
|
cpsrRegister(C_FLAG) <= not tres(32);
|
| 1656 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1657 |
|
|
if tres(31 downto 0) = 0 then
|
| 1658 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1659 |
|
|
else
|
| 1660 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1661 |
|
|
end if;
|
| 1662 |
|
|
op1 := theRegisters(datain20)(31);
|
| 1663 |
|
|
op2 := theRegisters(datain53)(31);
|
| 1664 |
|
|
opr := tres(31);
|
| 1665 |
|
|
cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
|
| 1666 |
|
|
(not op1 and op2 and opr);
|
| 1667 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1668 |
|
|
when CODE_CMP2 =>
|
| 1669 |
|
|
tres := ("0" & theRegisters(datain20)) -
|
| 1670 |
|
|
("0" & theRegisters(datain53));
|
| 1671 |
|
|
cpsrRegister(C_FLAG) <= not tres(32);
|
| 1672 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1673 |
|
|
if tres(31 downto 0) = 0 then
|
| 1674 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1675 |
|
|
else
|
| 1676 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1677 |
|
|
end if;
|
| 1678 |
|
|
op1 := theRegisters(datain20)(31);
|
| 1679 |
|
|
op2 := theRegisters(datain53)(31);
|
| 1680 |
|
|
opr := tres(31);
|
| 1681 |
|
|
cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
|
| 1682 |
|
|
(not op1 and op2 and opr);
|
| 1683 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1684 |
|
|
when CODE_CMN1 =>
|
| 1685 |
|
|
tres := ("0" & theRegisters(datain20)) +
|
| 1686 |
|
|
("0" & theRegisters(datain53));
|
| 1687 |
|
|
cpsrRegister(C_FLAG) <= tres(32);
|
| 1688 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1689 |
|
|
if tres(31 downto 0) = 0 then
|
| 1690 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1691 |
|
|
else
|
| 1692 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1693 |
|
|
end if;
|
| 1694 |
|
|
op1 := theRegisters(datain20)(31);
|
| 1695 |
|
|
op2 := theRegisters(datain53)(31);
|
| 1696 |
|
|
opr := tres(31);
|
| 1697 |
|
|
cpsrRegister(V_FLAG) <= (op1 and op2 and not opr) or
|
| 1698 |
|
|
(not op1 and not op2 and opr);
|
| 1699 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1700 |
|
|
when CODE_ORR1 =>
|
| 1701 |
|
|
tres := ("0" & theRegisters(datain20)) or
|
| 1702 |
|
|
("0" & theRegisters(datain53));
|
| 1703 |
|
|
theRegisters(datain20) <=
|
| 1704 |
|
|
theRegisters(datain20) or
|
| 1705 |
|
|
theRegisters(datain53);
|
| 1706 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1707 |
|
|
if tres(31 downto 0) = 0 then
|
| 1708 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1709 |
|
|
else
|
| 1710 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1711 |
|
|
end if;
|
| 1712 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1713 |
|
|
when CODE_MUL1 =>
|
| 1714 |
|
|
theRegisters(datain20) <= product(31 downto 0);
|
| 1715 |
|
|
cpsrRegister(N_FLAG) <= product(31);
|
| 1716 |
|
|
if product(31 downto 0) = 0 then
|
| 1717 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1718 |
|
|
else
|
| 1719 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1720 |
|
|
end if;
|
| 1721 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1722 |
|
|
when CODE_BIC1 =>
|
| 1723 |
|
|
tres := ("0" & theRegisters(datain20)) and
|
| 1724 |
|
|
not ("0" & theRegisters(datain53));
|
| 1725 |
|
|
theRegisters(datain20) <=
|
| 1726 |
|
|
theRegisters(datain20) and
|
| 1727 |
|
|
not theRegisters(datain53);
|
| 1728 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1729 |
|
|
if tres(31 downto 0) = 0 then
|
| 1730 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1731 |
|
|
else
|
| 1732 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1733 |
|
|
end if;
|
| 1734 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1735 |
|
|
when CODE_MVN1 =>
|
| 1736 |
|
|
tres := not ("0" & theRegisters(datain53));
|
| 1737 |
|
|
theRegisters(datain20) <=
|
| 1738 |
|
|
not theRegisters(datain53);
|
| 1739 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1740 |
|
|
if tres(31 downto 0) = 0 then
|
| 1741 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1742 |
|
|
else
|
| 1743 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1744 |
|
|
end if;
|
| 1745 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1746 |
|
|
when CODE_CMP3 =>
|
| 1747 |
|
|
tres := ("0" & theRegisters(conv_integer(datain(7) & datain(2 downto 0)))) -
|
| 1748 |
|
|
("0" & theRegisters(conv_integer(datain(6) & datain(5 downto 3))));
|
| 1749 |
|
|
cpsrRegister(C_FLAG) <= not tres(32);
|
| 1750 |
|
|
cpsrRegister(N_FLAG) <= tres(31);
|
| 1751 |
|
|
if tres(31 downto 0) = 0 then
|
| 1752 |
|
|
cpsrRegister(Z_FLAG) <= '1';
|
| 1753 |
|
|
else
|
| 1754 |
|
|
cpsrRegister(Z_FLAG) <= '0';
|
| 1755 |
|
|
end if;
|
| 1756 |
|
|
op1 := theRegisters(conv_integer(datain(7) & datain(2 downto 0)))(31);
|
| 1757 |
|
|
op2 := theRegisters(conv_integer(datain(6) & datain(5 downto 3)))(31);
|
| 1758 |
|
|
opr := tres(31);
|
| 1759 |
|
|
cpsrRegister(V_FLAG) <= (op1 and not op2 and not opr) or
|
| 1760 |
|
|
(not op1 and op2 and opr);
|
| 1761 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1762 |
|
|
when CODE_BX1 =>
|
| 1763 |
|
|
if theRegisters(14) = x"FFFFFFF9" then -- EXC_RETURN ?
|
| 1764 |
|
|
if datain(6 downto 3) = "1110" then
|
| 1765 |
|
|
cpuState <= STATE_RET;
|
| 1766 |
|
|
else
|
| 1767 |
|
|
theRegisters(15) <= theRegisters(conv_integer(datain(6 downto 3)))(31 downto 1) & "0";
|
| 1768 |
|
|
theRegisters(14) <= theRegisters(15) + 2;
|
| 1769 |
|
|
end if;
|
| 1770 |
|
|
else
|
| 1771 |
|
|
theRegisters(15) <= theRegisters(conv_integer(datain(6 downto 3)))(31 downto 1) & "0";
|
| 1772 |
|
|
if datain(6 downto 3) /= "1110" then
|
| 1773 |
|
|
theRegisters(14) <= theRegisters(15) + 2;
|
| 1774 |
|
|
end if;
|
| 1775 |
|
|
end if;
|
| 1776 |
|
|
when CODE_LDR1 =>
|
| 1777 |
|
|
address <= (theRegisters(15) and x"FFFFFFFC") +
|
| 1778 |
|
|
(x"00000" & "00" & datain(7 downto 0) & "00") + x"00000004";
|
| 1779 |
|
|
addrMux <= ADDR_RS;
|
| 1780 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1781 |
|
|
cpuState <= STATE_READ1;
|
| 1782 |
|
|
when CODE_LDR4 =>
|
| 1783 |
|
|
address <= theRegisters(13) +
|
| 1784 |
|
|
(x"00000" & "00" & datain(7 downto 0) & "00");
|
| 1785 |
|
|
addrMux <= ADDR_RS;
|
| 1786 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1787 |
|
|
cpuState <= STATE_READ1;
|
| 1788 |
|
|
when CODE_STR1 | CODE_STRH1 =>
|
| 1789 |
|
|
address <= theRegisters(datain53) +
|
| 1790 |
|
|
theRegisters(datain86);
|
| 1791 |
|
|
addrMux <= ADDR_RS;
|
| 1792 |
|
|
writeL <= '0';
|
| 1793 |
|
|
writeH <= '0';
|
| 1794 |
|
|
dataout <= theRegisters(datain20)(15 downto 0);
|
| 1795 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1796 |
|
|
cpuState <= STATE_WRITE1;
|
| 1797 |
|
|
when CODE_STRB1 =>
|
| 1798 |
|
|
address <= theRegisters(datain53) +
|
| 1799 |
|
|
theRegisters(datain86);
|
| 1800 |
|
|
tsum := theRegisters(datain53) +
|
| 1801 |
|
|
theRegisters(datain86);
|
| 1802 |
|
|
addrMux <= ADDR_RS;
|
| 1803 |
|
|
if tsum(0) = '0' then
|
| 1804 |
|
|
writeL <= '0';
|
| 1805 |
|
|
writeH <= '1';
|
| 1806 |
|
|
else
|
| 1807 |
|
|
writeL <= '1';
|
| 1808 |
|
|
writeH <= '0';
|
| 1809 |
|
|
end if;
|
| 1810 |
|
|
dataout <= theRegisters(datain20)(7 downto 0) &
|
| 1811 |
|
|
theRegisters(datain20)(7 downto 0);
|
| 1812 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1813 |
|
|
cpuState <= STATE_WRITE1;
|
| 1814 |
|
|
when CODE_LDRSB1 | CODE_LDR2 | CODE_LDRH1 | CODE_LDRB1 | CODE_LDRSH1 =>
|
| 1815 |
|
|
address <= theRegisters(datain53) +
|
| 1816 |
|
|
theRegisters(datain86);
|
| 1817 |
|
|
addrMux <= ADDR_RS;
|
| 1818 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1819 |
|
|
cpuState <= STATE_READ1;
|
| 1820 |
|
|
when CODE_STR2 =>
|
| 1821 |
|
|
address <= theRegisters(datain53) +
|
| 1822 |
|
|
(x"000000" & "0" & datain(10 downto 6) & "00");
|
| 1823 |
|
|
addrMux <= ADDR_RS;
|
| 1824 |
|
|
writeL <= '0';
|
| 1825 |
|
|
writeH <= '0';
|
| 1826 |
|
|
dataout <= theRegisters(datain20)(15 downto 0);
|
| 1827 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1828 |
|
|
cpuState <= STATE_WRITE1;
|
| 1829 |
|
|
when CODE_LDR3 =>
|
| 1830 |
|
|
address <= theRegisters(datain53) +
|
| 1831 |
|
|
(x"000000" & "0" & datain(10 downto 6) & "00");
|
| 1832 |
|
|
addrMux <= ADDR_RS;
|
| 1833 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1834 |
|
|
cpuState <= STATE_READ1;
|
| 1835 |
|
|
when CODE_STRB2 =>
|
| 1836 |
|
|
address <= theRegisters(datain53) +
|
| 1837 |
|
|
(x"000000" & "000" & datain(10 downto 6));
|
| 1838 |
|
|
tsum := theRegisters(datain53) +
|
| 1839 |
|
|
(x"000000" & "000" & datain(10 downto 6));
|
| 1840 |
|
|
addrMux <= ADDR_RS;
|
| 1841 |
|
|
if tsum(0) = '0' then
|
| 1842 |
|
|
writeL <= '0';
|
| 1843 |
|
|
writeH <= '1';
|
| 1844 |
|
|
else
|
| 1845 |
|
|
writeL <= '1';
|
| 1846 |
|
|
writeH <= '0';
|
| 1847 |
|
|
end if;
|
| 1848 |
|
|
dataout <= theRegisters(datain20)(7 downto 0) &
|
| 1849 |
|
|
theRegisters(datain20)(7 downto 0);
|
| 1850 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1851 |
|
|
cpuState <= STATE_WRITE1;
|
| 1852 |
|
|
when CODE_LDRB2 =>
|
| 1853 |
|
|
address <= theRegisters(datain53) +
|
| 1854 |
|
|
(x"000000" & "000" & datain(10 downto 6));
|
| 1855 |
|
|
addrMux <= ADDR_RS;
|
| 1856 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1857 |
|
|
cpuState <= STATE_READ1;
|
| 1858 |
|
|
when CODE_LDRH2 =>
|
| 1859 |
|
|
address <= theRegisters(datain53) +
|
| 1860 |
|
|
(x"000000" & "00" & datain(10 downto 6) & "0");
|
| 1861 |
|
|
addrMux <= ADDR_RS;
|
| 1862 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1863 |
|
|
cpuState <= STATE_READ1;
|
| 1864 |
|
|
when CODE_STRH2 =>
|
| 1865 |
|
|
address <= theRegisters(datain53) +
|
| 1866 |
|
|
(x"000000" & "00" & datain(10 downto 6) & "0");
|
| 1867 |
|
|
addrMux <= ADDR_RS;
|
| 1868 |
|
|
writeL <= '0';
|
| 1869 |
|
|
writeH <= '0';
|
| 1870 |
|
|
dataout <= theRegisters(datain20)(15 downto 0);
|
| 1871 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1872 |
|
|
cpuState <= STATE_WRITE1;
|
| 1873 |
|
|
when CODE_STR3 =>
|
| 1874 |
|
|
address <= theRegisters(13) +
|
| 1875 |
|
|
(x"00000" & "00" & datain(7 downto 0) & "00");
|
| 1876 |
|
|
addrMux <= ADDR_RS;
|
| 1877 |
|
|
writeL <= '0';
|
| 1878 |
|
|
writeH <= '0';
|
| 1879 |
|
|
dataout <= theRegisters(datain108)(15 downto 0);
|
| 1880 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1881 |
|
|
cpuState <= STATE_WRITE1;
|
| 1882 |
|
|
when CODE_ADD5 =>
|
| 1883 |
|
|
theRegisters(datain108) <=
|
| 1884 |
|
|
theRegisters(15) + (x"00000" & "00" & datain(7 downto 0) & "00");
|
| 1885 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1886 |
|
|
cpuState <= STATE_FETCH;
|
| 1887 |
|
|
when CODE_SXTH1 =>
|
| 1888 |
|
|
theRegisters(datain20) <=
|
| 1889 |
|
|
theRegisters(datain53)(15) &
|
| 1890 |
|
|
theRegisters(datain53)(15) &
|
| 1891 |
|
|
theRegisters(datain53)(15) &
|
| 1892 |
|
|
theRegisters(datain53)(15) &
|
| 1893 |
|
|
theRegisters(datain53)(15) &
|
| 1894 |
|
|
theRegisters(datain53)(15) &
|
| 1895 |
|
|
theRegisters(datain53)(15) &
|
| 1896 |
|
|
theRegisters(datain53)(15) &
|
| 1897 |
|
|
theRegisters(datain53)(15) &
|
| 1898 |
|
|
theRegisters(datain53)(15) &
|
| 1899 |
|
|
theRegisters(datain53)(15) &
|
| 1900 |
|
|
theRegisters(datain53)(15) &
|
| 1901 |
|
|
theRegisters(datain53)(15) &
|
| 1902 |
|
|
theRegisters(datain53)(15) &
|
| 1903 |
|
|
theRegisters(datain53)(15) &
|
| 1904 |
|
|
theRegisters(datain53)(15) &
|
| 1905 |
|
|
theRegisters(datain53)(15 downto 0);
|
| 1906 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1907 |
|
|
cpuState <= STATE_FETCH;
|
| 1908 |
|
|
when CODE_SXTB1 =>
|
| 1909 |
|
|
theRegisters(datain20) <=
|
| 1910 |
|
|
theRegisters(datain53)(7) &
|
| 1911 |
|
|
theRegisters(datain53)(7) &
|
| 1912 |
|
|
theRegisters(datain53)(7) &
|
| 1913 |
|
|
theRegisters(datain53)(7) &
|
| 1914 |
|
|
theRegisters(datain53)(7) &
|
| 1915 |
|
|
theRegisters(datain53)(7) &
|
| 1916 |
|
|
theRegisters(datain53)(7) &
|
| 1917 |
|
|
theRegisters(datain53)(7) &
|
| 1918 |
|
|
theRegisters(datain53)(7) &
|
| 1919 |
|
|
theRegisters(datain53)(7) &
|
| 1920 |
|
|
theRegisters(datain53)(7) &
|
| 1921 |
|
|
theRegisters(datain53)(7) &
|
| 1922 |
|
|
theRegisters(datain53)(7) &
|
| 1923 |
|
|
theRegisters(datain53)(7) &
|
| 1924 |
|
|
theRegisters(datain53)(7) &
|
| 1925 |
|
|
theRegisters(datain53)(7) &
|
| 1926 |
|
|
theRegisters(datain53)(7) &
|
| 1927 |
|
|
theRegisters(datain53)(7) &
|
| 1928 |
|
|
theRegisters(datain53)(7) &
|
| 1929 |
|
|
theRegisters(datain53)(7) &
|
| 1930 |
|
|
theRegisters(datain53)(7) &
|
| 1931 |
|
|
theRegisters(datain53)(7) &
|
| 1932 |
|
|
theRegisters(datain53)(7) &
|
| 1933 |
|
|
theRegisters(datain53)(7) &
|
| 1934 |
|
|
theRegisters(datain53)(7 downto 0);
|
| 1935 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1936 |
|
|
cpuState <= STATE_FETCH;
|
| 1937 |
|
|
when CODE_UXTH1 =>
|
| 1938 |
|
|
theRegisters(datain20) <= x"0000" &
|
| 1939 |
|
|
theRegisters(datain53)(15 downto 0);
|
| 1940 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1941 |
|
|
cpuState <= STATE_FETCH;
|
| 1942 |
|
|
when CODE_UXTB1 =>
|
| 1943 |
|
|
theRegisters(datain20) <= x"000000" &
|
| 1944 |
|
|
theRegisters(datain53)(7 downto 0);
|
| 1945 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1946 |
|
|
cpuState <= STATE_FETCH;
|
| 1947 |
|
|
when CODE_PUSH1 =>
|
| 1948 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1949 |
|
|
if datain(8 downto 0) = 0 then
|
| 1950 |
|
|
cpuState <= STATE_FETCH;
|
| 1951 |
|
|
else
|
| 1952 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 1953 |
|
|
addrMux <= ADDR_SP;
|
| 1954 |
|
|
writeL <= '0';
|
| 1955 |
|
|
writeH <= '0';
|
| 1956 |
|
|
if datain(8) = '1' then
|
| 1957 |
|
|
dataout <= theRegisters(14)(31 downto 16);
|
| 1958 |
|
|
cpuState <= STATE_WRPH;
|
| 1959 |
|
|
elsif datain(7) = '1' then
|
| 1960 |
|
|
dataout <= theRegisters(7)(31 downto 16);
|
| 1961 |
|
|
cpuState <= STATE_WR7H;
|
| 1962 |
|
|
elsif datain(6) = '1' then
|
| 1963 |
|
|
dataout <= theRegisters(6)(31 downto 16);
|
| 1964 |
|
|
cpuState <= STATE_WR6H;
|
| 1965 |
|
|
elsif datain(5) = '1' then
|
| 1966 |
|
|
dataout <= theRegisters(5)(31 downto 16);
|
| 1967 |
|
|
cpuState <= STATE_WR5H;
|
| 1968 |
|
|
elsif datain(4) = '1' then
|
| 1969 |
|
|
dataout <= theRegisters(4)(31 downto 16);
|
| 1970 |
|
|
cpuState <= STATE_WR4H;
|
| 1971 |
|
|
elsif datain(3) = '1' then
|
| 1972 |
|
|
dataout <= theRegisters(3)(31 downto 16);
|
| 1973 |
|
|
cpuState <= STATE_WR3H;
|
| 1974 |
|
|
elsif datain(2) = '1' then
|
| 1975 |
|
|
dataout <= theRegisters(2)(31 downto 16);
|
| 1976 |
|
|
cpuState <= STATE_WR2H;
|
| 1977 |
|
|
elsif datain(1) = '1' then
|
| 1978 |
|
|
dataout <= theRegisters(1)(31 downto 16);
|
| 1979 |
|
|
cpuState <= STATE_WR1H;
|
| 1980 |
|
|
else
|
| 1981 |
|
|
dataout <= theRegisters(0)(31 downto 16);
|
| 1982 |
|
|
cpuState <= STATE_WR0H;
|
| 1983 |
|
|
end if;
|
| 1984 |
|
|
end if;
|
| 1985 |
|
|
when CODE_POP1 =>
|
| 1986 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 1987 |
|
|
if datain(8 downto 0) = 0 then
|
| 1988 |
|
|
cpuState <= STATE_FETCH;
|
| 1989 |
|
|
else
|
| 1990 |
|
|
addrMux <= ADDR_SP;
|
| 1991 |
|
|
if datain(0) = '1' then
|
| 1992 |
|
|
cpuState <= STATE_RD0L;
|
| 1993 |
|
|
elsif datain(1) = '1' then
|
| 1994 |
|
|
cpuState <= STATE_RD1L;
|
| 1995 |
|
|
elsif datain(2) = '1' then
|
| 1996 |
|
|
cpuState <= STATE_RD2L;
|
| 1997 |
|
|
elsif datain(3) = '1' then
|
| 1998 |
|
|
cpuState <= STATE_RD3L;
|
| 1999 |
|
|
elsif datain(4) = '1' then
|
| 2000 |
|
|
cpuState <= STATE_RD4L;
|
| 2001 |
|
|
elsif datain(5) = '1' then
|
| 2002 |
|
|
cpuState <= STATE_RD5L;
|
| 2003 |
|
|
elsif datain(6) = '1' then
|
| 2004 |
|
|
cpuState <= STATE_RD6L;
|
| 2005 |
|
|
elsif datain(7) = '1' then
|
| 2006 |
|
|
cpuState <= STATE_RD7L;
|
| 2007 |
|
|
else
|
| 2008 |
|
|
cpuState <= STATE_RDPL;
|
| 2009 |
|
|
end if;
|
| 2010 |
|
|
end if;
|
| 2011 |
|
|
when CODE_NOP =>
|
| 2012 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 2013 |
|
|
when CODE_STMIA1 =>
|
| 2014 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 2015 |
|
|
if datain(7 downto 0) = 0 then
|
| 2016 |
|
|
cpuState <= STATE_FETCH;
|
| 2017 |
|
|
else
|
| 2018 |
|
|
address <= theRegisters(datain108);
|
| 2019 |
|
|
addrMux <= ADDR_RS;
|
| 2020 |
|
|
writeL <= '0';
|
| 2021 |
|
|
writeH <= '0';
|
| 2022 |
|
|
if datain(0) = '1' then
|
| 2023 |
|
|
dataout <= theRegisters(0)(15 downto 0);
|
| 2024 |
|
|
cpuState <= STATE_WR0H;
|
| 2025 |
|
|
elsif datain(1) = '1' then
|
| 2026 |
|
|
dataout <= theRegisters(1)(15 downto 0);
|
| 2027 |
|
|
cpuState <= STATE_WR1H;
|
| 2028 |
|
|
elsif datain(2) = '1' then
|
| 2029 |
|
|
dataout <= theRegisters(2)(15 downto 0);
|
| 2030 |
|
|
cpuState <= STATE_WR2H;
|
| 2031 |
|
|
elsif datain(3) = '1' then
|
| 2032 |
|
|
dataout <= theRegisters(3)(15 downto 0);
|
| 2033 |
|
|
cpuState <= STATE_WR3H;
|
| 2034 |
|
|
elsif datain(4) = '1' then
|
| 2035 |
|
|
dataout <= theRegisters(4)(15 downto 0);
|
| 2036 |
|
|
cpuState <= STATE_WR4H;
|
| 2037 |
|
|
elsif datain(5) = '1' then
|
| 2038 |
|
|
dataout <= theRegisters(5)(15 downto 0);
|
| 2039 |
|
|
cpuState <= STATE_WR5H;
|
| 2040 |
|
|
elsif datain(6) = '1' then
|
| 2041 |
|
|
dataout <= theRegisters(6)(15 downto 0);
|
| 2042 |
|
|
cpuState <= STATE_WR6H;
|
| 2043 |
|
|
else
|
| 2044 |
|
|
dataout <= theRegisters(7)(15 downto 0);
|
| 2045 |
|
|
cpuState <= STATE_WR7H;
|
| 2046 |
|
|
end if;
|
| 2047 |
|
|
end if;
|
| 2048 |
|
|
when CODE_LDMIA1 =>
|
| 2049 |
|
|
LDMread <= x"00";
|
| 2050 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 2051 |
|
|
if datain(7 downto 0) = 0 then
|
| 2052 |
|
|
cpuState <= STATE_FETCH;
|
| 2053 |
|
|
else
|
| 2054 |
|
|
address <= theRegisters(datain108);
|
| 2055 |
|
|
addrMux <= ADDR_RS;
|
| 2056 |
|
|
if datain(0) = '1' then
|
| 2057 |
|
|
cpuState <= STATE_RD0L;
|
| 2058 |
|
|
elsif datain(1) = '1' then
|
| 2059 |
|
|
cpuState <= STATE_RD1L;
|
| 2060 |
|
|
elsif datain(2) = '1' then
|
| 2061 |
|
|
cpuState <= STATE_RD2L;
|
| 2062 |
|
|
elsif datain(3) = '1' then
|
| 2063 |
|
|
cpuState <= STATE_RD3L;
|
| 2064 |
|
|
elsif datain(4) = '1' then
|
| 2065 |
|
|
cpuState <= STATE_RD4L;
|
| 2066 |
|
|
elsif datain(5) = '1' then
|
| 2067 |
|
|
cpuState <= STATE_RD5L;
|
| 2068 |
|
|
elsif datain(6) = '1' then
|
| 2069 |
|
|
cpuState <= STATE_RD6L;
|
| 2070 |
|
|
else
|
| 2071 |
|
|
cpuState <= STATE_RD7L;
|
| 2072 |
|
|
end if;
|
| 2073 |
|
|
end if;
|
| 2074 |
|
|
when CODE_BCC1 =>
|
| 2075 |
|
|
if branch = '1' then
|
| 2076 |
|
|
theRegisters(15) <= theRegisters(15) + (
|
| 2077 |
|
|
datain(7) & datain(7) & datain(7) & datain(7) &
|
| 2078 |
|
|
datain(7) & datain(7) & datain(7) & datain(7) &
|
| 2079 |
|
|
datain(7) & datain(7) & datain(7) & datain(7) &
|
| 2080 |
|
|
datain(7) & datain(7) & datain(7) & datain(7) &
|
| 2081 |
|
|
datain(7) & datain(7) & datain(7) & datain(7) &
|
| 2082 |
|
|
datain(7) & datain(7) & datain(7) &
|
| 2083 |
|
|
datain(7 downto 0) & "0") + x"00000004";
|
| 2084 |
|
|
else
|
| 2085 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 2086 |
|
|
end if;
|
| 2087 |
|
|
when CODE_B1 =>
|
| 2088 |
|
|
theRegisters(15) <= theRegisters(15) + (
|
| 2089 |
|
|
datain(10) & datain(10) & datain(10) & datain(10) &
|
| 2090 |
|
|
datain(10) & datain(10) & datain(10) & datain(10) &
|
| 2091 |
|
|
datain(10) & datain(10) & datain(10) & datain(10) &
|
| 2092 |
|
|
datain(10) & datain(10) & datain(10) & datain(10) &
|
| 2093 |
|
|
datain(10) & datain(10) & datain(10) & datain(10) &
|
| 2094 |
|
|
datain(10 downto 0) & "0") + x"00000004";
|
| 2095 |
|
|
when CODE_BLX2 =>
|
| 2096 |
|
|
theRegisters(14) <= theRegisters(15) + (
|
| 2097 |
|
|
datain(10) & datain(10) & datain(10) & datain(10) &
|
| 2098 |
|
|
datain(10) & datain(10) & datain(10) & datain(10) &
|
| 2099 |
|
|
datain(10) &
|
| 2100 |
|
|
datain(10 downto 0) & x"000") + x"00000004";
|
| 2101 |
|
|
theRegisters(15) <= theRegisters(15) + 2;
|
| 2102 |
|
|
when CODE_BL1 =>
|
| 2103 |
|
|
theRegisters(15) <= theRegisters(14) + (x"00000" &
|
| 2104 |
|
|
datain(10 downto 0) & "0");
|
| 2105 |
|
|
theRegisters(14) <= theRegisters(15) + 2;
|
| 2106 |
|
|
|
| 2107 |
|
|
when others =>
|
| 2108 |
|
|
cpuState <= STATE_FETCH;
|
| 2109 |
|
|
end case; -- unitControl
|
| 2110 |
|
|
end if; -- irqrequest
|
| 2111 |
|
|
when STATE_READ1 => -- ##################################################
|
| 2112 |
|
|
case unitControl2 is
|
| 2113 |
|
|
when CODE_LDRH1 | CODE_LDRH2 =>
|
| 2114 |
|
|
theRegisters(opcode20)(15 downto 0) <= datain;
|
| 2115 |
|
|
addrMux <= ADDR_PC;
|
| 2116 |
|
|
cpuState <= STATE_FETCH;
|
| 2117 |
|
|
when CODE_LDRSH1 =>
|
| 2118 |
|
|
theRegisters(opcode20)(15 downto 0) <= datain;
|
| 2119 |
|
|
theRegisters(opcode20)(31 downto 16) <=
|
| 2120 |
|
|
datain(15) & datain(15) & datain(15) & datain(15) & datain(15) & datain(15) &
|
| 2121 |
|
|
datain(15) & datain(15) & datain(15) & datain(15) & datain(15) & datain(15) &
|
| 2122 |
|
|
datain(15) & datain(15) & datain(15) & datain(15);
|
| 2123 |
|
|
addrMux <= ADDR_PC;
|
| 2124 |
|
|
cpuState <= STATE_FETCH;
|
| 2125 |
|
|
when CODE_LDR1 | CODE_LDR4 =>
|
| 2126 |
|
|
theRegisters(opcode108)(15 downto 0) <= datain;
|
| 2127 |
|
|
address <= address + 2;
|
| 2128 |
|
|
cpuState <= STATE_READ2;
|
| 2129 |
|
|
when CODE_LDR2 | CODE_LDR3 =>
|
| 2130 |
|
|
theRegisters(opcode20)(15 downto 0) <= datain;
|
| 2131 |
|
|
address <= address + 2;
|
| 2132 |
|
|
cpuState <= STATE_READ2;
|
| 2133 |
|
|
when CODE_LDRSB1 =>
|
| 2134 |
|
|
if address(0) = '0' then
|
| 2135 |
|
|
theRegisters(opcode20)(7 downto 0) <= datain(7 downto 0);
|
| 2136 |
|
|
theRegisters(opcode20)(31 downto 8) <=
|
| 2137 |
|
|
datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) &
|
| 2138 |
|
|
datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) &
|
| 2139 |
|
|
datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7) &
|
| 2140 |
|
|
datain(7) & datain(7) & datain(7) & datain(7) & datain(7) & datain(7);
|
| 2141 |
|
|
else
|
| 2142 |
|
|
theRegisters(opcode20)(7 downto 0) <= datain(15 downto 8);
|
| 2143 |
|
|
theRegisters(opcode20)(31 downto 8) <=
|
| 2144 |
|
|
datain(15) & datain(15) & datain(15) & datain(15) & datain(15) & datain(15) &
|
| 2145 |
|
|
datain(15) & datain(15) & datain(15) & datain(15) & datain(15) & datain(15) &
|
| 2146 |
|
|
datain(15) & datain(15) & datain(15) & datain(15) & datain(15) & datain(15) &
|
| 2147 |
|
|
datain(15) & datain(15) & datain(15) & datain(15) & datain(15) & datain(15);
|
| 2148 |
|
|
end if;
|
| 2149 |
|
|
addrMux <= ADDR_PC;
|
| 2150 |
|
|
cpuState <= STATE_FETCH;
|
| 2151 |
|
|
when CODE_LDRB1 | CODE_LDRB2 =>
|
| 2152 |
|
|
if address(0) = '0' then
|
| 2153 |
|
|
theRegisters(opcode20)(7 downto 0) <= datain(7 downto 0);
|
| 2154 |
|
|
else
|
| 2155 |
|
|
theRegisters(opcode20)(7 downto 0) <= datain(15 downto 8);
|
| 2156 |
|
|
end if;
|
| 2157 |
|
|
theRegisters(opcode20)(31 downto 8) <= x"000000";
|
| 2158 |
|
|
addrMux <= ADDR_PC;
|
| 2159 |
|
|
cpuState <= STATE_FETCH;
|
| 2160 |
|
|
|
| 2161 |
|
|
when others =>
|
| 2162 |
|
|
cpuState <= STATE_FETCH;
|
| 2163 |
|
|
end case; -- unitControl2
|
| 2164 |
|
|
|
| 2165 |
|
|
when STATE_READ2 => -- ##################################################
|
| 2166 |
|
|
case unitControl2 is
|
| 2167 |
|
|
when CODE_LDR1 | CODE_LDR4 =>
|
| 2168 |
|
|
theRegisters(opcode108)(31 downto 16) <= datain;
|
| 2169 |
|
|
addrMux <= ADDR_PC;
|
| 2170 |
|
|
cpuState <= STATE_FETCH;
|
| 2171 |
|
|
when CODE_LDR2 | CODE_LDR3 =>
|
| 2172 |
|
|
theRegisters(opcode20)(31 downto 16) <= datain;
|
| 2173 |
|
|
addrMux <= ADDR_PC;
|
| 2174 |
|
|
cpuState <= STATE_FETCH;
|
| 2175 |
|
|
|
| 2176 |
|
|
when others =>
|
| 2177 |
|
|
cpuState <= STATE_FETCH;
|
| 2178 |
|
|
end case; -- unitControl2
|
| 2179 |
|
|
|
| 2180 |
|
|
when STATE_RD0L => -- ##################################################
|
| 2181 |
|
|
case unitControl2 is
|
| 2182 |
|
|
when CODE_POP1 =>
|
| 2183 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2184 |
|
|
theRegisters(0)(15 downto 0) <= datain;
|
| 2185 |
|
|
cpuState <= STATE_RD0H;
|
| 2186 |
|
|
when CODE_LDMIA1 =>
|
| 2187 |
|
|
LDMread(0) <= '1';
|
| 2188 |
|
|
theRegisters(0)(15 downto 0) <= datain;
|
| 2189 |
|
|
address <= address + 2;
|
| 2190 |
|
|
cpuState <= STATE_RD0H;
|
| 2191 |
|
|
|
| 2192 |
|
|
when others =>
|
| 2193 |
|
|
cpuState <= STATE_FETCH;
|
| 2194 |
|
|
end case; -- unitControl2
|
| 2195 |
|
|
|
| 2196 |
|
|
when STATE_RD0H => -- ##################################################
|
| 2197 |
|
|
case unitControl2 is
|
| 2198 |
|
|
when CODE_POP1 =>
|
| 2199 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2200 |
|
|
theRegisters(0)(31 downto 16) <= datain;
|
| 2201 |
|
|
if opcode(8 downto 1) = 0 then
|
| 2202 |
|
|
addrMux <= ADDR_PC;
|
| 2203 |
|
|
cpuState <= STATE_FETCH;
|
| 2204 |
|
|
else
|
| 2205 |
|
|
if opcode(1) = '1' then
|
| 2206 |
|
|
cpuState <= STATE_RD1L;
|
| 2207 |
|
|
elsif opcode(2) = '1' then
|
| 2208 |
|
|
cpuState <= STATE_RD2L;
|
| 2209 |
|
|
elsif opcode(3) = '1' then
|
| 2210 |
|
|
cpuState <= STATE_RD3L;
|
| 2211 |
|
|
elsif opcode(4) = '1' then
|
| 2212 |
|
|
cpuState <= STATE_RD4L;
|
| 2213 |
|
|
elsif opcode(5) = '1' then
|
| 2214 |
|
|
cpuState <= STATE_RD5L;
|
| 2215 |
|
|
elsif opcode(6) = '1' then
|
| 2216 |
|
|
cpuState <= STATE_RD6L;
|
| 2217 |
|
|
elsif opcode(7) = '1' then
|
| 2218 |
|
|
cpuState <= STATE_RD7L;
|
| 2219 |
|
|
else
|
| 2220 |
|
|
cpuState <= STATE_RDPL;
|
| 2221 |
|
|
end if;
|
| 2222 |
|
|
end if;
|
| 2223 |
|
|
when CODE_LDMIA1 =>
|
| 2224 |
|
|
address <= address + 2;
|
| 2225 |
|
|
if opcode(7 downto 1) = 0 then
|
| 2226 |
|
|
addrMux <= ADDR_PC;
|
| 2227 |
|
|
if opcode108 = 0 then
|
| 2228 |
|
|
theRegisters(0)(31 downto 16) <= datain;
|
| 2229 |
|
|
else
|
| 2230 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 2231 |
|
|
end if;
|
| 2232 |
|
|
cpuState <= STATE_FETCH;
|
| 2233 |
|
|
else
|
| 2234 |
|
|
theRegisters(0)(31 downto 16) <= datain;
|
| 2235 |
|
|
if opcode(1) = '1' then
|
| 2236 |
|
|
cpuState <= STATE_RD1L;
|
| 2237 |
|
|
elsif opcode(2) = '1' then
|
| 2238 |
|
|
cpuState <= STATE_RD2L;
|
| 2239 |
|
|
elsif opcode(3) = '1' then
|
| 2240 |
|
|
cpuState <= STATE_RD3L;
|
| 2241 |
|
|
elsif opcode(4) = '1' then
|
| 2242 |
|
|
cpuState <= STATE_RD4L;
|
| 2243 |
|
|
elsif opcode(5) = '1' then
|
| 2244 |
|
|
cpuState <= STATE_RD5L;
|
| 2245 |
|
|
elsif opcode(6) = '1' then
|
| 2246 |
|
|
cpuState <= STATE_RD6L;
|
| 2247 |
|
|
else
|
| 2248 |
|
|
cpuState <= STATE_RD7L;
|
| 2249 |
|
|
end if;
|
| 2250 |
|
|
end if;
|
| 2251 |
|
|
|
| 2252 |
|
|
when others =>
|
| 2253 |
|
|
cpuState <= STATE_FETCH;
|
| 2254 |
|
|
end case; -- unitControl2
|
| 2255 |
|
|
|
| 2256 |
|
|
when STATE_RD1L => -- ##################################################
|
| 2257 |
|
|
case unitControl2 is
|
| 2258 |
|
|
when CODE_POP1 =>
|
| 2259 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2260 |
|
|
theRegisters(1)(15 downto 0) <= datain;
|
| 2261 |
|
|
cpuState <= STATE_RD1H;
|
| 2262 |
|
|
when CODE_LDMIA1 =>
|
| 2263 |
|
|
LDMread(1) <= '1';
|
| 2264 |
|
|
theRegisters(1)(15 downto 0) <= datain;
|
| 2265 |
|
|
address <= address + 2;
|
| 2266 |
|
|
cpuState <= STATE_RD1H;
|
| 2267 |
|
|
|
| 2268 |
|
|
when others =>
|
| 2269 |
|
|
cpuState <= STATE_FETCH;
|
| 2270 |
|
|
end case; -- unitControl2
|
| 2271 |
|
|
|
| 2272 |
|
|
when STATE_RD1H => -- ##################################################
|
| 2273 |
|
|
case unitControl2 is
|
| 2274 |
|
|
when CODE_POP1 =>
|
| 2275 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2276 |
|
|
theRegisters(1)(31 downto 16) <= datain;
|
| 2277 |
|
|
if opcode(8 downto 2) = 0 then
|
| 2278 |
|
|
addrMux <= ADDR_PC;
|
| 2279 |
|
|
cpuState <= STATE_FETCH;
|
| 2280 |
|
|
else
|
| 2281 |
|
|
if opcode(2) = '1' then
|
| 2282 |
|
|
cpuState <= STATE_RD2L;
|
| 2283 |
|
|
elsif opcode(3) = '1' then
|
| 2284 |
|
|
cpuState <= STATE_RD3L;
|
| 2285 |
|
|
elsif opcode(4) = '1' then
|
| 2286 |
|
|
cpuState <= STATE_RD4L;
|
| 2287 |
|
|
elsif opcode(5) = '1' then
|
| 2288 |
|
|
cpuState <= STATE_RD5L;
|
| 2289 |
|
|
elsif opcode(6) = '1' then
|
| 2290 |
|
|
cpuState <= STATE_RD6L;
|
| 2291 |
|
|
elsif opcode(7) = '1' then
|
| 2292 |
|
|
cpuState <= STATE_RD7L;
|
| 2293 |
|
|
else
|
| 2294 |
|
|
cpuState <= STATE_RDPL;
|
| 2295 |
|
|
end if;
|
| 2296 |
|
|
end if;
|
| 2297 |
|
|
when CODE_LDMIA1 =>
|
| 2298 |
|
|
address <= address + 2;
|
| 2299 |
|
|
if opcode(7 downto 2) = 0 then
|
| 2300 |
|
|
theRegisters(1)(31 downto 16) <= datain;
|
| 2301 |
|
|
if opcode108 /= 1 then
|
| 2302 |
|
|
if LDMread(opcode108) /= '1' then
|
| 2303 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 2304 |
|
|
end if;
|
| 2305 |
|
|
end if;
|
| 2306 |
|
|
addrMux <= ADDR_PC;
|
| 2307 |
|
|
cpuState <= STATE_FETCH;
|
| 2308 |
|
|
else
|
| 2309 |
|
|
theRegisters(1)(31 downto 16) <= datain;
|
| 2310 |
|
|
if opcode(2) = '1' then
|
| 2311 |
|
|
cpuState <= STATE_RD2L;
|
| 2312 |
|
|
elsif opcode(3) = '1' then
|
| 2313 |
|
|
cpuState <= STATE_RD3L;
|
| 2314 |
|
|
elsif opcode(4) = '1' then
|
| 2315 |
|
|
cpuState <= STATE_RD4L;
|
| 2316 |
|
|
elsif opcode(5) = '1' then
|
| 2317 |
|
|
cpuState <= STATE_RD5L;
|
| 2318 |
|
|
elsif opcode(6) = '1' then
|
| 2319 |
|
|
cpuState <= STATE_RD6L;
|
| 2320 |
|
|
else
|
| 2321 |
|
|
cpuState <= STATE_RD7L;
|
| 2322 |
|
|
end if;
|
| 2323 |
|
|
end if;
|
| 2324 |
|
|
|
| 2325 |
|
|
when others =>
|
| 2326 |
|
|
cpuState <= STATE_FETCH;
|
| 2327 |
|
|
end case; -- unitControl2
|
| 2328 |
|
|
|
| 2329 |
|
|
when STATE_RD2L => -- ##################################################
|
| 2330 |
|
|
case unitControl2 is
|
| 2331 |
|
|
when CODE_POP1 =>
|
| 2332 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2333 |
|
|
theRegisters(2)(15 downto 0) <= datain;
|
| 2334 |
|
|
cpuState <= STATE_RD2H;
|
| 2335 |
|
|
when CODE_LDMIA1 =>
|
| 2336 |
|
|
LDMread(2) <= '1';
|
| 2337 |
|
|
theRegisters(2)(15 downto 0) <= datain;
|
| 2338 |
|
|
address <= address + 2;
|
| 2339 |
|
|
cpuState <= STATE_RD2H;
|
| 2340 |
|
|
|
| 2341 |
|
|
when others =>
|
| 2342 |
|
|
cpuState <= STATE_FETCH;
|
| 2343 |
|
|
end case; -- unitControl2
|
| 2344 |
|
|
|
| 2345 |
|
|
when STATE_RD2H => -- ##################################################
|
| 2346 |
|
|
case unitControl2 is
|
| 2347 |
|
|
when CODE_POP1 =>
|
| 2348 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2349 |
|
|
theRegisters(2)(31 downto 16) <= datain;
|
| 2350 |
|
|
if opcode(8 downto 3) = 0 then
|
| 2351 |
|
|
addrMux <= ADDR_PC;
|
| 2352 |
|
|
cpuState <= STATE_FETCH;
|
| 2353 |
|
|
else
|
| 2354 |
|
|
if opcode(3) = '1' then
|
| 2355 |
|
|
cpuState <= STATE_RD3L;
|
| 2356 |
|
|
elsif opcode(4) = '1' then
|
| 2357 |
|
|
cpuState <= STATE_RD4L;
|
| 2358 |
|
|
elsif opcode(5) = '1' then
|
| 2359 |
|
|
cpuState <= STATE_RD5L;
|
| 2360 |
|
|
elsif opcode(6) = '1' then
|
| 2361 |
|
|
cpuState <= STATE_RD6L;
|
| 2362 |
|
|
elsif opcode(7) = '1' then
|
| 2363 |
|
|
cpuState <= STATE_RD7L;
|
| 2364 |
|
|
else
|
| 2365 |
|
|
cpuState <= STATE_RDPL;
|
| 2366 |
|
|
end if;
|
| 2367 |
|
|
end if;
|
| 2368 |
|
|
when CODE_LDMIA1 =>
|
| 2369 |
|
|
address <= address + 2;
|
| 2370 |
|
|
if opcode(7 downto 3) = 0 then
|
| 2371 |
|
|
addrMux <= ADDR_PC;
|
| 2372 |
|
|
theRegisters(2)(31 downto 16) <= datain;
|
| 2373 |
|
|
if opcode108 /= 2 then
|
| 2374 |
|
|
if LDMread(opcode108) /= '1' then
|
| 2375 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 2376 |
|
|
end if;
|
| 2377 |
|
|
end if;
|
| 2378 |
|
|
cpuState <= STATE_FETCH;
|
| 2379 |
|
|
else
|
| 2380 |
|
|
theRegisters(2)(31 downto 16) <= datain;
|
| 2381 |
|
|
if opcode(3) = '1' then
|
| 2382 |
|
|
cpuState <= STATE_RD3L;
|
| 2383 |
|
|
elsif opcode(4) = '1' then
|
| 2384 |
|
|
cpuState <= STATE_RD4L;
|
| 2385 |
|
|
elsif opcode(5) = '1' then
|
| 2386 |
|
|
cpuState <= STATE_RD5L;
|
| 2387 |
|
|
elsif opcode(6) = '1' then
|
| 2388 |
|
|
cpuState <= STATE_RD6L;
|
| 2389 |
|
|
else
|
| 2390 |
|
|
cpuState <= STATE_RD7L;
|
| 2391 |
|
|
end if;
|
| 2392 |
|
|
end if;
|
| 2393 |
|
|
|
| 2394 |
|
|
when others =>
|
| 2395 |
|
|
cpuState <= STATE_FETCH;
|
| 2396 |
|
|
end case; -- unitControl2
|
| 2397 |
|
|
|
| 2398 |
|
|
when STATE_RD3L => -- ##################################################
|
| 2399 |
|
|
case unitControl2 is
|
| 2400 |
|
|
when CODE_POP1 =>
|
| 2401 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2402 |
|
|
theRegisters(3)(15 downto 0) <= datain;
|
| 2403 |
|
|
cpuState <= STATE_RD3H;
|
| 2404 |
|
|
when CODE_LDMIA1 =>
|
| 2405 |
|
|
LDMread(3) <= '1';
|
| 2406 |
|
|
theRegisters(3)(15 downto 0) <= datain;
|
| 2407 |
|
|
address <= address + 2;
|
| 2408 |
|
|
cpuState <= STATE_RD3H;
|
| 2409 |
|
|
|
| 2410 |
|
|
when others =>
|
| 2411 |
|
|
cpuState <= STATE_FETCH;
|
| 2412 |
|
|
end case; -- unitControl2
|
| 2413 |
|
|
|
| 2414 |
|
|
when STATE_RD3H => -- ##################################################
|
| 2415 |
|
|
case unitControl2 is
|
| 2416 |
|
|
when CODE_POP1 =>
|
| 2417 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2418 |
|
|
theRegisters(3)(31 downto 16) <= datain;
|
| 2419 |
|
|
if opcode(8 downto 4) = 0 then
|
| 2420 |
|
|
addrMux <= ADDR_PC;
|
| 2421 |
|
|
cpuState <= STATE_FETCH;
|
| 2422 |
|
|
else
|
| 2423 |
|
|
if opcode(4) = '1' then
|
| 2424 |
|
|
cpuState <= STATE_RD4L;
|
| 2425 |
|
|
elsif opcode(5) = '1' then
|
| 2426 |
|
|
cpuState <= STATE_RD5L;
|
| 2427 |
|
|
elsif opcode(6) = '1' then
|
| 2428 |
|
|
cpuState <= STATE_RD6L;
|
| 2429 |
|
|
elsif opcode(7) = '1' then
|
| 2430 |
|
|
cpuState <= STATE_RD7L;
|
| 2431 |
|
|
else
|
| 2432 |
|
|
cpuState <= STATE_RDPL;
|
| 2433 |
|
|
end if;
|
| 2434 |
|
|
end if;
|
| 2435 |
|
|
when CODE_LDMIA1 =>
|
| 2436 |
|
|
address <= address + 2;
|
| 2437 |
|
|
if opcode(7 downto 4) = 0 then
|
| 2438 |
|
|
addrMux <= ADDR_PC;
|
| 2439 |
|
|
theRegisters(3)(31 downto 16) <= datain;
|
| 2440 |
|
|
if opcode108 /= 3 then
|
| 2441 |
|
|
if LDMread(opcode108) /= '1' then
|
| 2442 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 2443 |
|
|
end if;
|
| 2444 |
|
|
end if;
|
| 2445 |
|
|
cpuState <= STATE_FETCH;
|
| 2446 |
|
|
else
|
| 2447 |
|
|
theRegisters(3)(31 downto 16) <= datain;
|
| 2448 |
|
|
if opcode(4) = '1' then
|
| 2449 |
|
|
cpuState <= STATE_RD4L;
|
| 2450 |
|
|
elsif opcode(5) = '1' then
|
| 2451 |
|
|
cpuState <= STATE_RD5L;
|
| 2452 |
|
|
elsif opcode(6) = '1' then
|
| 2453 |
|
|
cpuState <= STATE_RD6L;
|
| 2454 |
|
|
else
|
| 2455 |
|
|
cpuState <= STATE_RD7L;
|
| 2456 |
|
|
end if;
|
| 2457 |
|
|
end if;
|
| 2458 |
|
|
|
| 2459 |
|
|
when others =>
|
| 2460 |
|
|
cpuState <= STATE_FETCH;
|
| 2461 |
|
|
end case; -- unitControl2
|
| 2462 |
|
|
|
| 2463 |
|
|
when STATE_RD4L => -- ##################################################
|
| 2464 |
|
|
case unitControl2 is
|
| 2465 |
|
|
when CODE_POP1 =>
|
| 2466 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2467 |
|
|
theRegisters(4)(15 downto 0) <= datain;
|
| 2468 |
|
|
cpuState <= STATE_RD4H;
|
| 2469 |
|
|
when CODE_LDMIA1 =>
|
| 2470 |
|
|
LDMread(4) <= '1';
|
| 2471 |
|
|
theRegisters(4)(15 downto 0) <= datain;
|
| 2472 |
|
|
address <= address + 2;
|
| 2473 |
|
|
cpuState <= STATE_RD4H;
|
| 2474 |
|
|
|
| 2475 |
|
|
when others =>
|
| 2476 |
|
|
cpuState <= STATE_FETCH;
|
| 2477 |
|
|
end case; -- unitControl2
|
| 2478 |
|
|
|
| 2479 |
|
|
when STATE_RD4H => -- ##################################################
|
| 2480 |
|
|
case unitControl2 is
|
| 2481 |
|
|
when CODE_POP1 =>
|
| 2482 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2483 |
|
|
theRegisters(4)(31 downto 16) <= datain;
|
| 2484 |
|
|
if opcode(8 downto 5) = 0 then
|
| 2485 |
|
|
addrMux <= ADDR_PC;
|
| 2486 |
|
|
cpuState <= STATE_FETCH;
|
| 2487 |
|
|
else
|
| 2488 |
|
|
if opcode(5) = '1' then
|
| 2489 |
|
|
cpuState <= STATE_RD5L;
|
| 2490 |
|
|
elsif opcode(6) = '1' then
|
| 2491 |
|
|
cpuState <= STATE_RD6L;
|
| 2492 |
|
|
elsif opcode(7) = '1' then
|
| 2493 |
|
|
cpuState <= STATE_RD7L;
|
| 2494 |
|
|
else
|
| 2495 |
|
|
cpuState <= STATE_RDPL;
|
| 2496 |
|
|
end if;
|
| 2497 |
|
|
end if;
|
| 2498 |
|
|
when CODE_LDMIA1 =>
|
| 2499 |
|
|
address <= address + 2;
|
| 2500 |
|
|
if opcode(7 downto 5) = 0 then
|
| 2501 |
|
|
addrMux <= ADDR_PC;
|
| 2502 |
|
|
theRegisters(4)(31 downto 16) <= datain;
|
| 2503 |
|
|
if opcode108 /= 4 then
|
| 2504 |
|
|
if LDMread(opcode108) /= '1' then
|
| 2505 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 2506 |
|
|
end if;
|
| 2507 |
|
|
end if;
|
| 2508 |
|
|
cpuState <= STATE_FETCH;
|
| 2509 |
|
|
else
|
| 2510 |
|
|
theRegisters(4)(31 downto 16) <= datain;
|
| 2511 |
|
|
if opcode(5) = '1' then
|
| 2512 |
|
|
cpuState <= STATE_RD5L;
|
| 2513 |
|
|
elsif opcode(6) = '1' then
|
| 2514 |
|
|
cpuState <= STATE_RD6L;
|
| 2515 |
|
|
else
|
| 2516 |
|
|
cpuState <= STATE_RD7L;
|
| 2517 |
|
|
end if;
|
| 2518 |
|
|
end if;
|
| 2519 |
|
|
|
| 2520 |
|
|
when others =>
|
| 2521 |
|
|
cpuState <= STATE_FETCH;
|
| 2522 |
|
|
end case; -- unitControl2
|
| 2523 |
|
|
|
| 2524 |
|
|
when STATE_RD5L => -- ##################################################
|
| 2525 |
|
|
case unitControl2 is
|
| 2526 |
|
|
when CODE_POP1 =>
|
| 2527 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2528 |
|
|
theRegisters(5)(15 downto 0) <= datain;
|
| 2529 |
|
|
cpuState <= STATE_RD5H;
|
| 2530 |
|
|
when CODE_LDMIA1 =>
|
| 2531 |
|
|
LDMread(5) <= '1';
|
| 2532 |
|
|
theRegisters(5)(15 downto 0) <= datain;
|
| 2533 |
|
|
address <= address + 2;
|
| 2534 |
|
|
cpuState <= STATE_RD5H;
|
| 2535 |
|
|
|
| 2536 |
|
|
when others =>
|
| 2537 |
|
|
cpuState <= STATE_FETCH;
|
| 2538 |
|
|
end case; -- unitControl2
|
| 2539 |
|
|
|
| 2540 |
|
|
when STATE_RD5H => -- ##################################################
|
| 2541 |
|
|
case unitControl2 is
|
| 2542 |
|
|
when CODE_POP1 =>
|
| 2543 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2544 |
|
|
theRegisters(5)(31 downto 16) <= datain;
|
| 2545 |
|
|
if opcode(8 downto 6) = 0 then
|
| 2546 |
|
|
addrMux <= ADDR_PC;
|
| 2547 |
|
|
cpuState <= STATE_FETCH;
|
| 2548 |
|
|
else
|
| 2549 |
|
|
if opcode(6) = '1' then
|
| 2550 |
|
|
cpuState <= STATE_RD6L;
|
| 2551 |
|
|
elsif opcode(7) = '1' then
|
| 2552 |
|
|
cpuState <= STATE_RD7L;
|
| 2553 |
|
|
else
|
| 2554 |
|
|
cpuState <= STATE_RDPL;
|
| 2555 |
|
|
end if;
|
| 2556 |
|
|
end if;
|
| 2557 |
|
|
when CODE_LDMIA1 =>
|
| 2558 |
|
|
address <= address + 2;
|
| 2559 |
|
|
if opcode(7 downto 6) = 0 then
|
| 2560 |
|
|
addrMux <= ADDR_PC;
|
| 2561 |
|
|
theRegisters(5)(31 downto 16) <= datain;
|
| 2562 |
|
|
if opcode108 /= 5 then
|
| 2563 |
|
|
if LDMread(opcode108) /= '1' then
|
| 2564 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 2565 |
|
|
end if;
|
| 2566 |
|
|
end if;
|
| 2567 |
|
|
cpuState <= STATE_FETCH;
|
| 2568 |
|
|
else
|
| 2569 |
|
|
theRegisters(5)(31 downto 16) <= datain;
|
| 2570 |
|
|
if opcode(6) = '1' then
|
| 2571 |
|
|
cpuState <= STATE_RD6L;
|
| 2572 |
|
|
else
|
| 2573 |
|
|
cpuState <= STATE_RD7L;
|
| 2574 |
|
|
end if;
|
| 2575 |
|
|
end if;
|
| 2576 |
|
|
|
| 2577 |
|
|
when others =>
|
| 2578 |
|
|
cpuState <= STATE_FETCH;
|
| 2579 |
|
|
end case; -- unitControl2
|
| 2580 |
|
|
|
| 2581 |
|
|
when STATE_RD6L => -- ##################################################
|
| 2582 |
|
|
case unitControl2 is
|
| 2583 |
|
|
when CODE_POP1 =>
|
| 2584 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2585 |
|
|
theRegisters(6)(15 downto 0) <= datain;
|
| 2586 |
|
|
cpuState <= STATE_RD6H;
|
| 2587 |
|
|
when CODE_LDMIA1 =>
|
| 2588 |
|
|
LDMread(7) <= '1';
|
| 2589 |
|
|
theRegisters(6)(15 downto 0) <= datain;
|
| 2590 |
|
|
address <= address + 2;
|
| 2591 |
|
|
cpuState <= STATE_RD6H;
|
| 2592 |
|
|
|
| 2593 |
|
|
when others =>
|
| 2594 |
|
|
cpuState <= STATE_FETCH;
|
| 2595 |
|
|
end case; -- unitControl2
|
| 2596 |
|
|
|
| 2597 |
|
|
when STATE_RD6H => -- ##################################################
|
| 2598 |
|
|
case unitControl2 is
|
| 2599 |
|
|
when CODE_POP1 =>
|
| 2600 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2601 |
|
|
theRegisters(6)(31 downto 16) <= datain;
|
| 2602 |
|
|
if opcode(8 downto 7) = 0 then
|
| 2603 |
|
|
addrMux <= ADDR_PC;
|
| 2604 |
|
|
cpuState <= STATE_FETCH;
|
| 2605 |
|
|
else
|
| 2606 |
|
|
if opcode(7) = '1' then
|
| 2607 |
|
|
cpuState <= STATE_RD7L;
|
| 2608 |
|
|
else
|
| 2609 |
|
|
cpuState <= STATE_RDPL;
|
| 2610 |
|
|
end if;
|
| 2611 |
|
|
end if;
|
| 2612 |
|
|
when CODE_LDMIA1 =>
|
| 2613 |
|
|
address <= address + 2;
|
| 2614 |
|
|
if opcode(7) = '0' then
|
| 2615 |
|
|
addrMux <= ADDR_PC;
|
| 2616 |
|
|
theRegisters(6)(31 downto 16) <= datain;
|
| 2617 |
|
|
if opcode108 /= 6 then
|
| 2618 |
|
|
if LDMread(opcode108) /= '1' then
|
| 2619 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 2620 |
|
|
end if;
|
| 2621 |
|
|
end if;
|
| 2622 |
|
|
cpuState <= STATE_FETCH;
|
| 2623 |
|
|
else
|
| 2624 |
|
|
theRegisters(6)(31 downto 16) <= datain;
|
| 2625 |
|
|
cpuState <= STATE_RD7L;
|
| 2626 |
|
|
end if;
|
| 2627 |
|
|
|
| 2628 |
|
|
when others =>
|
| 2629 |
|
|
cpuState <= STATE_FETCH;
|
| 2630 |
|
|
end case; -- unitControl2
|
| 2631 |
|
|
|
| 2632 |
|
|
when STATE_RD7L => -- ##################################################
|
| 2633 |
|
|
case unitControl2 is
|
| 2634 |
|
|
when CODE_POP1 =>
|
| 2635 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2636 |
|
|
theRegisters(7)(15 downto 0) <= datain;
|
| 2637 |
|
|
cpuState <= STATE_RD7H;
|
| 2638 |
|
|
when CODE_LDMIA1 =>
|
| 2639 |
|
|
LDMread(7) <= '1';
|
| 2640 |
|
|
theRegisters(7)(15 downto 0) <= datain;
|
| 2641 |
|
|
address <= address + 2;
|
| 2642 |
|
|
cpuState <= STATE_RD7H;
|
| 2643 |
|
|
|
| 2644 |
|
|
when others =>
|
| 2645 |
|
|
cpuState <= STATE_FETCH;
|
| 2646 |
|
|
end case; -- unitControl2
|
| 2647 |
|
|
|
| 2648 |
|
|
when STATE_RD7H => -- ##################################################
|
| 2649 |
|
|
case unitControl2 is
|
| 2650 |
|
|
when CODE_POP1 =>
|
| 2651 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2652 |
|
|
theRegisters(7)(31 downto 16) <= datain;
|
| 2653 |
|
|
if opcode(8) = '0' then
|
| 2654 |
|
|
addrMux <= ADDR_PC;
|
| 2655 |
|
|
cpuState <= STATE_FETCH;
|
| 2656 |
|
|
else
|
| 2657 |
|
|
cpuState <= STATE_RDPL;
|
| 2658 |
|
|
end if;
|
| 2659 |
|
|
when CODE_LDMIA1 =>
|
| 2660 |
|
|
address <= address + 2;
|
| 2661 |
|
|
theRegisters(7)(31 downto 16) <= datain;
|
| 2662 |
|
|
if opcode108 /= 7 then
|
| 2663 |
|
|
if LDMread(opcode108) /= '1' then
|
| 2664 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 2665 |
|
|
end if;
|
| 2666 |
|
|
end if;
|
| 2667 |
|
|
addrMux <= ADDR_PC;
|
| 2668 |
|
|
cpuState <= STATE_FETCH;
|
| 2669 |
|
|
|
| 2670 |
|
|
when others =>
|
| 2671 |
|
|
cpuState <= STATE_FETCH;
|
| 2672 |
|
|
end case; -- unitControl2
|
| 2673 |
|
|
|
| 2674 |
|
|
when STATE_RDPL => -- ##################################################
|
| 2675 |
|
|
case unitControl2 is
|
| 2676 |
|
|
when CODE_POP1 =>
|
| 2677 |
|
|
if theRegisters(14) = x"FFFFFFF9" then
|
| 2678 |
|
|
cpuState <= STATE_RET;
|
| 2679 |
|
|
else
|
| 2680 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2681 |
|
|
theRegisters(15)(15 downto 0) <= datain;
|
| 2682 |
|
|
cpuState <= STATE_RDPH;
|
| 2683 |
|
|
end if;
|
| 2684 |
|
|
when others =>
|
| 2685 |
|
|
cpuState <= STATE_FETCH;
|
| 2686 |
|
|
end case; -- unitControl2
|
| 2687 |
|
|
|
| 2688 |
|
|
when STATE_RDPH => -- ##################################################
|
| 2689 |
|
|
case unitControl2 is
|
| 2690 |
|
|
when CODE_POP1 =>
|
| 2691 |
|
|
theRegisters(13) <= theRegisters(13) + 2;
|
| 2692 |
|
|
theRegisters(15)(31 downto 16) <= datain;
|
| 2693 |
|
|
addrMux <= ADDR_PC;
|
| 2694 |
|
|
cpuState <= STATE_FETCH;
|
| 2695 |
|
|
when others =>
|
| 2696 |
|
|
cpuState <= STATE_FETCH;
|
| 2697 |
|
|
end case; -- unitControl2
|
| 2698 |
|
|
|
| 2699 |
|
|
|
| 2700 |
|
|
|
| 2701 |
|
|
when STATE_WRITE1 => -- ##################################################
|
| 2702 |
|
|
case unitControl2 is
|
| 2703 |
|
|
when CODE_STR1 | CODE_STR2 =>
|
| 2704 |
|
|
address <= address + 2;
|
| 2705 |
|
|
dataout <= theRegisters(opcode20)(31 downto 16);
|
| 2706 |
|
|
cpuState <= STATE_WRITE2;
|
| 2707 |
|
|
when CODE_STRH1 | CODE_STRB1 | CODE_STRB2 | CODE_STRH2 =>
|
| 2708 |
|
|
addrMux <= ADDR_PC;
|
| 2709 |
|
|
writeL <= '1';
|
| 2710 |
|
|
writeH <= '1';
|
| 2711 |
|
|
cpuState <= STATE_FETCH;
|
| 2712 |
|
|
when CODE_STR3 =>
|
| 2713 |
|
|
address <= address + 2;
|
| 2714 |
|
|
dataout <= theRegisters(opcode108)(31 downto 16);
|
| 2715 |
|
|
cpuState <= STATE_WRITE2;
|
| 2716 |
|
|
|
| 2717 |
|
|
when others =>
|
| 2718 |
|
|
cpuState <= STATE_FETCH;
|
| 2719 |
|
|
end case; -- unitControl2
|
| 2720 |
|
|
|
| 2721 |
|
|
when STATE_WRITE2 => -- ##################################################
|
| 2722 |
|
|
case unitControl2 is
|
| 2723 |
|
|
when CODE_STR1 | CODE_STR2 | CODE_STR3 =>
|
| 2724 |
|
|
addrMux <= ADDR_PC;
|
| 2725 |
|
|
writeL <= '1';
|
| 2726 |
|
|
writeH <= '1';
|
| 2727 |
|
|
cpuState <= STATE_FETCH;
|
| 2728 |
|
|
|
| 2729 |
|
|
when others =>
|
| 2730 |
|
|
cpuState <= STATE_FETCH;
|
| 2731 |
|
|
end case; -- unitControl2
|
| 2732 |
|
|
|
| 2733 |
|
|
when STATE_WRPH => -- ##################################################
|
| 2734 |
|
|
case unitControl2 is
|
| 2735 |
|
|
when CODE_PUSH1 =>
|
| 2736 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 2737 |
|
|
dataout <= theRegisters(14)(15 downto 0);
|
| 2738 |
|
|
cpuState <= STATE_WRPL;
|
| 2739 |
|
|
|
| 2740 |
|
|
when others =>
|
| 2741 |
|
|
writeL <= '1';
|
| 2742 |
|
|
writeH <= '1';
|
| 2743 |
|
|
cpuState <= STATE_FETCH;
|
| 2744 |
|
|
end case; -- unitControl2
|
| 2745 |
|
|
|
| 2746 |
|
|
when STATE_WRPL => -- ##################################################
|
| 2747 |
|
|
case unitControl2 is
|
| 2748 |
|
|
when CODE_PUSH1 =>
|
| 2749 |
|
|
if opcode(7 downto 0) = 0 then
|
| 2750 |
|
|
writeL <= '1';
|
| 2751 |
|
|
writeH <= '1';
|
| 2752 |
|
|
addrMux <= ADDR_PC;
|
| 2753 |
|
|
cpuState <= STATE_FETCH;
|
| 2754 |
|
|
else
|
| 2755 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 2756 |
|
|
if opcode(7) = '1' then
|
| 2757 |
|
|
dataout <= theRegisters(7)(31 downto 16);
|
| 2758 |
|
|
cpuState <= STATE_WR7H;
|
| 2759 |
|
|
elsif opcode(6) = '1' then
|
| 2760 |
|
|
dataout <= theRegisters(6)(31 downto 16);
|
| 2761 |
|
|
cpuState <= STATE_WR6H;
|
| 2762 |
|
|
elsif opcode(5) = '1' then
|
| 2763 |
|
|
dataout <= theRegisters(5)(31 downto 16);
|
| 2764 |
|
|
cpuState <= STATE_WR5H;
|
| 2765 |
|
|
elsif opcode(4) = '1' then
|
| 2766 |
|
|
dataout <= theRegisters(4)(31 downto 16);
|
| 2767 |
|
|
cpuState <= STATE_WR4H;
|
| 2768 |
|
|
elsif opcode(3) = '1' then
|
| 2769 |
|
|
dataout <= theRegisters(3)(31 downto 16);
|
| 2770 |
|
|
cpuState <= STATE_WR3H;
|
| 2771 |
|
|
elsif opcode(2) = '1' then
|
| 2772 |
|
|
dataout <= theRegisters(2)(31 downto 16);
|
| 2773 |
|
|
cpuState <= STATE_WR2H;
|
| 2774 |
|
|
elsif opcode(1) = '1' then
|
| 2775 |
|
|
dataout <= theRegisters(1)(31 downto 16);
|
| 2776 |
|
|
cpuState <= STATE_WR1H;
|
| 2777 |
|
|
else
|
| 2778 |
|
|
dataout <= theRegisters(0)(31 downto 16);
|
| 2779 |
|
|
cpuState <= STATE_WR0H;
|
| 2780 |
|
|
end if;
|
| 2781 |
|
|
end if;
|
| 2782 |
|
|
|
| 2783 |
|
|
when others =>
|
| 2784 |
|
|
writeL <= '1';
|
| 2785 |
|
|
writeH <= '1';
|
| 2786 |
|
|
cpuState <= STATE_FETCH;
|
| 2787 |
|
|
end case; -- unitControl2
|
| 2788 |
|
|
|
| 2789 |
|
|
when STATE_WR7H => -- ##################################################
|
| 2790 |
|
|
case unitControl2 is
|
| 2791 |
|
|
when CODE_PUSH1 =>
|
| 2792 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 2793 |
|
|
dataout <= theRegisters(7)(15 downto 0);
|
| 2794 |
|
|
cpuState <= STATE_WR7L;
|
| 2795 |
|
|
when CODE_STMIA1 =>
|
| 2796 |
|
|
address <= address + 2;
|
| 2797 |
|
|
dataout <= theRegisters(7)(31 downto 16);
|
| 2798 |
|
|
cpuState <= STATE_WR7L;
|
| 2799 |
|
|
|
| 2800 |
|
|
when others =>
|
| 2801 |
|
|
writeL <= '1';
|
| 2802 |
|
|
writeH <= '1';
|
| 2803 |
|
|
cpuState <= STATE_FETCH;
|
| 2804 |
|
|
end case; -- unitControl2
|
| 2805 |
|
|
|
| 2806 |
|
|
when STATE_WR7L => -- ##################################################
|
| 2807 |
|
|
case unitControl2 is
|
| 2808 |
|
|
when CODE_PUSH1 =>
|
| 2809 |
|
|
if opcode(6 downto 0) = 0 then
|
| 2810 |
|
|
writeL <= '1';
|
| 2811 |
|
|
writeH <= '1';
|
| 2812 |
|
|
addrMux <= ADDR_PC;
|
| 2813 |
|
|
cpuState <= STATE_FETCH;
|
| 2814 |
|
|
else
|
| 2815 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 2816 |
|
|
if opcode(6) = '1' then
|
| 2817 |
|
|
dataout <= theRegisters(6)(31 downto 16);
|
| 2818 |
|
|
cpuState <= STATE_WR6H;
|
| 2819 |
|
|
elsif opcode(5) = '1' then
|
| 2820 |
|
|
dataout <= theRegisters(5)(31 downto 16);
|
| 2821 |
|
|
cpuState <= STATE_WR5H;
|
| 2822 |
|
|
elsif opcode(4) = '1' then
|
| 2823 |
|
|
dataout <= theRegisters(4)(31 downto 16);
|
| 2824 |
|
|
cpuState <= STATE_WR4H;
|
| 2825 |
|
|
elsif opcode(3) = '1' then
|
| 2826 |
|
|
dataout <= theRegisters(3)(31 downto 16);
|
| 2827 |
|
|
cpuState <= STATE_WR3H;
|
| 2828 |
|
|
elsif opcode(2) = '1' then
|
| 2829 |
|
|
dataout <= theRegisters(2)(31 downto 16);
|
| 2830 |
|
|
cpuState <= STATE_WR2H;
|
| 2831 |
|
|
elsif opcode(1) = '1' then
|
| 2832 |
|
|
dataout <= theRegisters(1)(31 downto 16);
|
| 2833 |
|
|
cpuState <= STATE_WR1H;
|
| 2834 |
|
|
else
|
| 2835 |
|
|
dataout <= theRegisters(0)(31 downto 16);
|
| 2836 |
|
|
cpuState <= STATE_WR0H;
|
| 2837 |
|
|
end if;
|
| 2838 |
|
|
end if;
|
| 2839 |
|
|
when CODE_STMIA1 =>
|
| 2840 |
|
|
address <= address + 2;
|
| 2841 |
|
|
writeL <= '1';
|
| 2842 |
|
|
writeH <= '1';
|
| 2843 |
|
|
addrMux <= ADDR_PC;
|
| 2844 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 2845 |
|
|
cpuState <= STATE_FETCH;
|
| 2846 |
|
|
|
| 2847 |
|
|
when others =>
|
| 2848 |
|
|
writeL <= '1';
|
| 2849 |
|
|
writeH <= '1';
|
| 2850 |
|
|
cpuState <= STATE_FETCH;
|
| 2851 |
|
|
end case; -- unitControl2
|
| 2852 |
|
|
|
| 2853 |
|
|
when STATE_WR6H => -- ##################################################
|
| 2854 |
|
|
case unitControl2 is
|
| 2855 |
|
|
when CODE_PUSH1 =>
|
| 2856 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 2857 |
|
|
dataout <= theRegisters(6)(15 downto 0);
|
| 2858 |
|
|
cpuState <= STATE_WR6L;
|
| 2859 |
|
|
when CODE_STMIA1 =>
|
| 2860 |
|
|
address <= address + 2;
|
| 2861 |
|
|
dataout <= theRegisters(6)(31 downto 16);
|
| 2862 |
|
|
cpuState <= STATE_WR6L;
|
| 2863 |
|
|
|
| 2864 |
|
|
when others =>
|
| 2865 |
|
|
writeL <= '1';
|
| 2866 |
|
|
writeH <= '1';
|
| 2867 |
|
|
cpuState <= STATE_FETCH;
|
| 2868 |
|
|
end case; -- unitControl2
|
| 2869 |
|
|
|
| 2870 |
|
|
when STATE_WR6L => -- ##################################################
|
| 2871 |
|
|
case unitControl2 is
|
| 2872 |
|
|
when CODE_PUSH1 =>
|
| 2873 |
|
|
if opcode(5 downto 0) = 0 then
|
| 2874 |
|
|
writeL <= '1';
|
| 2875 |
|
|
writeH <= '1';
|
| 2876 |
|
|
addrMux <= ADDR_PC;
|
| 2877 |
|
|
cpuState <= STATE_FETCH;
|
| 2878 |
|
|
else
|
| 2879 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 2880 |
|
|
if opcode(5) = '1' then
|
| 2881 |
|
|
dataout <= theRegisters(5)(31 downto 16);
|
| 2882 |
|
|
cpuState <= STATE_WR5H;
|
| 2883 |
|
|
elsif opcode(4) = '1' then
|
| 2884 |
|
|
dataout <= theRegisters(4)(31 downto 16);
|
| 2885 |
|
|
cpuState <= STATE_WR4H;
|
| 2886 |
|
|
elsif opcode(3) = '1' then
|
| 2887 |
|
|
dataout <= theRegisters(3)(31 downto 16);
|
| 2888 |
|
|
cpuState <= STATE_WR3H;
|
| 2889 |
|
|
elsif opcode(2) = '1' then
|
| 2890 |
|
|
dataout <= theRegisters(2)(31 downto 16);
|
| 2891 |
|
|
cpuState <= STATE_WR2H;
|
| 2892 |
|
|
elsif opcode(1) = '1' then
|
| 2893 |
|
|
dataout <= theRegisters(1)(31 downto 16);
|
| 2894 |
|
|
cpuState <= STATE_WR1H;
|
| 2895 |
|
|
else
|
| 2896 |
|
|
dataout <= theRegisters(0)(31 downto 16);
|
| 2897 |
|
|
cpuState <= STATE_WR0H;
|
| 2898 |
|
|
end if;
|
| 2899 |
|
|
end if;
|
| 2900 |
|
|
when CODE_STMIA1 =>
|
| 2901 |
|
|
address <= address + 2;
|
| 2902 |
|
|
if opcode(7) = '0' then
|
| 2903 |
|
|
writeL <= '1';
|
| 2904 |
|
|
writeH <= '1';
|
| 2905 |
|
|
addrMux <= ADDR_PC;
|
| 2906 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 2907 |
|
|
cpuState <= STATE_FETCH;
|
| 2908 |
|
|
else
|
| 2909 |
|
|
dataout <= theRegisters(7)(15 downto 0);
|
| 2910 |
|
|
cpuState <= STATE_WR7H;
|
| 2911 |
|
|
end if;
|
| 2912 |
|
|
|
| 2913 |
|
|
when others =>
|
| 2914 |
|
|
writeL <= '1';
|
| 2915 |
|
|
writeH <= '1';
|
| 2916 |
|
|
cpuState <= STATE_FETCH;
|
| 2917 |
|
|
end case; -- unitControl2
|
| 2918 |
|
|
|
| 2919 |
|
|
when STATE_WR5H => -- ##################################################
|
| 2920 |
|
|
case unitControl2 is
|
| 2921 |
|
|
when CODE_PUSH1 =>
|
| 2922 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 2923 |
|
|
dataout <= theRegisters(5)(15 downto 0);
|
| 2924 |
|
|
cpuState <= STATE_WR5L;
|
| 2925 |
|
|
when CODE_STMIA1 =>
|
| 2926 |
|
|
address <= address + 2;
|
| 2927 |
|
|
dataout <= theRegisters(5)(31 downto 16);
|
| 2928 |
|
|
cpuState <= STATE_WR5L;
|
| 2929 |
|
|
|
| 2930 |
|
|
when others =>
|
| 2931 |
|
|
writeL <= '1';
|
| 2932 |
|
|
writeH <= '1';
|
| 2933 |
|
|
cpuState <= STATE_FETCH;
|
| 2934 |
|
|
end case; -- unitControl2
|
| 2935 |
|
|
|
| 2936 |
|
|
when STATE_WR5L => -- ##################################################
|
| 2937 |
|
|
case unitControl2 is
|
| 2938 |
|
|
when CODE_PUSH1 =>
|
| 2939 |
|
|
if opcode(4 downto 0) = 0 then
|
| 2940 |
|
|
writeL <= '1';
|
| 2941 |
|
|
writeH <= '1';
|
| 2942 |
|
|
addrMux <= ADDR_PC;
|
| 2943 |
|
|
cpuState <= STATE_FETCH;
|
| 2944 |
|
|
else
|
| 2945 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 2946 |
|
|
if opcode(4) = '1' then
|
| 2947 |
|
|
dataout <= theRegisters(4)(31 downto 16);
|
| 2948 |
|
|
cpuState <= STATE_WR4H;
|
| 2949 |
|
|
elsif opcode(3) = '1' then
|
| 2950 |
|
|
dataout <= theRegisters(3)(31 downto 16);
|
| 2951 |
|
|
cpuState <= STATE_WR3H;
|
| 2952 |
|
|
elsif opcode(2) = '1' then
|
| 2953 |
|
|
dataout <= theRegisters(2)(31 downto 16);
|
| 2954 |
|
|
cpuState <= STATE_WR2H;
|
| 2955 |
|
|
elsif opcode(1) = '1' then
|
| 2956 |
|
|
dataout <= theRegisters(1)(31 downto 16);
|
| 2957 |
|
|
cpuState <= STATE_WR1H;
|
| 2958 |
|
|
else
|
| 2959 |
|
|
dataout <= theRegisters(0)(31 downto 16);
|
| 2960 |
|
|
cpuState <= STATE_WR0H;
|
| 2961 |
|
|
end if;
|
| 2962 |
|
|
end if;
|
| 2963 |
|
|
when CODE_STMIA1 =>
|
| 2964 |
|
|
address <= address + 2;
|
| 2965 |
|
|
if opcode(7 downto 6) = 0 then
|
| 2966 |
|
|
writeL <= '1';
|
| 2967 |
|
|
writeH <= '1';
|
| 2968 |
|
|
addrMux <= ADDR_PC;
|
| 2969 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 2970 |
|
|
cpuState <= STATE_FETCH;
|
| 2971 |
|
|
else
|
| 2972 |
|
|
if opcode(6) = '1' then
|
| 2973 |
|
|
dataout <= theRegisters(6)(15 downto 0);
|
| 2974 |
|
|
cpuState <= STATE_WR6H;
|
| 2975 |
|
|
else
|
| 2976 |
|
|
dataout <= theRegisters(7)(15 downto 0);
|
| 2977 |
|
|
cpuState <= STATE_WR7H;
|
| 2978 |
|
|
end if;
|
| 2979 |
|
|
end if;
|
| 2980 |
|
|
|
| 2981 |
|
|
when others =>
|
| 2982 |
|
|
writeL <= '1';
|
| 2983 |
|
|
writeH <= '1';
|
| 2984 |
|
|
cpuState <= STATE_FETCH;
|
| 2985 |
|
|
end case; -- unitControl2
|
| 2986 |
|
|
|
| 2987 |
|
|
when STATE_WR4H => -- ##################################################
|
| 2988 |
|
|
case unitControl2 is
|
| 2989 |
|
|
when CODE_PUSH1 =>
|
| 2990 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 2991 |
|
|
dataout <= theRegisters(4)(15 downto 0);
|
| 2992 |
|
|
cpuState <= STATE_WR4L;
|
| 2993 |
|
|
when CODE_STMIA1 =>
|
| 2994 |
|
|
address <= address + 2;
|
| 2995 |
|
|
dataout <= theRegisters(4)(31 downto 16);
|
| 2996 |
|
|
cpuState <= STATE_WR4L;
|
| 2997 |
|
|
|
| 2998 |
|
|
when others =>
|
| 2999 |
|
|
writeL <= '1';
|
| 3000 |
|
|
writeH <= '1';
|
| 3001 |
|
|
cpuState <= STATE_FETCH;
|
| 3002 |
|
|
end case; -- unitControl2
|
| 3003 |
|
|
|
| 3004 |
|
|
when STATE_WR4L => -- ##################################################
|
| 3005 |
|
|
case unitControl2 is
|
| 3006 |
|
|
when CODE_PUSH1 =>
|
| 3007 |
|
|
if opcode(3 downto 0) = 0 then
|
| 3008 |
|
|
writeL <= '1';
|
| 3009 |
|
|
writeH <= '1';
|
| 3010 |
|
|
addrMux <= ADDR_PC;
|
| 3011 |
|
|
cpuState <= STATE_FETCH;
|
| 3012 |
|
|
else
|
| 3013 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 3014 |
|
|
if opcode(3) = '1' then
|
| 3015 |
|
|
dataout <= theRegisters(3)(31 downto 16);
|
| 3016 |
|
|
cpuState <= STATE_WR3H;
|
| 3017 |
|
|
elsif opcode(2) = '1' then
|
| 3018 |
|
|
dataout <= theRegisters(2)(31 downto 16);
|
| 3019 |
|
|
cpuState <= STATE_WR2H;
|
| 3020 |
|
|
elsif opcode(1) = '1' then
|
| 3021 |
|
|
dataout <= theRegisters(1)(31 downto 16);
|
| 3022 |
|
|
cpuState <= STATE_WR1H;
|
| 3023 |
|
|
else
|
| 3024 |
|
|
dataout <= theRegisters(0)(31 downto 16);
|
| 3025 |
|
|
cpuState <= STATE_WR0H;
|
| 3026 |
|
|
end if;
|
| 3027 |
|
|
end if;
|
| 3028 |
|
|
when CODE_STMIA1 =>
|
| 3029 |
|
|
address <= address + 2;
|
| 3030 |
|
|
if opcode(7 downto 5) = 0 then
|
| 3031 |
|
|
writeL <= '1';
|
| 3032 |
|
|
writeH <= '1';
|
| 3033 |
|
|
addrMux <= ADDR_PC;
|
| 3034 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 3035 |
|
|
cpuState <= STATE_FETCH;
|
| 3036 |
|
|
else
|
| 3037 |
|
|
if opcode(5) = '1' then
|
| 3038 |
|
|
dataout <= theRegisters(5)(15 downto 0);
|
| 3039 |
|
|
cpuState <= STATE_WR5H;
|
| 3040 |
|
|
elsif opcode(6) = '1' then
|
| 3041 |
|
|
dataout <= theRegisters(6)(15 downto 0);
|
| 3042 |
|
|
cpuState <= STATE_WR6H;
|
| 3043 |
|
|
else
|
| 3044 |
|
|
dataout <= theRegisters(7)(15 downto 0);
|
| 3045 |
|
|
cpuState <= STATE_WR7H;
|
| 3046 |
|
|
end if;
|
| 3047 |
|
|
end if;
|
| 3048 |
|
|
|
| 3049 |
|
|
when others =>
|
| 3050 |
|
|
writeL <= '1';
|
| 3051 |
|
|
writeH <= '1';
|
| 3052 |
|
|
cpuState <= STATE_FETCH;
|
| 3053 |
|
|
end case; -- unitControl2
|
| 3054 |
|
|
|
| 3055 |
|
|
when STATE_WR3H => -- ##################################################
|
| 3056 |
|
|
case unitControl2 is
|
| 3057 |
|
|
when CODE_PUSH1 =>
|
| 3058 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 3059 |
|
|
dataout <= theRegisters(3)(15 downto 0);
|
| 3060 |
|
|
cpuState <= STATE_WR3L;
|
| 3061 |
|
|
when CODE_STMIA1 =>
|
| 3062 |
|
|
address <= address + 2;
|
| 3063 |
|
|
dataout <= theRegisters(3)(31 downto 16);
|
| 3064 |
|
|
cpuState <= STATE_WR3L;
|
| 3065 |
|
|
|
| 3066 |
|
|
when others =>
|
| 3067 |
|
|
writeL <= '1';
|
| 3068 |
|
|
writeH <= '1';
|
| 3069 |
|
|
cpuState <= STATE_FETCH;
|
| 3070 |
|
|
end case; -- unitControl2
|
| 3071 |
|
|
|
| 3072 |
|
|
when STATE_WR3L => -- ##################################################
|
| 3073 |
|
|
case unitControl2 is
|
| 3074 |
|
|
when CODE_PUSH1 =>
|
| 3075 |
|
|
if opcode(2 downto 0) = 0 then
|
| 3076 |
|
|
writeL <= '1';
|
| 3077 |
|
|
writeH <= '1';
|
| 3078 |
|
|
addrMux <= ADDR_PC;
|
| 3079 |
|
|
cpuState <= STATE_FETCH;
|
| 3080 |
|
|
else
|
| 3081 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 3082 |
|
|
if opcode(2) = '1' then
|
| 3083 |
|
|
dataout <= theRegisters(2)(31 downto 16);
|
| 3084 |
|
|
cpuState <= STATE_WR2H;
|
| 3085 |
|
|
elsif opcode(1) = '1' then
|
| 3086 |
|
|
dataout <= theRegisters(1)(31 downto 16);
|
| 3087 |
|
|
cpuState <= STATE_WR1H;
|
| 3088 |
|
|
else
|
| 3089 |
|
|
dataout <= theRegisters(0)(31 downto 16);
|
| 3090 |
|
|
cpuState <= STATE_WR0H;
|
| 3091 |
|
|
end if;
|
| 3092 |
|
|
end if;
|
| 3093 |
|
|
when CODE_STMIA1 =>
|
| 3094 |
|
|
address <= address + 2;
|
| 3095 |
|
|
if opcode(7 downto 4) = 0 then
|
| 3096 |
|
|
writeL <= '1';
|
| 3097 |
|
|
writeH <= '1';
|
| 3098 |
|
|
addrMux <= ADDR_PC;
|
| 3099 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 3100 |
|
|
cpuState <= STATE_FETCH;
|
| 3101 |
|
|
else
|
| 3102 |
|
|
if opcode(4) = '1' then
|
| 3103 |
|
|
dataout <= theRegisters(4)(15 downto 0);
|
| 3104 |
|
|
cpuState <= STATE_WR4H;
|
| 3105 |
|
|
elsif opcode(5) = '1' then
|
| 3106 |
|
|
dataout <= theRegisters(5)(15 downto 0);
|
| 3107 |
|
|
cpuState <= STATE_WR5H;
|
| 3108 |
|
|
elsif opcode(6) = '1' then
|
| 3109 |
|
|
dataout <= theRegisters(6)(15 downto 0);
|
| 3110 |
|
|
cpuState <= STATE_WR6H;
|
| 3111 |
|
|
else
|
| 3112 |
|
|
dataout <= theRegisters(7)(15 downto 0);
|
| 3113 |
|
|
cpuState <= STATE_WR7H;
|
| 3114 |
|
|
end if;
|
| 3115 |
|
|
end if;
|
| 3116 |
|
|
|
| 3117 |
|
|
when others =>
|
| 3118 |
|
|
writeL <= '1';
|
| 3119 |
|
|
writeH <= '1';
|
| 3120 |
|
|
cpuState <= STATE_FETCH;
|
| 3121 |
|
|
end case; -- unitControl2
|
| 3122 |
|
|
|
| 3123 |
|
|
when STATE_WR2H => -- ##################################################
|
| 3124 |
|
|
case unitControl2 is
|
| 3125 |
|
|
when CODE_PUSH1 =>
|
| 3126 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 3127 |
|
|
dataout <= theRegisters(2)(15 downto 0);
|
| 3128 |
|
|
cpuState <= STATE_WR2L;
|
| 3129 |
|
|
when CODE_STMIA1 =>
|
| 3130 |
|
|
address <= address + 2;
|
| 3131 |
|
|
dataout <= theRegisters(2)(31 downto 16);
|
| 3132 |
|
|
cpuState <= STATE_WR2L;
|
| 3133 |
|
|
|
| 3134 |
|
|
when others =>
|
| 3135 |
|
|
writeL <= '1';
|
| 3136 |
|
|
writeH <= '1';
|
| 3137 |
|
|
cpuState <= STATE_FETCH;
|
| 3138 |
|
|
end case; -- unitControl2
|
| 3139 |
|
|
|
| 3140 |
|
|
when STATE_WR2L => -- ##################################################
|
| 3141 |
|
|
case unitControl2 is
|
| 3142 |
|
|
when CODE_PUSH1 =>
|
| 3143 |
|
|
if opcode(1 downto 0) = 0 then
|
| 3144 |
|
|
writeL <= '1';
|
| 3145 |
|
|
writeH <= '1';
|
| 3146 |
|
|
addrMux <= ADDR_PC;
|
| 3147 |
|
|
cpuState <= STATE_FETCH;
|
| 3148 |
|
|
else
|
| 3149 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 3150 |
|
|
if opcode(1) = '1' then
|
| 3151 |
|
|
dataout <= theRegisters(1)(31 downto 16);
|
| 3152 |
|
|
cpuState <= STATE_WR1H;
|
| 3153 |
|
|
else
|
| 3154 |
|
|
dataout <= theRegisters(0)(31 downto 16);
|
| 3155 |
|
|
cpuState <= STATE_WR0H;
|
| 3156 |
|
|
end if;
|
| 3157 |
|
|
end if;
|
| 3158 |
|
|
when CODE_STMIA1 =>
|
| 3159 |
|
|
address <= address + 2;
|
| 3160 |
|
|
if opcode(7 downto 3) = 0 then
|
| 3161 |
|
|
writeL <= '1';
|
| 3162 |
|
|
writeH <= '1';
|
| 3163 |
|
|
addrMux <= ADDR_PC;
|
| 3164 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 3165 |
|
|
cpuState <= STATE_FETCH;
|
| 3166 |
|
|
else
|
| 3167 |
|
|
if opcode(3) = '1' then
|
| 3168 |
|
|
dataout <= theRegisters(3)(15 downto 0);
|
| 3169 |
|
|
cpuState <= STATE_WR3H;
|
| 3170 |
|
|
elsif opcode(4) = '1' then
|
| 3171 |
|
|
dataout <= theRegisters(4)(15 downto 0);
|
| 3172 |
|
|
cpuState <= STATE_WR4H;
|
| 3173 |
|
|
elsif opcode(5) = '1' then
|
| 3174 |
|
|
dataout <= theRegisters(5)(15 downto 0);
|
| 3175 |
|
|
cpuState <= STATE_WR5H;
|
| 3176 |
|
|
elsif opcode(6) = '1' then
|
| 3177 |
|
|
dataout <= theRegisters(6)(15 downto 0);
|
| 3178 |
|
|
cpuState <= STATE_WR6H;
|
| 3179 |
|
|
else
|
| 3180 |
|
|
dataout <= theRegisters(7)(15 downto 0);
|
| 3181 |
|
|
cpuState <= STATE_WR7H;
|
| 3182 |
|
|
end if;
|
| 3183 |
|
|
end if;
|
| 3184 |
|
|
|
| 3185 |
|
|
when others =>
|
| 3186 |
|
|
writeL <= '1';
|
| 3187 |
|
|
writeH <= '1';
|
| 3188 |
|
|
cpuState <= STATE_FETCH;
|
| 3189 |
|
|
end case; -- unitControl2
|
| 3190 |
|
|
|
| 3191 |
|
|
when STATE_WR1H => -- ##################################################
|
| 3192 |
|
|
case unitControl2 is
|
| 3193 |
|
|
when CODE_PUSH1 =>
|
| 3194 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 3195 |
|
|
dataout <= theRegisters(1)(15 downto 0);
|
| 3196 |
|
|
cpuState <= STATE_WR1L;
|
| 3197 |
|
|
when CODE_STMIA1 =>
|
| 3198 |
|
|
address <= address + 2;
|
| 3199 |
|
|
dataout <= theRegisters(1)(31 downto 16);
|
| 3200 |
|
|
cpuState <= STATE_WR1L;
|
| 3201 |
|
|
|
| 3202 |
|
|
when others =>
|
| 3203 |
|
|
writeL <= '1';
|
| 3204 |
|
|
writeH <= '1';
|
| 3205 |
|
|
cpuState <= STATE_FETCH;
|
| 3206 |
|
|
end case; -- unitControl2
|
| 3207 |
|
|
|
| 3208 |
|
|
when STATE_WR1L => -- ##################################################
|
| 3209 |
|
|
case unitControl2 is
|
| 3210 |
|
|
when CODE_PUSH1 =>
|
| 3211 |
|
|
if opcode(0) = '0' then
|
| 3212 |
|
|
writeL <= '1';
|
| 3213 |
|
|
writeH <= '1';
|
| 3214 |
|
|
addrMux <= ADDR_PC;
|
| 3215 |
|
|
cpuState <= STATE_FETCH;
|
| 3216 |
|
|
else
|
| 3217 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 3218 |
|
|
dataout <= theRegisters(0)(31 downto 16);
|
| 3219 |
|
|
cpuState <= STATE_WR0H;
|
| 3220 |
|
|
end if;
|
| 3221 |
|
|
when CODE_STMIA1 =>
|
| 3222 |
|
|
address <= address + 2;
|
| 3223 |
|
|
if opcode(7 downto 2) = 0 then
|
| 3224 |
|
|
writeL <= '1';
|
| 3225 |
|
|
writeH <= '1';
|
| 3226 |
|
|
addrMux <= ADDR_PC;
|
| 3227 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 3228 |
|
|
cpuState <= STATE_FETCH;
|
| 3229 |
|
|
else
|
| 3230 |
|
|
if opcode(2) = '1' then
|
| 3231 |
|
|
dataout <= theRegisters(2)(15 downto 0);
|
| 3232 |
|
|
cpuState <= STATE_WR2H;
|
| 3233 |
|
|
elsif opcode(3) = '1' then
|
| 3234 |
|
|
dataout <= theRegisters(3)(15 downto 0);
|
| 3235 |
|
|
cpuState <= STATE_WR3H;
|
| 3236 |
|
|
elsif opcode(4) = '1' then
|
| 3237 |
|
|
dataout <= theRegisters(4)(15 downto 0);
|
| 3238 |
|
|
cpuState <= STATE_WR4H;
|
| 3239 |
|
|
elsif opcode(5) = '1' then
|
| 3240 |
|
|
dataout <= theRegisters(5)(15 downto 0);
|
| 3241 |
|
|
cpuState <= STATE_WR5H;
|
| 3242 |
|
|
elsif opcode(6) = '1' then
|
| 3243 |
|
|
dataout <= theRegisters(6)(15 downto 0);
|
| 3244 |
|
|
cpuState <= STATE_WR6H;
|
| 3245 |
|
|
else
|
| 3246 |
|
|
dataout <= theRegisters(7)(15 downto 0);
|
| 3247 |
|
|
cpuState <= STATE_WR7H;
|
| 3248 |
|
|
end if;
|
| 3249 |
|
|
end if;
|
| 3250 |
|
|
|
| 3251 |
|
|
when others =>
|
| 3252 |
|
|
writeL <= '1';
|
| 3253 |
|
|
writeH <= '1';
|
| 3254 |
|
|
cpuState <= STATE_FETCH;
|
| 3255 |
|
|
end case; -- unitControl2
|
| 3256 |
|
|
|
| 3257 |
|
|
when STATE_WR0H => -- ##################################################
|
| 3258 |
|
|
case unitControl2 is
|
| 3259 |
|
|
when CODE_PUSH1 =>
|
| 3260 |
|
|
theRegisters(13) <= theRegisters(13) - 2;
|
| 3261 |
|
|
dataout <= theRegisters(0)(15 downto 0);
|
| 3262 |
|
|
cpuState <= STATE_WR0L;
|
| 3263 |
|
|
when CODE_STMIA1 =>
|
| 3264 |
|
|
address <= address + 2;
|
| 3265 |
|
|
dataout <= theRegisters(0)(31 downto 16);
|
| 3266 |
|
|
cpuState <= STATE_WR0L;
|
| 3267 |
|
|
|
| 3268 |
|
|
|
| 3269 |
|
|
when others =>
|
| 3270 |
|
|
writeL <= '1';
|
| 3271 |
|
|
writeH <= '1';
|
| 3272 |
|
|
cpuState <= STATE_FETCH;
|
| 3273 |
|
|
end case; -- unitControl2
|
| 3274 |
|
|
|
| 3275 |
|
|
when STATE_WR0L => -- ##################################################
|
| 3276 |
|
|
case unitControl2 is
|
| 3277 |
|
|
when CODE_PUSH1 =>
|
| 3278 |
|
|
writeL <= '1';
|
| 3279 |
|
|
writeH <= '1';
|
| 3280 |
|
|
addrMux <= ADDR_PC;
|
| 3281 |
|
|
cpuState <= STATE_FETCH;
|
| 3282 |
|
|
when CODE_STMIA1 =>
|
| 3283 |
|
|
address <= address + 2;
|
| 3284 |
|
|
if opcode(7 downto 1) = 0 then
|
| 3285 |
|
|
writeL <= '1';
|
| 3286 |
|
|
writeH <= '1';
|
| 3287 |
|
|
addrMux <= ADDR_PC;
|
| 3288 |
|
|
theRegisters(opcode108) <= address + 2;
|
| 3289 |
|
|
cpuState <= STATE_FETCH;
|
| 3290 |
|
|
else
|
| 3291 |
|
|
if opcode(1) = '1' then
|
| 3292 |
|
|
dataout <= theRegisters(1)(15 downto 0);
|
| 3293 |
|
|
cpuState <= STATE_WR1H;
|
| 3294 |
|
|
elsif opcode(2) = '1' then
|
| 3295 |
|
|
dataout <= theRegisters(2)(15 downto 0);
|
| 3296 |
|
|
cpuState <= STATE_WR2H;
|
| 3297 |
|
|
elsif opcode(3) = '1' then
|
| 3298 |
|
|
dataout <= theRegisters(3)(15 downto 0);
|
| 3299 |
|
|
cpuState <= STATE_WR3H;
|
| 3300 |
|
|
elsif opcode(4) = '1' then
|
| 3301 |
|
|
dataout <= theRegisters(4)(15 downto 0);
|
| 3302 |
|
|
cpuState <= STATE_WR4H;
|
| 3303 |
|
|
elsif opcode(5) = '1' then
|
| 3304 |
|
|
dataout <= theRegisters(5)(15 downto 0);
|
| 3305 |
|
|
cpuState <= STATE_WR5H;
|
| 3306 |
|
|
elsif opcode(6) = '1' then
|
| 3307 |
|
|
dataout <= theRegisters(6)(15 downto 0);
|
| 3308 |
|
|
cpuState <= STATE_WR6H;
|
| 3309 |
|
|
else
|
| 3310 |
|
|
dataout <= theRegisters(7)(15 downto 0);
|
| 3311 |
|
|
cpuState <= STATE_WR7H;
|
| 3312 |
|
|
end if;
|
| 3313 |
|
|
end if;
|
| 3314 |
|
|
|
| 3315 |
|
|
when others =>
|
| 3316 |
|
|
writeL <= '1';
|
| 3317 |
|
|
writeH <= '1';
|
| 3318 |
|
|
cpuState <= STATE_FETCH;
|
| 3319 |
|
|
end case; -- unitControl2
|
| 3320 |
|
|
|
| 3321 |
|
|
|
| 3322 |
|
|
|
| 3323 |
|
|
when others =>
|
| 3324 |
|
|
cpuState <= STATE_FETCH;
|
| 3325 |
|
|
end case; -- cpuState
|
| 3326 |
|
|
end if; -- rst = '0'
|
| 3327 |
|
|
end if; -- rising_edge(clk)
|
| 3328 |
|
|
end process;
|
| 3329 |
|
|
|
| 3330 |
|
|
|
| 3331 |
|
|
end behavior;
|
