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riedelx |
-- http://www.cs.umbc.edu/help/VHDL/samples/samples.shtml
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-- mul32c.vhdl parallel multiply 32 bit x 32 bit to get 64 bit unsigned product
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-- uses add32 component and fadd component, includes carry save
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-- uses VHDL 'generate' to have less statements
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity add32csa is -- one stage of carry save adder for multiplier
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port(
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b : in std_logic; -- a multiplier bit
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a : in std_logic_vector(31 downto 0); -- multiplicand
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sum_in : in std_logic_vector(31 downto 0); -- sums from previous stage
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cin : in std_logic_vector(31 downto 0); -- carrys from previous stage
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sum_out : out std_logic_vector(31 downto 0); -- sums to next stage
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cout : out std_logic_vector(31 downto 0)); -- carrys to next stage
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end add32csa;
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architecture circuits of add32csa is
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signal zero : std_logic_vector(31 downto 0) := X"00000000";
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signal aa : std_logic_vector(31 downto 0) := X"00000000";
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component fadd -- duplicates entity port
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port(a : in std_logic;
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b : in std_logic;
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cin : in std_logic;
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s : out std_logic;
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cout : out std_logic);
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end component fadd;
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begin -- circuits of add32csa
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aa <= a when b='1' else zero after 1 ns;
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stage: for I in 0 to 31 generate
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sta: fadd port map(aa(I), sum_in(I), cin(I) , sum_out(I), cout(I));
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end generate stage;
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end architecture circuits; -- of add32csa
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity mul32c is -- 32 x 32 = 64 bit unsigned product multiplier
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port(a : in std_logic_vector(31 downto 0); -- multiplicand
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b : in std_logic_vector(31 downto 0); -- multiplier
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prod : out std_logic_vector(63 downto 0)); -- product
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end mul32c;
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architecture circuits of mul32c is
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signal zero : std_logic_vector(31 downto 0) := X"00000000";
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signal nc1 : std_logic;
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type arr32 is array(0 to 31) of std_logic_vector(31 downto 0);
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signal s : arr32; -- partial sums
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signal c : arr32; -- partial carries
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signal ss : arr32; -- shifted sums
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component add32csa is -- duplicate entity port
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port(b : in std_logic;
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a : in std_logic_vector(31 downto 0);
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sum_in : in std_logic_vector(31 downto 0);
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cin : in std_logic_vector(31 downto 0);
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sum_out : out std_logic_vector(31 downto 0);
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cout : out std_logic_vector(31 downto 0));
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end component add32csa;
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component add32 -- duplicate entity port
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port(a : in std_logic_vector(31 downto 0);
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b : in std_logic_vector(31 downto 0);
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cin : in std_logic;
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sum : out std_logic_vector(31 downto 0);
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cout : out std_logic);
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end component add32;
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begin -- circuits of mul32c
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st0: add32csa port map(b(0), a, zero , zero, s(0), c(0)); -- CSA stage
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ss(0) <= '0'&s(0)(31 downto 1) after 1 ns;
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prod(0) <= s(0)(0) after 1 ns;
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stage: for I in 1 to 31 generate
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st: add32csa port map(b(I), a, ss(I-1) , c(I-1), s(I), c(I)); -- CSA stage
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ss(I) <= '0'&s(I)(31 downto 1) after 1 ns;
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prod(I) <= s(I)(0) after 1 ns;
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end generate stage;
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add: add32 port map(ss(31), c(31), '0' , prod(63 downto 32), nc1); -- adder
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end architecture circuits; -- of mul32c
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