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[/] [cortexi/] [trunk/] [uart.vhd] - Blame information for rev 9

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1 9 riedelx 
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- uart baudrate
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-- baudrate register = 1  =>  clk / 8
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-- baudrate register = 2  =>  clk / 12
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-- baudrate register = N  =>  clk / ((N + 1) * 4)
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entity uart is
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    Port ( clk     : in  std_logic;
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           rst     : in  std_logic;
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           datain  : in  std_logic_vector(7 downto 0);
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           dataout : out std_logic_vector(7 downto 0);
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           addr    : in  std_logic_vector(2 downto 0);
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           cs      : in  std_logic;
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           wr      : in  std_logic;
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           serIn   : in  std_logic;
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           serOut  : out std_logic);
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end uart;
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architecture Behavioral of uart is
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  type UARTregisters is array (0 to 7) of std_logic_vector(7 downto 0);
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  signal registers : UARTregisters;
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  signal txBaud    : std_logic_vector(15 downto 0);
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  signal rxBaud    : std_logic_vector(15 downto 0);
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  signal txFSM     : std_logic_vector(3 downto 0);
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  signal rxFSM     : std_logic_vector(3 downto 0);
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  signal txTick    : std_logic_vector(2 downto 0);
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  signal rxTick    : std_logic_vector(2 downto 0);
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  signal txBit     : std_logic_vector(2 downto 0);
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  signal rxBit     : std_logic_vector(2 downto 0);
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  signal sendRequest : std_logic;
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  signal serInput  : std_logic;
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begin
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  process(clk, rst)
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  begin
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    if falling_edge(clk) then
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      if rst = '0' then
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        for i in 0 to 7 loop
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          registers(i) <= x"00";
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        end loop;
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        txBaud      <= x"0000";
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        rxBaud      <= x"0000";
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        dataout     <= x"00";
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        sendRequest <= '0';
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        txFSM  <= "0000";
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        rxFSM  <= "0000";
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        txTick <= "000";
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        rxTick <= "000";
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        txBit  <= "000";
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        rxBit  <= "000";
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        serOut <= '1';
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        serInput <= '1';
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      else
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        serInput <= serIn;
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-------- access to UART registers -----------------------
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        if cs = '0' then   -- uart selected
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          if wr = '0' then -- write access
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            registers(conv_integer(addr)) <= datain;
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            if addr = "000" then
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              sendRequest <= '1';
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            end if;
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          else
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            if addr = "001" then
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              registers(4)(1) <= '0'; -- data ready
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              registers(4)(2) <= '0'; -- frame error
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            end if;
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            dataout <= registers(conv_integer(addr));
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          end if;
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        end if;
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-------- baudrate ---------------------------------------
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        txBaud <= txBaud + 1;
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        if txBaud = (registers(2) & registers(3)) then
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          txBaud <= x"0000";
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        end if;
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        rxBaud <= rxBaud + 1;
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        if rxBaud = (registers(2) & registers(3)) then
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          rxBaud <= x"0000";
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        end if;
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-------- transmitter ------------------------------------
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        case txFSM is
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          when "0000" => --##### tx idle #####
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            if sendRequest = '1' then
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              registers(4)(0) <= '1'; -- tx busy
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              sendRequest <= '0';
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              txFSM  <= "0001";
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              txBaud <= x"0000";
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              txTick <= "000";
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              txBit  <= "000";
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              serOut <= '0';  -- start bit
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            end if;
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          when "0001" => --##### send start bit #####
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            if txBaud = x"0000" then
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              txTick <= txTick + 1;
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              if txTick = "011" then
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                txTick <= "000";
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                txFSM  <= "0010";
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                serOut <= registers(0)(conv_integer(txBit));
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                txBit  <= txBit + 1;
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              end if;
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            end if;
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          when "0010" => --##### send data bits #####
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            if txBaud = x"0000" then
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              txTick <= txTick + 1;
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              if txTick = "011" then
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                txTick <= "000";
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                serOut <= registers(0)(conv_integer(txBit));
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                txBit  <= txBit + 1;
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                if txBit = "111" then
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                  txFSM <= "0011";
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                end if;
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              end if;
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            end if;
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          when "0011" => --##### send stop bit #####
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            if txBaud = x"0000" then
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              txTick <= txTick + 1;
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              if txTick = "011" then
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                txTick <= "000";
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                serOut <= '1';
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                txFSM  <= "0100";
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              end if;
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            end if;
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          when "0100" => --##### finishing stop bit #####
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            if txBaud = x"0000" then
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              txTick <= txTick + 1;
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              if txTick = "011" then
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                txFSM <= "0000";
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                registers(4)(0) <= '0'; -- tx ready
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              end if;
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            end if;
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          when others =>
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            txFSM <= "0000";
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        end case; -- txFSM
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-------- receiver ------------------------------------
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        case rxFSM is
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          when "0000" => --##### awaiting start bit #####
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            if serInput = '0' then
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              rxBaud <= x"0000";
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              rxTick <= "000";
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              rxFSM  <= "0001";
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            end if;
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          when "0001" => --##### cnt to middle start bit #####
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            if rxBaud = x"0000" then
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              rxTick <= rxTick + 1;
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              if rxTick = "001" then
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                if serInput = '1' then -- false start bit
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                  rxFSM <= "0000";
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                else
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                  rxTick <= "000";
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                  rxBit  <= "000";
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                  rxFSM  <= "0010";
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                end if;
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              end if;
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            end if;
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          when "0010" => --##### receive bits ######
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            if rxBaud = x"0000" then
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              rxTick <= rxTick + 1;
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              if rxTick = "011" then
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                rxTick <= "000";
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                registers(1)(conv_integer(rxBit)) <= serInput;
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                rxBit <= rxBit + 1;
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                if rxBit = "111" then -- last bit
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                  rxFSM <= "0011";
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                end if;
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              end if;
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            end if;
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          when "0011" => --##### receive stop bit #####
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            if rxBaud = x"0000" then
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              rxTick <= rxTick + 1;
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              if rxTick = "011" then
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                if serInput = '0' then
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                  registers(4)(2) <= '1'; -- frame error
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                else
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                  registers(4)(1) <= '1'; -- data ready
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                end if;
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                rxFSM <= "0000";
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              end if;
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            end if;
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          when others =>
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            rxFSM <= "0000";
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        end case; -- rxFSM
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      end if; -- rst = '0'
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    end if; -- rising_edge(clk)
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  end process;
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end Behavioral;

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