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[/] [cowgirl/] [trunk/] [arithmetic.vhdl] - Blame information for rev 4

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1 2 thebeekeep
-- ALU
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-- 10/24/05
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-- Everything here works except for division
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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entity arithmetic is port(
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  a:    in signed(15 downto 0);
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  b:    in signed(15 downto 0);
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  fcn:  in std_logic_vector(2 downto 0);
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  o:    out signed(15 downto 0);
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  m_o:  out signed(31 downto 0)
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  );
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end arithmetic;
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architecture arith_arch of arithmetic is
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  signal temp: signed(31 downto 0);
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begin
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  arith_logic: process(fcn, a, b)
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  begin
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    case fcn is
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      when "000" =>                     -- add
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        o <= a + b;
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      when "001" =>                     -- subtract
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        o <= a - b;
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      when "010" =>                     -- multiply
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        m_o <= a * b;
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      when "011" =>                     -- divide
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        --o <= a / b;
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      when "100" =>                     -- 2's complement inverse
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        o <= signed((not std_logic_vector(a))) + '1';
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      when others =>
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        o <= x"0000";
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    end case;
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  end process arith_logic;
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end arith_arch;

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